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5c9efb36 | 1 | /* |
1b77ca8a | 2 | * Copyright 2006, 2010-2011 Freescale Semiconductor. |
5c9efb36 | 3 | * |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
debb7354 JL |
7 | */ |
8 | ||
9 | /* | |
5c9efb36 | 10 | * MPC8641HPCN board configuration file |
debb7354 JL |
11 | * |
12 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 13 | * search for CONFIG_SERVERIP, etc. in this file. |
debb7354 JL |
14 | */ |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
15672c6d YS |
19 | #define CONFIG_DISPLAY_BOARDINFO |
20 | ||
debb7354 | 21 | /* High Level Configuration Options */ |
debb7354 JL |
22 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ |
23 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
7649a590 | 24 | #define CONFIG_MP 1 /* support multiple processors */ |
53677ef1 | 25 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
3111d32c | 26 | /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ |
d591a80e | 27 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
debb7354 | 28 | |
2ae18241 WD |
29 | /* |
30 | * default CCSRBAR is at 0xff700000 | |
31 | * assume U-Boot is less than 0.5MB | |
32 | */ | |
33 | #define CONFIG_SYS_TEXT_BASE 0xeff00000 | |
34 | ||
debb7354 | 35 | #ifdef RUN_DIAG |
6bf98b13 | 36 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
debb7354 | 37 | #endif |
5c9efb36 | 38 | |
1266df88 BB |
39 | /* |
40 | * virtual address to be used for temporary mappings. There | |
41 | * should be 128k free at this VA. | |
42 | */ | |
43 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
44 | ||
1b77ca8a KG |
45 | #define CONFIG_SYS_SRIO |
46 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
af5d100e | 47 | |
63cec581 | 48 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
46f3e385 KG |
49 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ |
50 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ | |
63cec581 | 51 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
8ba93f68 | 52 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
4933b91f | 53 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
5c9efb36 | 54 | |
53677ef1 | 55 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
debb7354 | 56 | #define CONFIG_ENV_OVERWRITE |
debb7354 | 57 | |
4bbfd3e2 | 58 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
31d82672 | 59 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
d591a80e | 60 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
debb7354 | 61 | |
53677ef1 | 62 | #define CONFIG_ALTIVEC 1 |
debb7354 | 63 | |
5c9efb36 | 64 | /* |
debb7354 JL |
65 | * L2CR setup -- make sure this is right for your board! |
66 | */ | |
6d0f6bcf | 67 | #define CONFIG_SYS_L2 |
debb7354 JL |
68 | #define L2_INIT 0 |
69 | #define L2_ENABLE (L2CR_L2E) | |
70 | ||
71 | #ifndef CONFIG_SYS_CLK_FREQ | |
63cec581 ES |
72 | #ifndef __ASSEMBLY__ |
73 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
74 | #endif | |
53677ef1 | 75 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
debb7354 JL |
76 | #endif |
77 | ||
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
79 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
debb7354 | 80 | |
3111d32c BB |
81 | /* |
82 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
83 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
84 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
85 | */ | |
86 | #ifdef CONFIG_PHYS_64BIT | |
1605cc9e | 87 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f |
3111d32c | 88 | #else |
1605cc9e | 89 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 |
3111d32c BB |
90 | #endif |
91 | ||
debb7354 JL |
92 | /* |
93 | * Base addresses -- Note these are effective addresses where the | |
94 | * actual resources get mapped (not physical addresses) | |
95 | */ | |
6d0f6bcf | 96 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
c759a01a | 97 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
6d0f6bcf | 98 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
debb7354 | 99 | |
3111d32c BB |
100 | /* Physical addresses */ |
101 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
1605cc9e BB |
102 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH |
103 | #define CONFIG_SYS_CCSRBAR_PHYS \ | |
104 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ | |
105 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) | |
3111d32c | 106 | |
076bff8f YS |
107 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
108 | ||
debb7354 JL |
109 | /* |
110 | * DDR Setup | |
111 | */ | |
5614e71b | 112 | #define CONFIG_SYS_FSL_DDR2 |
6a8e5692 KG |
113 | #undef CONFIG_FSL_DDR_INTERACTIVE |
114 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
115 | #define CONFIG_DDR_SPD | |
116 | ||
117 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
118 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
119 | ||
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
121 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1266df88 | 122 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
fcb28e76 | 123 | #define CONFIG_VERY_BIG_RAM |
debb7354 | 124 | |
6a8e5692 KG |
125 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
126 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
127 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
128 | ||
129 | /* | |
130 | * I2C addresses of SPD EEPROMs | |
131 | */ | |
132 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
133 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
134 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
135 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
136 | ||
137 | ||
138 | /* | |
139 | * These are used when DDR doesn't use SPD. | |
140 | */ | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
142 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
143 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
144 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
145 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
146 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
147 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
148 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
149 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
150 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
151 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
152 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
153 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
154 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
155 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
156 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
6a8e5692 | 157 | |
ad8f8687 | 158 | #define CONFIG_ID_EEPROM |
6d0f6bcf | 159 | #define CONFIG_SYS_I2C_EEPROM_NXID |
32628c50 | 160 | #define CONFIG_ID_EEPROM |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
162 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
debb7354 | 163 | |
c759a01a | 164 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
1605cc9e BB |
165 | #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE |
166 | #define CONFIG_SYS_FLASH_BASE_PHYS \ | |
167 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ | |
168 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
3111d32c | 169 | |
b81b773e | 170 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
debb7354 | 171 | |
3111d32c BB |
172 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
173 | | 0x00001001) /* port size 16bit */ | |
174 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
debb7354 | 175 | |
3111d32c BB |
176 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
177 | | 0x00001001) /* port size 16bit */ | |
178 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
debb7354 | 179 | |
3111d32c BB |
180 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
181 | | 0x00000801) /* port size 8bit */ | |
182 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
debb7354 | 183 | |
c759a01a BB |
184 | /* |
185 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
186 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
187 | * required for the smallest BAT mapping, so there's a 64k hole. | |
188 | */ | |
189 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
1605cc9e | 190 | #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE |
debb7354 | 191 | |
7608d75f | 192 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
c759a01a | 193 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
1605cc9e BB |
194 | #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) |
195 | #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ | |
196 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
c759a01a | 197 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
5c9efb36 JL |
198 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
199 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
200 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
201 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
202 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
203 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
204 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
205 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
206 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
207 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
9af9c6bd KG |
208 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
209 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
5c9efb36 JL |
210 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
211 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
212 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
213 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 214 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
debb7354 | 215 | |
b5431560 | 216 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
c759a01a | 217 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
3111d32c | 218 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
b5431560 | 219 | |
170deacb | 220 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6d0f6bcf | 221 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
debb7354 | 222 | |
6d0f6bcf JCPV |
223 | #undef CONFIG_SYS_FLASH_CHECKSUM |
224 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
225 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
14d0a02a | 226 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bf9a8c34 | 227 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
debb7354 | 228 | |
00b1883a | 229 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_FLASH_CFI |
231 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
debb7354 | 232 | |
6d0f6bcf JCPV |
233 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
234 | #define CONFIG_SYS_RAMBOOT | |
debb7354 | 235 | #else |
6d0f6bcf | 236 | #undef CONFIG_SYS_RAMBOOT |
debb7354 JL |
237 | #endif |
238 | ||
6d0f6bcf | 239 | #if defined(CONFIG_SYS_RAMBOOT) |
fa7db9c3 | 240 | #undef CONFIG_SPD_EEPROM |
6d0f6bcf | 241 | #define CONFIG_SYS_SDRAM_SIZE 256 |
debb7354 JL |
242 | #endif |
243 | ||
244 | #undef CONFIG_CLOCKS_IN_MHZ | |
245 | ||
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
247 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
248 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
debb7354 | 249 | #else |
6d0f6bcf | 250 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
debb7354 | 251 | #endif |
553f0982 | 252 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
debb7354 | 253 | |
25ddd1fb | 254 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 255 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
debb7354 | 256 | |
221fbd22 | 257 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
6d0f6bcf | 258 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
debb7354 JL |
259 | |
260 | /* Serial Port */ | |
261 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_NS16550_SERIAL |
263 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
264 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
debb7354 | 265 | |
6d0f6bcf | 266 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
debb7354 JL |
267 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
268 | ||
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
270 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
debb7354 | 271 | |
586d1d5a JL |
272 | /* |
273 | * I2C | |
274 | */ | |
00f792e0 HS |
275 | #define CONFIG_SYS_I2C |
276 | #define CONFIG_SYS_I2C_FSL | |
277 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
278 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
279 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
280 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
debb7354 | 281 | |
586d1d5a JL |
282 | /* |
283 | * RapidIO MMU | |
284 | */ | |
1b77ca8a | 285 | #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ |
3111d32c | 286 | #ifdef CONFIG_PHYS_64BIT |
1605cc9e BB |
287 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 |
288 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c | |
3111d32c | 289 | #else |
1605cc9e BB |
290 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE |
291 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 | |
3111d32c | 292 | #endif |
1605cc9e BB |
293 | #define CONFIG_SYS_SRIO1_MEM_PHYS \ |
294 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ | |
295 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) | |
1b77ca8a | 296 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
debb7354 JL |
297 | |
298 | /* | |
299 | * General PCI | |
300 | * Addresses are mapped 1-1. | |
301 | */ | |
49f46f3b | 302 | |
64e55d5e | 303 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
46f3e385 | 304 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
3111d32c | 305 | #ifdef CONFIG_PHYS_64BIT |
46f3e385 | 306 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
1605cc9e BB |
307 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 |
308 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c | |
3111d32c | 309 | #else |
46f3e385 | 310 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
1605cc9e BB |
311 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT |
312 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 | |
3111d32c | 313 | #endif |
1605cc9e BB |
314 | #define CONFIG_SYS_PCIE1_MEM_PHYS \ |
315 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ | |
316 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) | |
46f3e385 KG |
317 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
318 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
319 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
1605cc9e BB |
320 | #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT |
321 | #define CONFIG_SYS_PCIE1_IO_PHYS \ | |
322 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ | |
323 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
46f3e385 | 324 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
debb7354 | 325 | |
4c78d4a6 BB |
326 | #ifdef CONFIG_PHYS_64BIT |
327 | /* | |
46f3e385 | 328 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
4c78d4a6 BB |
329 | * This will increase the amount of PCI address space available for |
330 | * for mapping RAM. | |
331 | */ | |
46f3e385 | 332 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
4c78d4a6 | 333 | #else |
46f3e385 KG |
334 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
335 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
4c78d4a6 | 336 | #endif |
46f3e385 KG |
337 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
338 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
1605cc9e BB |
339 | #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ |
340 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
341 | #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH | |
46f3e385 KG |
342 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ |
343 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
344 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
345 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
346 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
347 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
1605cc9e BB |
348 | #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ |
349 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
46f3e385 KG |
350 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ |
351 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
352 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
debb7354 | 353 | |
debb7354 JL |
354 | #if defined(CONFIG_PCI) |
355 | ||
53677ef1 | 356 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 357 | |
6d0f6bcf | 358 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
debb7354 | 359 | |
53677ef1 | 360 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
debb7354 | 361 | |
debb7354 | 362 | |
debb7354 JL |
363 | #undef CONFIG_EEPRO100 |
364 | #undef CONFIG_TULIP | |
365 | ||
a81d1c0b ZW |
366 | /************************************************************ |
367 | * USB support | |
368 | ************************************************************/ | |
53677ef1 | 369 | #define CONFIG_PCI_OHCI 1 |
a81d1c0b | 370 | #define CONFIG_USB_OHCI_NEW 1 |
53677ef1 | 371 | #define CONFIG_USB_KEYBOARD 1 |
52cb4d4f | 372 | #define CONFIG_SYS_STDIO_DEREGISTER |
6d0f6bcf JCPV |
373 | #define CONFIG_SYS_USB_EVENT_POLL 1 |
374 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
375 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
376 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
a81d1c0b | 377 | |
0f460a1e | 378 | /*PCIE video card used*/ |
46f3e385 | 379 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
380 | |
381 | /*PCI video card used*/ | |
46f3e385 | 382 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
0f460a1e JJ |
383 | |
384 | /* video */ | |
385 | #define CONFIG_VIDEO | |
386 | ||
387 | #if defined(CONFIG_VIDEO) | |
388 | #define CONFIG_BIOSEMU | |
389 | #define CONFIG_CFB_CONSOLE | |
390 | #define CONFIG_VIDEO_SW_CURSOR | |
391 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
392 | #define CONFIG_ATI_RADEON_FB | |
393 | #define CONFIG_VIDEO_LOGO | |
46f3e385 | 394 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
395 | #endif |
396 | ||
debb7354 | 397 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 398 | |
dabf9ef8 JZ |
399 | #define CONFIG_DOS_PARTITION |
400 | #define CONFIG_SCSI_AHCI | |
401 | ||
402 | #ifdef CONFIG_SCSI_AHCI | |
344ca0b4 | 403 | #define CONFIG_LIBATA |
dabf9ef8 | 404 | #define CONFIG_SATA_ULI5288 |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
406 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
407 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
408 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
dabf9ef8 JZ |
409 | #endif |
410 | ||
debb7354 JL |
411 | #endif /* CONFIG_PCI */ |
412 | ||
debb7354 JL |
413 | #if defined(CONFIG_TSEC_ENET) |
414 | ||
debb7354 JL |
415 | #define CONFIG_MII 1 /* MII PHY management */ |
416 | ||
53677ef1 WD |
417 | #define CONFIG_TSEC1 1 |
418 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
419 | #define CONFIG_TSEC2 1 | |
420 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
421 | #define CONFIG_TSEC3 1 | |
422 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
423 | #define CONFIG_TSEC4 1 | |
424 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
debb7354 | 425 | |
debb7354 JL |
426 | #define TSEC1_PHY_ADDR 0 |
427 | #define TSEC2_PHY_ADDR 1 | |
428 | #define TSEC3_PHY_ADDR 2 | |
429 | #define TSEC4_PHY_ADDR 3 | |
430 | #define TSEC1_PHYIDX 0 | |
431 | #define TSEC2_PHYIDX 0 | |
432 | #define TSEC3_PHYIDX 0 | |
433 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
434 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
435 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
436 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
437 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
debb7354 JL |
438 | |
439 | #define CONFIG_ETHPRIME "eTSEC1" | |
440 | ||
441 | #endif /* CONFIG_TSEC_ENET */ | |
442 | ||
3111d32c | 443 | |
1605cc9e | 444 | #ifdef CONFIG_PHYS_64BIT |
3111d32c BB |
445 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) |
446 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
447 | ||
1605cc9e BB |
448 | /* Put physical address into the BAT format */ |
449 | #define BAT_PHYS_ADDR(low, high) \ | |
450 | (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) | |
451 | /* Convert high/low pairs to actual 64-bit value */ | |
452 | #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) | |
453 | #else | |
454 | /* 32-bit systems just ignore the "high" bits */ | |
455 | #define BAT_PHYS_ADDR(low, high) (low) | |
456 | #define PAIRED_PHYS_TO_PHYS(low, high) (low) | |
457 | #endif | |
458 | ||
586d1d5a | 459 | /* |
c759a01a | 460 | * BAT0 DDR |
debb7354 | 461 | */ |
6d0f6bcf | 462 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
9ff32d8c | 463 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
debb7354 | 464 | |
586d1d5a | 465 | /* |
c759a01a | 466 | * BAT1 LBC (PIXIS/CF) |
af5d100e | 467 | */ |
1605cc9e BB |
468 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
469 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
470 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
471 | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
472 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
473 | | BATU_VS | BATU_VP) | |
1605cc9e BB |
474 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
475 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 476 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
c759a01a | 477 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
af5d100e BB |
478 | |
479 | /* if CONFIG_PCI: | |
46f3e385 | 480 | * BAT2 PCIE1 and PCIE1 MEM |
af5d100e | 481 | * if CONFIG_RIO |
c759a01a | 482 | * BAT2 Rapidio Memory |
debb7354 | 483 | */ |
af5d100e | 484 | #ifdef CONFIG_PCI |
842033e6 | 485 | #define CONFIG_PCI_INDIRECT_BRIDGE |
1605cc9e BB |
486 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
487 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
3111d32c BB |
488 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
489 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 490 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
af5d100e | 491 | | BATU_VS | BATU_VP) |
1605cc9e BB |
492 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
493 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
3111d32c | 494 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
af5d100e BB |
495 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
496 | #else /* CONFIG_RIO */ | |
1605cc9e BB |
497 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
498 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
3111d32c BB |
499 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
500 | BATL_GUARDEDSTORAGE) | |
1b77ca8a | 501 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ |
3111d32c | 502 | | BATU_VS | BATU_VP) |
1605cc9e BB |
503 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
504 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
3111d32c | 505 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 506 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
af5d100e | 507 | #endif |
debb7354 | 508 | |
586d1d5a | 509 | /* |
c759a01a | 510 | * BAT3 CCSR Space |
debb7354 | 511 | */ |
1605cc9e BB |
512 | #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
513 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
3111d32c BB |
514 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
515 | | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
516 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
517 | | BATU_VP) | |
1605cc9e BB |
518 | #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
519 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
3111d32c | 520 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 521 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
debb7354 | 522 | |
3111d32c BB |
523 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
524 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
525 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
526 | | BATL_GUARDEDSTORAGE) | |
527 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
528 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
529 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
530 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
531 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
532 | #endif | |
533 | ||
586d1d5a | 534 | /* |
46f3e385 | 535 | * BAT4 PCIE1_IO and PCIE2_IO |
debb7354 | 536 | */ |
1605cc9e BB |
537 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
538 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
539 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
540 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 541 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
c759a01a | 542 | | BATU_VS | BATU_VP) |
1605cc9e BB |
543 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
544 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 545 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 546 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
debb7354 | 547 | |
586d1d5a | 548 | /* |
c759a01a | 549 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
debb7354 | 550 | */ |
6d0f6bcf JCPV |
551 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
552 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
553 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
554 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
debb7354 | 555 | |
586d1d5a | 556 | /* |
c759a01a | 557 | * BAT6 FLASH |
debb7354 | 558 | */ |
1605cc9e BB |
559 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
560 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
561 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
562 | | BATL_GUARDEDSTORAGE) | |
170deacb BB |
563 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
564 | | BATU_VP) | |
1605cc9e BB |
565 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
566 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 567 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
6d0f6bcf | 568 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
debb7354 | 569 | |
bf9a8c34 BB |
570 | /* Map the last 1M of flash where we're running from reset */ |
571 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
572 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
14d0a02a | 573 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
bf9a8c34 BB |
574 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
575 | | BATL_MEMCOHERENCE) | |
576 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
577 | ||
c759a01a BB |
578 | /* |
579 | * BAT7 FREE - used later for tmp mappings | |
580 | */ | |
6d0f6bcf JCPV |
581 | #define CONFIG_SYS_DBAT7L 0x00000000 |
582 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
583 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
584 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
debb7354 | 585 | |
debb7354 JL |
586 | /* |
587 | * Environment | |
588 | */ | |
6d0f6bcf | 589 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 590 | #define CONFIG_ENV_IS_IN_FLASH 1 |
221fbd22 SW |
591 | #define CONFIG_ENV_ADDR \ |
592 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 593 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
5c9efb36 | 594 | #else |
93f6d725 | 595 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 596 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
5c9efb36 | 597 | #endif |
0f2d6602 | 598 | #define CONFIG_ENV_SIZE 0x2000 |
debb7354 JL |
599 | |
600 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 601 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
debb7354 | 602 | |
2f9c19e4 | 603 | |
659e2f67 JL |
604 | /* |
605 | * BOOTP options | |
606 | */ | |
607 | #define CONFIG_BOOTP_BOOTFILESIZE | |
608 | #define CONFIG_BOOTP_BOOTPATH | |
609 | #define CONFIG_BOOTP_GATEWAY | |
610 | #define CONFIG_BOOTP_HOSTNAME | |
611 | ||
612 | ||
2f9c19e4 JL |
613 | /* |
614 | * Command line configuration. | |
615 | */ | |
2f9c19e4 JL |
616 | #define CONFIG_CMD_PING |
617 | #define CONFIG_CMD_I2C | |
4f93f8b1 | 618 | #define CONFIG_CMD_REGINFO |
2f9c19e4 | 619 | |
2f9c19e4 JL |
620 | #if defined(CONFIG_PCI) |
621 | #define CONFIG_CMD_PCI | |
622 | #define CONFIG_CMD_SCSI | |
623 | #define CONFIG_CMD_EXT2 | |
bbf4796f | 624 | #define CONFIG_CMD_USB |
debb7354 JL |
625 | #endif |
626 | ||
debb7354 JL |
627 | |
628 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
629 | ||
630 | /* | |
631 | * Miscellaneous configurable options | |
632 | */ | |
6d0f6bcf | 633 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
53677ef1 | 634 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf | 635 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
debb7354 | 636 | |
2f9c19e4 | 637 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 638 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
debb7354 | 639 | #else |
6d0f6bcf | 640 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
debb7354 JL |
641 | #endif |
642 | ||
6d0f6bcf JCPV |
643 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
644 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
645 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
debb7354 JL |
646 | |
647 | /* | |
648 | * For booting Linux, the board info and command line data | |
649 | * have to be in the first 8 MB of memory, since this is | |
650 | * the maximum mapped by the Linux kernel during initialization. | |
651 | */ | |
6d0f6bcf | 652 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
debb7354 | 653 | |
2f9c19e4 JL |
654 | #if defined(CONFIG_CMD_KGDB) |
655 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
debb7354 JL |
656 | #endif |
657 | ||
debb7354 JL |
658 | /* |
659 | * Environment Configuration | |
660 | */ | |
661 | ||
10327dc5 | 662 | #define CONFIG_HAS_ETH0 1 |
5c9efb36 JL |
663 | #define CONFIG_HAS_ETH1 1 |
664 | #define CONFIG_HAS_ETH2 1 | |
665 | #define CONFIG_HAS_ETH3 1 | |
debb7354 | 666 | |
18b6c8cd | 667 | #define CONFIG_IPADDR 192.168.1.100 |
debb7354 JL |
668 | |
669 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 670 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 671 | #define CONFIG_BOOTFILE "uImage" |
32922cdc | 672 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
debb7354 | 673 | |
5c9efb36 | 674 | #define CONFIG_SERVERIP 192.168.1.1 |
18b6c8cd | 675 | #define CONFIG_GATEWAYIP 192.168.1.1 |
5c9efb36 | 676 | #define CONFIG_NETMASK 255.255.255.0 |
debb7354 | 677 | |
5c9efb36 JL |
678 | /* default location for tftp and bootm */ |
679 | #define CONFIG_LOADADDR 1000000 | |
debb7354 JL |
680 | |
681 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
53677ef1 | 682 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
debb7354 JL |
683 | |
684 | #define CONFIG_BAUDRATE 115200 | |
685 | ||
53677ef1 WD |
686 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
687 | "netdev=eth0\0" \ | |
5368c55d | 688 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
53677ef1 | 689 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
690 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
691 | " +$filesize; " \ | |
692 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
693 | " +$filesize; " \ | |
694 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
695 | " $filesize; " \ | |
696 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
697 | " +$filesize; " \ | |
698 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
699 | " $filesize\0" \ | |
53677ef1 WD |
700 | "consoledev=ttyS0\0" \ |
701 | "ramdiskaddr=2000000\0" \ | |
702 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
703 | "fdtaddr=c00000\0" \ | |
704 | "fdtfile=mpc8641_hpcn.dtb\0" \ | |
3111d32c BB |
705 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
706 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
53677ef1 WD |
707 | "maxcpus=2" |
708 | ||
709 | ||
710 | #define CONFIG_NFSBOOTCOMMAND \ | |
711 | "setenv bootargs root=/dev/nfs rw " \ | |
712 | "nfsroot=$serverip:$rootpath " \ | |
713 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
714 | "console=$consoledev,$baudrate $othbootargs;" \ | |
715 | "tftp $loadaddr $bootfile;" \ | |
716 | "tftp $fdtaddr $fdtfile;" \ | |
717 | "bootm $loadaddr - $fdtaddr" | |
718 | ||
719 | #define CONFIG_RAMBOOTCOMMAND \ | |
720 | "setenv bootargs root=/dev/ram rw " \ | |
721 | "console=$consoledev,$baudrate $othbootargs;" \ | |
722 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
723 | "tftp $loadaddr $bootfile;" \ | |
724 | "tftp $fdtaddr $fdtfile;" \ | |
725 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
debb7354 JL |
726 | |
727 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
728 | ||
729 | #endif /* __CONFIG_H */ |