[people/ms/u-boot.git] / include / configs / MigoR.h

/*
 * Configuation settings for the Renesas Solutions Migo-R board
 *
 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MIGO_R_H
#define __MIGO_R_H

#undef DEBUG
#define CONFIG_CPU_SH7722	1
#define CONFIG_MIGO_R		1

#define CONFIG_CMD_SDRAM

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"

#define CONFIG_VERSION_VARIABLE
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SMC9111 */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE    (0xB0000000)

/* MEMORY */
#define MIGO_R_SDRAM_BASE	(0x8C000000)
#define MIGO_R_FLASH_BASE_1	(0xA0000000)
#define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
#define CONFIG_SYS_BARGSIZE	512		/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF0	1
#undef  CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress display of console
								   information at boot */
#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE

#define CONFIG_SYS_MEMTEST_START	(MIGO_R_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
/* maybe more, but if so u-boot doesn't know about it... */
#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
/* default load address for scripts ?!? */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Physical start address of Flash memory */
#define CONFIG_SYS_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
/* Max number of sectors on each Flash chip */
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */

#endif	/* __MIGO_R_H */
Commit	Line	Data
c2042f59	1	/*
	2	* Configuation settings for the Renesas Solutions Migo-R board
	3	*
	4	* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c2042f59	7	*/
	8
	9	#ifndef __MIGO_R_H
	10	#define __MIGO_R_H
	11
	12	#undef DEBUG
c2042f59	13	#define CONFIG_CPU_SH7722 1
	14	#define CONFIG_MIGO_R 1
	15
c2042f59	16	#define CONFIG_CMD_SDRAM
c2042f59	17
	18	#define CONFIG_BAUDRATE 115200
	19	#define CONFIG_BOOTDELAY 3
	20	#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
c2042f59	21
	22	#define CONFIG_VERSION_VARIABLE
	23	#undef CONFIG_SHOW_BOOT_PROGRESS
	24
	25	/* SMC9111 */
7194ab80	26	#define CONFIG_SMC91111
c2042f59	27	#define CONFIG_SMC91111_BASE (0xB0000000)
	28
	29	/* MEMORY */
	30	#define MIGO_R_SDRAM_BASE (0x8C000000)
	31	#define MIGO_R_FLASH_BASE_1 (0xA0000000)
	32	#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
	33
8cd7379e	34	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	35	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	36	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	37	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	38	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
	39	#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
	40	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
c2042f59	41
c2042f59	42	/* SCIF */
6c58a030	43	#define CONFIG_SCIF_CONSOLE 1
c2042f59	44	#define CONFIG_CONS_SCIF0 1
6d0f6bcf	45	#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console
c2042f59	46	information at boot */
6d0f6bcf JCPV	47	#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
6d0f6bcf JCPV	48	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
c2042f59	49
6d0f6bcf JCPV	50	#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
6d0f6bcf JCPV	51	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
c2042f59	52
c2042f59	53	/* Enable alternate, more extensive, memory test */
6d0f6bcf	54	#undef CONFIG_SYS_ALT_MEMTEST
c2042f59	55	/* Scratch address used by the alternate memory test */
6d0f6bcf	56	#undef CONFIG_SYS_MEMTEST_SCRATCH
c2042f59	57
c2042f59	58	/* Enable temporary baudrate change while serial download */
6d0f6bcf	59	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
c2042f59	60
6d0f6bcf	61	#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
c2042f59	62	/* maybe more, but if so u-boot doesn't know about it... */
6d0f6bcf	63	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
c2042f59	64	/* default load address for scripts ?!? */
6d0f6bcf	65	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
c2042f59	66
c2042f59	67	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
6d0f6bcf	68	#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
c2042f59	69	/* Monitor size */
6d0f6bcf	70	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
c2042f59	71	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	72	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	73	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
c2042f59	74
c2042f59	75	/* FLASH */
6d0f6bcf	76	#define CONFIG_SYS_FLASH_CFI
00b1883a	77	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf	78	#undef CONFIG_SYS_FLASH_QUIET_TEST
c2042f59	79	/* print 'E' for empty sector on flinfo */
6d0f6bcf	80	#define CONFIG_SYS_FLASH_EMPTY_INFO
c2042f59	81	/* Physical start address of Flash memory */
6d0f6bcf	82	#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
c2042f59	83	/* Max number of sectors on each Flash chip */
6d0f6bcf	84	#define CONFIG_SYS_MAX_FLASH_SECT 512
c2042f59	85
c2042f59	86	/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
6d0f6bcf JCPV	87	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6d0f6bcf JCPV	88	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
c2042f59	89
c2042f59	90	/* Timeout for Flash erase operations (in ms) */
6d0f6bcf	91	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
c2042f59	92	/* Timeout for Flash write operations (in ms) */
6d0f6bcf	93	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
c2042f59	94	/* Timeout for Flash set sector lock bit operations (in ms) */
6d0f6bcf	95	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
c2042f59	96	/* Timeout for Flash clear lock bit operations (in ms) */
6d0f6bcf	97	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
c2042f59	98
c2042f59	99	/* Use hardware flash sectors protection instead of U-Boot software protection */
6d0f6bcf JCPV	100	#undef CONFIG_SYS_FLASH_PROTECTION
6d0f6bcf JCPV	101	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
c2042f59	102
c2042f59	103	/* ENV setting */
5a1aceb0	104	#define CONFIG_ENV_IS_IN_FLASH
c2042f59	105	#define CONFIG_ENV_OVERWRITE 1
0e8d1586 JCPV	106	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	107	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	108	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	109	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	110	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586	111	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
c2042f59	112
	113	/* Board Clock */
	114	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	115	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	116	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	117	#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
c2042f59	118
c2042f59	119	#endif /* __MIGO_R_H */