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Convert CONFIG_BOOTP_BOOTPATH et al to Kconfig
[people/ms/u-boot.git] / include / configs / MigoR.h
CommitLineData
c2042f59 1/*
2 * Configuation settings for the Renesas Solutions Migo-R board
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
c2042f59 7 */
8
9#ifndef __MIGO_R_H
10#define __MIGO_R_H
11
c2042f59 12#define CONFIG_CPU_SH7722 1
c2042f59 13
18a40e84 14#define CONFIG_DISPLAY_BOARDINFO
c2042f59 15#undef CONFIG_SHOW_BOOT_PROGRESS
16
17/* SMC9111 */
7194ab80 18#define CONFIG_SMC91111
c2042f59 19#define CONFIG_SMC91111_BASE (0xB0000000)
20
21/* MEMORY */
22#define MIGO_R_SDRAM_BASE (0x8C000000)
23#define MIGO_R_FLASH_BASE_1 (0xA0000000)
24#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
25
6d0f6bcf 26#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
6d0f6bcf 27#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
c2042f59 28
29/* SCIF */
c2042f59 30#define CONFIG_CONS_SCIF0 1
c2042f59 31
6d0f6bcf
JCPV
32#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
33#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
c2042f59 34
35/* Enable alternate, more extensive, memory test */
6d0f6bcf 36#undef CONFIG_SYS_ALT_MEMTEST
c2042f59 37/* Scratch address used by the alternate memory test */
6d0f6bcf 38#undef CONFIG_SYS_MEMTEST_SCRATCH
c2042f59 39
40/* Enable temporary baudrate change while serial download */
6d0f6bcf 41#undef CONFIG_SYS_LOADS_BAUD_CHANGE
c2042f59 42
6d0f6bcf 43#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
c2042f59 44/* maybe more, but if so u-boot doesn't know about it... */
6d0f6bcf 45#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
c2042f59 46/* default load address for scripts ?!? */
6d0f6bcf 47#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
c2042f59 48
49/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
6d0f6bcf 50#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
c2042f59 51/* Monitor size */
6d0f6bcf 52#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
c2042f59 53/* Size of DRAM reserved for malloc() use */
6d0f6bcf 54#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf 55#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
c2042f59 56
57/* FLASH */
6d0f6bcf 58#define CONFIG_SYS_FLASH_CFI
00b1883a 59#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf 60#undef CONFIG_SYS_FLASH_QUIET_TEST
c2042f59 61/* print 'E' for empty sector on flinfo */
6d0f6bcf 62#define CONFIG_SYS_FLASH_EMPTY_INFO
c2042f59 63/* Physical start address of Flash memory */
6d0f6bcf 64#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
c2042f59 65/* Max number of sectors on each Flash chip */
6d0f6bcf 66#define CONFIG_SYS_MAX_FLASH_SECT 512
c2042f59 67
68/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
6d0f6bcf
JCPV
69#define CONFIG_SYS_MAX_FLASH_BANKS 1
70#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
c2042f59 71
72/* Timeout for Flash erase operations (in ms) */
6d0f6bcf 73#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
c2042f59 74/* Timeout for Flash write operations (in ms) */
6d0f6bcf 75#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
c2042f59 76/* Timeout for Flash set sector lock bit operations (in ms) */
6d0f6bcf 77#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
c2042f59 78/* Timeout for Flash clear lock bit operations (in ms) */
6d0f6bcf 79#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
c2042f59 80
81/* Use hardware flash sectors protection instead of U-Boot software protection */
6d0f6bcf
JCPV
82#undef CONFIG_SYS_FLASH_PROTECTION
83#undef CONFIG_SYS_DIRECT_FLASH_TFTP
c2042f59 84
85/* ENV setting */
c2042f59 86#define CONFIG_ENV_OVERWRITE 1
0e8d1586
JCPV
87#define CONFIG_ENV_SECT_SIZE (128 * 1024)
88#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf
JCPV
89#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
90/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
91#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586 92#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
c2042f59 93
94/* Board Clock */
95#define CONFIG_SYS_CLK_FREQ 33333333
684a501e
NI
96#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
97#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632 98#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
c2042f59 99
100#endif /* __MIGO_R_H */