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c59e1b4d | 1 | /* |
3d7506fa | 2 | * Copyright 2010-2012 Freescale Semiconductor, Inc. |
c59e1b4d TT |
3 | * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
4 | * Timur Tabi <timur@freescale.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the Free | |
8 | * Software Foundation; either version 2 of the License, or (at your option) | |
9 | * any later version. | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #include "../board/freescale/common/ics307_clk.h" | |
16 | ||
9899ac19 JY |
17 | #ifdef CONFIG_36BIT |
18 | #define CONFIG_PHYS_64BIT | |
19 | #endif | |
20 | ||
af253608 MM |
21 | #ifdef CONFIG_SDCARD |
22 | #define CONFIG_RAMBOOT_SDCARD | |
23 | #define CONFIG_SYS_RAMBOOT | |
24 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
25 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
26 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
27 | #endif | |
28 | ||
29 | #ifdef CONFIG_SPIFLASH | |
30 | #define CONFIG_RAMBOOT_SPIFLASH | |
31 | #define CONFIG_SYS_RAMBOOT | |
32 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
33 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
34 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
35 | #endif | |
36 | ||
c59e1b4d TT |
37 | /* High Level Configuration Options */ |
38 | #define CONFIG_BOOKE /* BOOKE */ | |
39 | #define CONFIG_E500 /* BOOKE e500 family */ | |
40 | #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ | |
41 | #define CONFIG_P1022 | |
42 | #define CONFIG_P1022DS | |
43 | #define CONFIG_MP /* support multiple processors */ | |
44 | ||
2ae18241 WD |
45 | #ifndef CONFIG_SYS_TEXT_BASE |
46 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
47 | #endif | |
48 | ||
7a577fda KG |
49 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
50 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
51 | #endif | |
52 | ||
c59e1b4d TT |
53 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ |
54 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
55 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
56 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ | |
57 | #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ | |
58 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
59 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
60 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
61 | ||
c59e1b4d | 62 | #define CONFIG_ENABLE_36BIT_PHYS |
babb348c TT |
63 | |
64 | #ifdef CONFIG_PHYS_64BIT | |
c59e1b4d TT |
65 | #define CONFIG_ADDR_MAP |
66 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
9899ac19 | 67 | #endif |
c59e1b4d TT |
68 | |
69 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
70 | ||
71 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
72 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
73 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ | |
74 | ||
75 | /* | |
76 | * These can be toggled for performance analysis, otherwise use default. | |
77 | */ | |
78 | #define CONFIG_L2_CACHE | |
79 | #define CONFIG_BTB | |
80 | ||
81 | #define CONFIG_SYS_MEMTEST_START 0x00000000 | |
82 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
83 | ||
e46fedfe TT |
84 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
85 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
c59e1b4d | 86 | |
c59e1b4d TT |
87 | /* DDR Setup */ |
88 | #define CONFIG_DDR_SPD | |
89 | #define CONFIG_VERY_BIG_RAM | |
90 | #define CONFIG_FSL_DDR3 | |
91 | ||
92 | #ifdef CONFIG_DDR_ECC | |
93 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
94 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
95 | #endif | |
96 | ||
97 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
98 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
99 | ||
100 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
101 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
102 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
103 | ||
104 | /* I2C addresses of SPD EEPROMs */ | |
105 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
c39f44dc | 106 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
c59e1b4d TT |
107 | |
108 | /* | |
109 | * Memory map | |
110 | * | |
111 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
112 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable | |
113 | * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable | |
114 | * | |
115 | * Localbus cacheable (TBD) | |
116 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
117 | * | |
118 | * Localbus non-cacheable | |
119 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
120 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
121 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 | |
122 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
123 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
124 | */ | |
125 | ||
126 | /* | |
127 | * Local Bus Definitions | |
128 | */ | |
129 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ | |
9899ac19 | 130 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 131 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
9899ac19 JY |
132 | #else |
133 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
134 | #endif | |
c59e1b4d TT |
135 | |
136 | #define CONFIG_FLASH_BR_PRELIM \ | |
7ee41107 | 137 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
c59e1b4d TT |
138 | #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) |
139 | ||
140 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
141 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
142 | ||
143 | #define CONFIG_SYS_BR1_PRELIM \ | |
144 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
145 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM | |
146 | ||
147 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
148 | {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
149 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
150 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
151 | ||
152 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 | |
153 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 | |
154 | ||
14d0a02a | 155 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
c59e1b4d TT |
156 | |
157 | #define CONFIG_FLASH_CFI_DRIVER | |
158 | #define CONFIG_SYS_FLASH_CFI | |
159 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
160 | ||
161 | #define CONFIG_BOARD_EARLY_INIT_F | |
162 | #define CONFIG_BOARD_EARLY_INIT_R | |
163 | #define CONFIG_MISC_INIT_R | |
a2d12f88 | 164 | #define CONFIG_HWCONFIG |
c59e1b4d TT |
165 | |
166 | #define CONFIG_FSL_NGPIXIS | |
167 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
9899ac19 | 168 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 169 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
9899ac19 JY |
170 | #else |
171 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
172 | #endif | |
c59e1b4d TT |
173 | |
174 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
175 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) | |
176 | ||
177 | #define PIXIS_LBMAP_SWITCH 7 | |
2906845a | 178 | #define PIXIS_LBMAP_MASK 0xF0 |
c59e1b4d | 179 | #define PIXIS_LBMAP_ALTBANK 0x20 |
9b6e9d1c JY |
180 | #define PIXIS_ELBC_SPI_MASK 0xc0 |
181 | #define PIXIS_SPI 0x80 | |
c59e1b4d TT |
182 | |
183 | #define CONFIG_SYS_INIT_RAM_LOCK | |
184 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
553f0982 | 185 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
c59e1b4d | 186 | |
c59e1b4d | 187 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 188 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
c59e1b4d TT |
189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
190 | ||
191 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
07b5edc2 | 192 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
c59e1b4d TT |
193 | |
194 | /* | |
195 | * Serial Port | |
196 | */ | |
197 | #define CONFIG_CONS_INDEX 1 | |
198 | #define CONFIG_SYS_NS16550 | |
199 | #define CONFIG_SYS_NS16550_SERIAL | |
200 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
201 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
202 | ||
203 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
204 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
205 | ||
206 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
207 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
208 | ||
209 | /* Use the HUSH parser */ | |
210 | #define CONFIG_SYS_HUSH_PARSER | |
c59e1b4d | 211 | |
c59e1b4d | 212 | /* Video */ |
ba8e76bd TT |
213 | #define CONFIG_FSL_DIU_FB |
214 | ||
d5e01e49 TT |
215 | #ifdef CONFIG_FSL_DIU_FB |
216 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) | |
217 | #define CONFIG_VIDEO | |
218 | #define CONFIG_CMD_BMP | |
c59e1b4d | 219 | #define CONFIG_CFB_CONSOLE |
7d3053fb | 220 | #define CONFIG_VIDEO_SW_CURSOR |
c59e1b4d | 221 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
d5e01e49 TT |
222 | #define CONFIG_VIDEO_LOGO |
223 | #define CONFIG_VIDEO_BMP_LOGO | |
55b05237 TT |
224 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
225 | /* | |
226 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
227 | * disable empty flash sector detection, which is I/O-intensive. | |
228 | */ | |
229 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
c59e1b4d TT |
230 | #endif |
231 | ||
ba8e76bd | 232 | #ifndef CONFIG_FSL_DIU_FB |
218a758f JY |
233 | #define CONFIG_ATI |
234 | #endif | |
235 | ||
236 | #ifdef CONFIG_ATI | |
237 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
238 | #define CONFIG_VIDEO | |
239 | #define CONFIG_BIOSEMU | |
240 | #define CONFIG_VIDEO_SW_CURSOR | |
241 | #define CONFIG_ATI_RADEON_FB | |
242 | #define CONFIG_VIDEO_LOGO | |
243 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
244 | #define CONFIG_CFB_CONSOLE | |
245 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
246 | #endif | |
247 | ||
c59e1b4d TT |
248 | /* |
249 | * Pass open firmware flat tree | |
250 | */ | |
251 | #define CONFIG_OF_LIBFDT | |
252 | #define CONFIG_OF_BOARD_SETUP | |
253 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
254 | ||
255 | /* new uImage format support */ | |
256 | #define CONFIG_FIT | |
257 | #define CONFIG_FIT_VERBOSE | |
258 | ||
259 | /* I2C */ | |
260 | #define CONFIG_FSL_I2C | |
261 | #define CONFIG_HARD_I2C | |
262 | #define CONFIG_I2C_MULTI_BUS | |
263 | #define CONFIG_SYS_I2C_SPEED 400000 | |
264 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
265 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
266 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} | |
267 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
268 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
269 | ||
270 | /* | |
271 | * I2C2 EEPROM | |
272 | */ | |
273 | #define CONFIG_ID_EEPROM | |
274 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
275 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
276 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
277 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
278 | ||
9b6e9d1c JY |
279 | /* |
280 | * eSPI - Enhanced SPI | |
281 | */ | |
282 | #define CONFIG_SPI_FLASH | |
283 | #define CONFIG_SPI_FLASH_SPANSION | |
284 | ||
285 | #define CONFIG_HARD_SPI | |
286 | #define CONFIG_FSL_ESPI | |
287 | ||
288 | #define CONFIG_CMD_SF | |
289 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
290 | #define CONFIG_SF_DEFAULT_MODE 0 | |
291 | ||
c59e1b4d TT |
292 | /* |
293 | * General PCI | |
294 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
295 | */ | |
296 | ||
297 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
298 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
9899ac19 | 299 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d TT |
300 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
301 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull | |
9899ac19 JY |
302 | #else |
303 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
304 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
305 | #endif | |
c59e1b4d TT |
306 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
307 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
308 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
9899ac19 | 309 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 310 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
9899ac19 JY |
311 | #else |
312 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
313 | #endif | |
c59e1b4d TT |
314 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
315 | ||
316 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
317 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
9899ac19 | 318 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d TT |
319 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
320 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
9899ac19 JY |
321 | #else |
322 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
323 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
324 | #endif | |
c59e1b4d TT |
325 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
326 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
327 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
9899ac19 | 328 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 329 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
9899ac19 JY |
330 | #else |
331 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
332 | #endif | |
c59e1b4d TT |
333 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
334 | ||
335 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
336 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 | |
9899ac19 | 337 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d TT |
338 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
339 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull | |
9899ac19 JY |
340 | #else |
341 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
342 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
343 | #endif | |
c59e1b4d TT |
344 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
345 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
346 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
9899ac19 | 347 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 348 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
9899ac19 JY |
349 | #else |
350 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
351 | #endif | |
c59e1b4d TT |
352 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
353 | ||
354 | #ifdef CONFIG_PCI | |
c59e1b4d TT |
355 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
356 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
16855ec1 | 357 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
c59e1b4d TT |
358 | #endif |
359 | ||
360 | /* SATA */ | |
361 | #define CONFIG_LIBATA | |
362 | #define CONFIG_FSL_SATA | |
363 | ||
364 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
365 | #define CONFIG_SATA1 | |
366 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
367 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
368 | #define CONFIG_SATA2 | |
369 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
370 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
371 | ||
372 | #ifdef CONFIG_FSL_SATA | |
373 | #define CONFIG_LBA48 | |
374 | #define CONFIG_CMD_SATA | |
375 | #define CONFIG_DOS_PARTITION | |
376 | #define CONFIG_CMD_EXT2 | |
377 | #endif | |
378 | ||
379 | #define CONFIG_MMC | |
380 | #ifdef CONFIG_MMC | |
381 | #define CONFIG_CMD_MMC | |
382 | #define CONFIG_FSL_ESDHC | |
383 | #define CONFIG_GENERIC_MMC | |
384 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
385 | #endif | |
386 | ||
387 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
388 | #define CONFIG_CMD_EXT2 | |
389 | #define CONFIG_CMD_FAT | |
390 | #define CONFIG_DOS_PARTITION | |
391 | #endif | |
392 | ||
393 | #define CONFIG_TSEC_ENET | |
394 | #ifdef CONFIG_TSEC_ENET | |
395 | ||
396 | #define CONFIG_TSECV2 | |
c59e1b4d TT |
397 | |
398 | #define CONFIG_MII /* MII PHY management */ | |
399 | #define CONFIG_TSEC1 1 | |
400 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
401 | #define CONFIG_TSEC2 1 | |
402 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
403 | ||
404 | #define TSEC1_PHY_ADDR 1 | |
405 | #define TSEC2_PHY_ADDR 2 | |
406 | ||
407 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
408 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
409 | ||
410 | #define TSEC1_PHYIDX 0 | |
411 | #define TSEC2_PHYIDX 0 | |
412 | ||
413 | #define CONFIG_ETHPRIME "eTSEC1" | |
414 | ||
415 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
416 | #endif | |
417 | ||
418 | /* | |
419 | * Environment | |
420 | */ | |
af253608 MM |
421 | #ifdef CONFIG_SYS_RAMBOOT |
422 | #ifdef CONFIG_RAMBOOT_SPIFLASH | |
423 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
424 | #define CONFIG_ENV_SPI_BUS 0 | |
425 | #define CONFIG_ENV_SPI_CS 0 | |
426 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
427 | #define CONFIG_ENV_SPI_MODE 0 | |
428 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
429 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
430 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
431 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
432 | #define CONFIG_ENV_IS_IN_MMC | |
433 | #define CONFIG_ENV_SIZE 0x2000 | |
434 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
435 | #elif defined(CONFIG_NAND_U_BOOT) | |
436 | #define CONFIG_ENV_IS_IN_NAND | |
437 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
438 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
439 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) | |
440 | #else | |
441 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
442 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
443 | #define CONFIG_ENV_SIZE 0x2000 | |
444 | #endif | |
445 | #else | |
c59e1b4d | 446 | #define CONFIG_ENV_IS_IN_FLASH |
af253608 MM |
447 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
448 | #define CONFIG_ENV_ADDR 0xfff80000 | |
449 | #else | |
450 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
451 | #endif | |
c59e1b4d | 452 | #define CONFIG_ENV_SIZE 0x2000 |
af253608 MM |
453 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
454 | #endif | |
c59e1b4d TT |
455 | |
456 | #define CONFIG_LOADS_ECHO | |
457 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
458 | ||
459 | /* | |
460 | * Command line configuration. | |
461 | */ | |
462 | #include <config_cmd_default.h> | |
463 | ||
79ee3448 KG |
464 | #define CONFIG_CMD_ELF |
465 | #define CONFIG_CMD_ERRATA | |
c59e1b4d | 466 | #define CONFIG_CMD_IRQ |
c59e1b4d TT |
467 | #define CONFIG_CMD_I2C |
468 | #define CONFIG_CMD_MII | |
79ee3448 | 469 | #define CONFIG_CMD_PING |
c59e1b4d | 470 | #define CONFIG_CMD_SETEXPR |
b8339e2b | 471 | #define CONFIG_CMD_REGINFO |
c59e1b4d TT |
472 | |
473 | #ifdef CONFIG_PCI | |
474 | #define CONFIG_CMD_PCI | |
475 | #define CONFIG_CMD_NET | |
476 | #endif | |
477 | ||
478 | /* | |
479 | * USB | |
480 | */ | |
3d7506fa | 481 | #define CONFIG_HAS_FSL_DR_USB |
482 | #ifdef CONFIG_HAS_FSL_DR_USB | |
c59e1b4d TT |
483 | #define CONFIG_USB_EHCI |
484 | ||
485 | #ifdef CONFIG_USB_EHCI | |
486 | #define CONFIG_CMD_USB | |
487 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
488 | #define CONFIG_USB_EHCI_FSL | |
489 | #define CONFIG_USB_STORAGE | |
490 | #define CONFIG_CMD_FAT | |
491 | #endif | |
3d7506fa | 492 | #endif |
c59e1b4d TT |
493 | |
494 | /* | |
495 | * Miscellaneous configurable options | |
496 | */ | |
497 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
498 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
5be58f5f | 499 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
c59e1b4d TT |
500 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
501 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
502 | #ifdef CONFIG_CMD_KGDB | |
503 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
504 | #else | |
505 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
506 | #endif | |
507 | /* Print Buffer Size */ | |
508 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
509 | #define CONFIG_SYS_MAXARGS 16 | |
510 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
511 | #define CONFIG_SYS_HZ 1000 | |
512 | ||
513 | /* | |
514 | * For booting Linux, the board info and command line data | |
a832ac41 | 515 | * have to be in the first 64 MB of memory, since this is |
c59e1b4d TT |
516 | * the maximum mapped by the Linux kernel during initialization. |
517 | */ | |
a832ac41 KG |
518 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
519 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
c59e1b4d | 520 | |
c59e1b4d TT |
521 | #ifdef CONFIG_CMD_KGDB |
522 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
523 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
524 | #endif | |
525 | ||
526 | /* | |
527 | * Environment Configuration | |
528 | */ | |
529 | ||
530 | #define CONFIG_HOSTNAME p1022ds | |
8b3637c6 | 531 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 532 | #define CONFIG_BOOTFILE "uImage" |
c59e1b4d TT |
533 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
534 | ||
535 | #define CONFIG_LOADADDR 1000000 | |
536 | ||
537 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
c59e1b4d TT |
538 | |
539 | #define CONFIG_BAUDRATE 115200 | |
540 | ||
84e34b65 TT |
541 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
542 | "netdev=eth0\0" \ | |
5368c55d MV |
543 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
544 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
84e34b65 TT |
545 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
546 | "protect off $ubootaddr +$filesize && " \ | |
547 | "erase $ubootaddr +$filesize && " \ | |
548 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
549 | "protect on $ubootaddr +$filesize && " \ | |
550 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
551 | "consoledev=ttyS0\0" \ | |
552 | "ramdiskaddr=2000000\0" \ | |
553 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
554 | "fdtaddr=c00000\0" \ | |
555 | "fdtfile=p1022ds.dtb\0" \ | |
556 | "bdev=sda3\0" \ | |
ba8e76bd | 557 | "hwconfig=esdhc;audclk:12\0" |
c59e1b4d TT |
558 | |
559 | #define CONFIG_HDBOOT \ | |
560 | "setenv bootargs root=/dev/$bdev rw " \ | |
84e34b65 | 561 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
c59e1b4d TT |
562 | "tftp $loadaddr $bootfile;" \ |
563 | "tftp $fdtaddr $fdtfile;" \ | |
564 | "bootm $loadaddr - $fdtaddr" | |
565 | ||
566 | #define CONFIG_NFSBOOTCOMMAND \ | |
567 | "setenv bootargs root=/dev/nfs rw " \ | |
568 | "nfsroot=$serverip:$rootpath " \ | |
569 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
84e34b65 | 570 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
c59e1b4d TT |
571 | "tftp $loadaddr $bootfile;" \ |
572 | "tftp $fdtaddr $fdtfile;" \ | |
573 | "bootm $loadaddr - $fdtaddr" | |
574 | ||
575 | #define CONFIG_RAMBOOTCOMMAND \ | |
576 | "setenv bootargs root=/dev/ram rw " \ | |
84e34b65 | 577 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
c59e1b4d TT |
578 | "tftp $ramdiskaddr $ramdiskfile;" \ |
579 | "tftp $loadaddr $bootfile;" \ | |
580 | "tftp $fdtaddr $fdtfile;" \ | |
581 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
582 | ||
583 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
584 | ||
585 | #endif |