[people/ms/u-boot.git] / include / configs / P1023RDB.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Authors:  Roy Zang <tie-fei.zang@freescale.com>
 *	     Chunhe Lan <Chunhe.Lan@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xeff40000
#endif

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/* High Level Configuration Options */
#define CONFIG_BOOKE		/* BOOKE */
#define CONFIG_E500		/* BOOKE e500 family */
#define CONFIG_P1023
#define CONFIG_MP		/* support multiple processors */

#define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
#define CONFIG_PCI		/* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2		/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3		/* PCIE controler 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW		/* Use common FSL init code */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif

#define CONFIG_SYS_CLK_FREQ	66666666
#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_HWCONFIG

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x02000000

#define CONFIG_PANIC_HANG	/* do not reset board on panic */

/* Implement conversion of addresses in the LBC */
#define CONFIG_SYS_LBC_LBCR		0x00000000
#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8

/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
#define CONFIG_SYS_SPD_BUS_NUM          0
#define SPD_EEPROM_ADDRESS              0x50
#define CONFIG_SYS_DDR_RAW_TIMING

/*
 * Memory map
 *
 * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
 * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
 * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
 * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
 * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
 * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
 *
 * Localbus non-cacheable
 *
 * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
 * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
				| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f function */
#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */

#define CONFIG_SYS_NAND_BASE		0xffa00000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
				| BR_PS_8		/* Port Size = 8bit */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */
#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
				| OR_FCM_PGS \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR)

#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/*
 * I2C2 EEPROM
 */
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_BUS_NUM		0

#define CONFIG_CMD_I2C

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */

/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

#if defined(CONFIG_PCI)
#define CONFIG_E1000		/* Defind e1000 pci Ethernet card */
#define CONFIG_PCI_PNP		/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI

#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_BOOTDELAY -1	/* -1 disables auto-boot */

#define CONFIG_BAUDRATE	115200

/* Qman/Bman */
#define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000

/* For FM */
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_ATHEROS
#endif

/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2

#define CONFIG_SYS_TBIPA_VALUE	8
#define CONFIG_MII		/* MII PHY management */
#define CONFIG_ETHPRIME		"FM1@DTSEC1"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"

#endif	/* __CONFIG_H */
Commit	Line	Data
57072338 CL	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Authors: Roy Zang <tie-fei.zang@freescale.com>
	5	* Chunhe Lan <Chunhe.Lan@freescale.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
57072338 CL	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#ifndef CONFIG_SYS_TEXT_BASE
e222b1f3	14	#define CONFIG_SYS_TEXT_BASE 0xeff40000
57072338 CL	15	#endif
	16
	17	#ifndef CONFIG_SYS_MONITOR_BASE
	18	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	19	#endif
	20
	21	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	22	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	23	#endif
	24
	25	/* High Level Configuration Options */
	26	#define CONFIG_BOOKE /* BOOKE */
	27	#define CONFIG_E500 /* BOOKE e500 family */
57072338 CL	28	#define CONFIG_P1023
	29	#define CONFIG_MP /* support multiple processors */
	30
	31	#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
	32	#define CONFIG_PCI /* Enable PCI/PCIE */
	33	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
	34	#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
	35	#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
	36	#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
	37	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	38	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	39	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	40	#define CONFIG_FSL_LAW /* Use common FSL init code */
	41
	42	#ifndef __ASSEMBLY__
	43	extern unsigned long get_clock_freq(void);
	44	#endif
	45
	46	#define CONFIG_SYS_CLK_FREQ 66666666
	47	#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
	48
	49	/*
	50	* These can be toggled for performance analysis, otherwise use default.
	51	*/
	52	#define CONFIG_L2_CACHE /* toggle L2 cache */
	53	#define CONFIG_BTB /* toggle branch predition */
	54	#define CONFIG_HWCONFIG
	55
	56	#define CONFIG_ENABLE_36BIT_PHYS
	57
	58	#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
	59	#define CONFIG_SYS_MEMTEST_END 0x02000000
	60
	61	#define CONFIG_PANIC_HANG /* do not reset board on panic */
	62
	63	/* Implement conversion of addresses in the LBC */
	64	#define CONFIG_SYS_LBC_LBCR 0x00000000
	65	#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
	66
	67	/* DDR Setup */
	68	#define CONFIG_VERY_BIG_RAM
	69	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	70	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	71
	72	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	73	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	74
	75	#define CONFIG_DDR_SPD
5614e71b	76	#define CONFIG_SYS_FSL_DDR3
57072338 CL	77	#define CONFIG_FSL_DDR_INTERACTIVE
	78	#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
	79	#define CONFIG_SYS_SPD_BUS_NUM 0
	80	#define SPD_EEPROM_ADDRESS 0x50
	81	#define CONFIG_SYS_DDR_RAW_TIMING
	82
	83	/*
	84	* Memory map
	85	*
	86	* 0x0000_0000 0x1fff_ffff DDR 512M cacheable
	87	* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
	88	* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
	89	* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
	90	* 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
	91	* 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
	92	* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
	93	*
	94	* Localbus non-cacheable
	95	*
	96	* 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
	97	* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
	98	*/
	99
	100	/*
	101	* Local Bus Definitions
	102	*/
	103	#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
	104	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	105
	106	#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
	107	\| BR_PS_16 \| BR_V)
	108	#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
	109
	110	#define CONFIG_FLASH_CFI_DRIVER
	111	#define CONFIG_SYS_FLASH_CFI
	112	#define CONFIG_SYS_FLASH_EMPTY_INFO
	113	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	114	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
	115	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	116	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	117
	118	#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
	119	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
	120
	121	#define CONFIG_SYS_INIT_RAM_LOCK
	122	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
	123	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
	124	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	125	GENERATED_GBL_DATA_SIZE)
	126	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	127
9307cbab	128	#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
57072338 CL	129	#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
	130
	131	#define CONFIG_SYS_NAND_BASE 0xffa00000
	132	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	133
	134	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	135	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	136	#define CONFIG_MTD_NAND_VERIFY_WRITE
	137	#define CONFIG_CMD_NAND
	138	#define CONFIG_NAND_FSL_ELBC
	139	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	140
	141	/* NAND flash config */
	142	#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	143	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	144	\| BR_PS_8 /* Port Size = 8bit */ \
	145	\| BR_MS_FCM /* MSEL = FCM */ \
	146	\| BR_V) /* valid */
	147	#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
	148	\| OR_FCM_PGS \
	149	\| OR_FCM_CSCT \
	150	\| OR_FCM_CST \
	151	\| OR_FCM_CHT \
	152	\| OR_FCM_SCY_1 \
	153	\| OR_FCM_TRLX \
	154	\| OR_FCM_EHTR)
	155
	156	#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	157	#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	158	#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	159	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
	160
	161	/* Serial Port */
	162	#define CONFIG_CONS_INDEX 1
	163	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	164	#define CONFIG_SYS_NS16550
	165	#define CONFIG_SYS_NS16550_SERIAL
	166	#define CONFIG_SYS_NS16550_REG_SIZE 1
	167	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	168
	169	#define CONFIG_SYS_BAUDRATE_TABLE \
	170	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	171
	172	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
	173	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
	174
	175	/* Use the HUSH parser */
	176	#define CONFIG_SYS_HUSH_PARSER
	177
	178	/*
	179	* Pass open firmware flat tree
	180	*/
	181	#define CONFIG_OF_LIBFDT
	182	#define CONFIG_OF_BOARD_SETUP
	183	#define CONFIG_OF_STDOUT_VIA_ALIAS
	184
	185	/* new uImage format support */
	186	#define CONFIG_FIT
	187	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	188
	189	/* I2C */
00f792e0 HS	190	#define CONFIG_SYS_I2C
	191	#define CONFIG_SYS_I2C_FSL
	192	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	193	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	194	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	195	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	196	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	197	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
57072338 CL	198
	199	/*
	200	* I2C2 EEPROM
	201	*/
	202	#define CONFIG_ID_EEPROM
	203	#ifdef CONFIG_ID_EEPROM
	204	#define CONFIG_SYS_I2C_EEPROM_NXID
	205	#endif
	206	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	207	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	208	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	209
	210	#define CONFIG_CMD_I2C
	211
	212	/*
	213	* General PCI
	214	* Memory space is mapped 1-1, but I/O space must start from 0.
	215	*/
	216
	217	/* controller 3, Slot 1, tgtid 3, Base address b000 */
	218	#define CONFIG_SYS_PCIE3_NAME "Slot 3"
	219	#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
	220	#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
	221	#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
	222	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
	223	#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
	224	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
	225	#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
	226	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
	227
	228	/* controller 2, direct to uli, tgtid 2, Base address 9000 */
	229	#define CONFIG_SYS_PCIE2_NAME "Slot 2"
	230	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
	231	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
	232	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
	233	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	234	#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
	235	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
	236	#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
	237	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	238
	239	/* controller 1, Slot 2, tgtid 1, Base address a000 */
	240	#define CONFIG_SYS_PCIE1_NAME "Slot 1"
	241	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
	242	#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
	243	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
	244	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	245	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
	246	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	247	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
	248	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	249
	250	#if defined(CONFIG_PCI)
	251	#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
	252	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	253	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	254	#endif /* CONFIG_PCI */
	255
	256	/*
	257	* Environment
	258	*/
	259	#define CONFIG_ENV_OVERWRITE
	260
	261	#define CONFIG_ENV_IS_IN_FLASH
57072338	262	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
57072338 CL	263	#define CONFIG_ENV_SIZE 0x2000
	264	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
	265
	266	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	267	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	268
	269	/*
	270	* Command line configuration.
	271	*/
	272	#include <config_cmd_default.h>
	273
	274	#define CONFIG_CMD_IRQ
	275	#define CONFIG_CMD_PING
	276	#define CONFIG_CMD_MII
	277	#define CONFIG_CMD_SETEXPR
	278	#define CONFIG_CMD_REGINFO
	279
	280	#if defined(CONFIG_PCI)
	281	#define CONFIG_CMD_PCI
	282	#define CONFIG_CMD_NET
	283	#endif
	284
	285	/*
	286	* USB
	287	*/
	288	#define CONFIG_HAS_FSL_DR_USB
	289	#ifdef CONFIG_HAS_FSL_DR_USB
	290	#define CONFIG_USB_EHCI
	291
	292	#ifdef CONFIG_USB_EHCI
	293	#define CONFIG_CMD_USB
	294	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	295	#define CONFIG_USB_EHCI_FSL
	296	#define CONFIG_USB_STORAGE
	297	#define CONFIG_CMD_FAT
	298	#define CONFIG_CMD_EXT2
	299	#define CONFIG_CMD_FAT
	300	#define CONFIG_DOS_PARTITION
	301	#endif
	302	#endif
	303
	304	/*
	305	* Miscellaneous configurable options
	306	*/
	307	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	308	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	309	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
57072338 CL	310	#if defined(CONFIG_CMD_KGDB)
	311	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	312	#else
	313	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	314	#endif
	315	/* Print Buffer Size */
	316	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
	317	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	318	/* Boot Argument Buffer Size */
	319	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
57072338 CL	320
	321	/*
	322	* For booting Linux, the board info and command line data
	323	* have to be in the first 64 MB of memory, since this is
	324	* the maximum mapped by the Linux kernel during initialization.
	325	*/
	326	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
	327	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	328
	329	/*
	330	* Environment Configuration
	331	*/
	332	#define CONFIG_BOOTFILE "uImage"
	333	#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
	334
	335	/* default location for tftp and bootm */
	336	#define CONFIG_LOADADDR 1000000
	337
	338	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
	339
	340	#define CONFIG_BAUDRATE 115200
	341
	342	/* Qman/Bman */
	343	#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
	344	#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
	345	#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
	346	#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
	347	#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
	348	#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
	349	#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
	350
	351	/* For FM */
	352	#define CONFIG_SYS_DPAA_FMAN
	353	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
	354
	355	#ifdef CONFIG_SYS_DPAA_FMAN
	356	#define CONFIG_FMAN_ENET
	357	#define CONFIG_PHY_ATHEROS
	358	#endif
	359
	360	/* Default address of microcode for the Linux Fman driver */
	361	/* QE microcode/firmware address */
	362	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
dcf1d774	363	#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
57072338 CL	364	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	365	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	366
	367	#ifdef CONFIG_FMAN_ENET
	368	#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
	369	#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
	370
	371	#define CONFIG_SYS_TBIPA_VALUE 8
	372	#define CONFIG_MII /* MII PHY management */
	373	#define CONFIG_ETHPRIME "FM1@DTSEC1"
	374	#endif
	375
	376	#define CONFIG_EXTRA_ENV_SETTINGS \
	377	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
	378
	379	#endif /* __CONFIG_H */