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8ba132ca | 1 | /* |
76b565b6 | 2 | * (C) Copyright 2007-2008 |
8ba132ca MF |
3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. |
4 | * Based on the sequoia configuration file. | |
5 | * | |
6 | * (C) Copyright 2006-2007 | |
7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
8 | * | |
9 | * (C) Copyright 2006 | |
10 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
11 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
12 | * | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
8ba132ca MF |
14 | */ |
15 | ||
16 | /************************************************************************ | |
17 | * PMC440.h - configuration for esd PMC440 boards | |
18 | ***********************************************************************/ | |
19 | #ifndef __CONFIG_H | |
20 | #define __CONFIG_H | |
21 | ||
22 | /*----------------------------------------------------------------------- | |
23 | * High Level Configuration Options | |
24 | *----------------------------------------------------------------------*/ | |
25 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
26 | #define CONFIG_440 1 /* ... PPC440 family */ | |
8ba132ca | 27 | |
2ae18241 WD |
28 | #ifndef CONFIG_SYS_TEXT_BASE |
29 | #define CONFIG_SYS_TEXT_BASE 0xFFF90000 | |
30 | #endif | |
31 | ||
8ba132ca MF |
32 | #define CONFIG_SYS_CLK_FREQ 33333400 |
33 | ||
ff41ffc9 | 34 | #if 0 /* temporary disabled because OS/9 does not like dcache on startup */ |
8ba132ca | 35 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
ff41ffc9 | 36 | #endif |
8ba132ca MF |
37 | |
38 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
76b565b6 | 39 | #define CONFIG_MISC_INIT_F 1 |
8ba132ca MF |
40 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
41 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
42 | /*----------------------------------------------------------------------- | |
43 | * Base addresses -- Note these are effective addresses where the | |
44 | * actual resources get mapped (not physical addresses) | |
45 | *----------------------------------------------------------------------*/ | |
14d0a02a | 46 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
6d0f6bcf | 47 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */ |
8ba132ca MF |
48 | |
49 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ | |
50 | ||
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
52 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
53 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ | |
14d0a02a | 54 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */ |
56 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
57 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE | |
58 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
59 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
60 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
61 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
62 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
63 | #define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */ | |
8ba132ca | 64 | |
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
66 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
67 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
68 | #define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */ | |
69 | #define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */ | |
76b565b6 | 70 | #define CONFIG_SYS_RESET_BASE 0xef200000 |
8ba132ca MF |
71 | |
72 | /*----------------------------------------------------------------------- | |
73 | * Initial RAM & stack pointer | |
74 | *----------------------------------------------------------------------*/ | |
75 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ | |
6d0f6bcf | 76 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
553f0982 | 77 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
25ddd1fb | 78 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
800eb096 | 79 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
8ba132ca MF |
80 | |
81 | /*----------------------------------------------------------------------- | |
82 | * Serial Port | |
83 | *----------------------------------------------------------------------*/ | |
550650dd SR |
84 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
85 | #define CONFIG_SYS_NS16550 | |
86 | #define CONFIG_SYS_NS16550_SERIAL | |
87 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
88 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
6d0f6bcf | 89 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
8ba132ca | 90 | #define CONFIG_BAUDRATE 115200 |
8ba132ca | 91 | |
6d0f6bcf | 92 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8ba132ca MF |
93 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
94 | ||
95 | /*----------------------------------------------------------------------- | |
96 | * Environment | |
97 | *----------------------------------------------------------------------*/ | |
98 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
bb1f8b4f | 99 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ |
8ba132ca | 100 | #else |
51bfee19 | 101 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
0e8d1586 | 102 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
8ba132ca MF |
103 | #endif |
104 | ||
105 | /*----------------------------------------------------------------------- | |
106 | * RTC | |
107 | *----------------------------------------------------------------------*/ | |
108 | #define CONFIG_RTC_RX8025 | |
109 | ||
110 | /*----------------------------------------------------------------------- | |
111 | * FLASH related | |
112 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 113 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 114 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
8ba132ca | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
8ba132ca | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
119 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
8ba132ca | 120 | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
122 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
8ba132ca | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
125 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
8ba132ca | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
128 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
8ba132ca | 129 | |
5a1aceb0 | 130 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 131 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 132 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
76b565b6 | 133 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
8ba132ca MF |
134 | |
135 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
136 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
137 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8ba132ca MF |
138 | #endif |
139 | ||
bb1f8b4f | 140 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
0e8d1586 JCPV |
141 | #define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ |
142 | #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ | |
8ba132ca MF |
143 | #endif |
144 | ||
145 | /* | |
146 | * IPL (Initial Program Loader, integrated inside CPU) | |
147 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
148 | * | |
149 | * SPL (Secondary Program Loader) | |
150 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
151 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
152 | * controller and the NAND controller so that the special U-Boot image can be | |
153 | * loaded from NAND to SDRAM. | |
154 | * | |
155 | * NUB (NAND U-Boot) | |
156 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
157 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
158 | * | |
159 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
160 | * set up. While still running from cache, I experienced problems accessing | |
161 | * the NAND controller. sr - 2006-08-25 | |
162 | */ | |
7d5d7563 | 163 | #if defined (CONFIG_NAND_U_BOOT) |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
165 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
166 | #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
167 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
168 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
169 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) | |
8ba132ca MF |
170 | |
171 | /* | |
172 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
173 | */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
175 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
8ba132ca MF |
176 | |
177 | /* | |
178 | * Now the NAND chip has to be defined (no autodetection used!) | |
179 | */ | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
181 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
182 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
183 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
184 | #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
185 | ||
186 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
187 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
6d0f6bcf | 188 | #define CONFIG_SYS_NAND_OOBSIZE 16 |
6d0f6bcf | 189 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} |
7d5d7563 | 190 | #endif |
8ba132ca | 191 | |
51bfee19 | 192 | #ifdef CONFIG_ENV_IS_IN_NAND |
8ba132ca MF |
193 | /* |
194 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
195 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
196 | */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
198 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
0e8d1586 | 199 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
8ba132ca MF |
200 | #endif |
201 | ||
202 | /*----------------------------------------------------------------------- | |
203 | * DDR SDRAM | |
204 | *----------------------------------------------------------------------*/ | |
8ba132ca MF |
205 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
206 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ | |
207 | #endif | |
3aed3aa2 JCPV |
208 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
209 | /* 440EPx errata CHIP 11 */ | |
8ba132ca MF |
210 | |
211 | /*----------------------------------------------------------------------- | |
212 | * I2C | |
213 | *----------------------------------------------------------------------*/ | |
880540de DE |
214 | #define CONFIG_SYS_I2C |
215 | #define CONFIG_SYS_I2C_PPC4XX | |
216 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
217 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
218 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
219 | #define CONFIG_SYS_I2C_PPC4XX_CH1 | |
220 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 | |
221 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F | |
8ba132ca | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
8ba132ca | 224 | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 |
226 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
227 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
228 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
229 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 | |
8ba132ca | 230 | |
6d0f6bcf JCPV |
231 | #define CONFIG_SYS_EEPROM_WREN 1 |
232 | #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52 | |
8ba132ca MF |
233 | |
234 | /* | |
235 | * standard dtt sensor configuration - bottom bit will determine local or | |
236 | * remote sensor of the TMP401 | |
237 | */ | |
238 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
239 | ||
240 | /* | |
241 | * The PMC440 uses a TI TMP401 temperature sensor. This part | |
242 | * is basically compatible to the ADM1021 that is supported | |
243 | * by U-Boot. | |
244 | * | |
245 | * - i2c addr 0x4c | |
246 | * - conversion rate 0x02 = 0.25 conversions/second | |
247 | * - ALERT ouput disabled | |
248 | * - local temp sensor enabled, min set to 0 deg, max set to 70 deg | |
249 | * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg | |
250 | */ | |
251 | #define CONFIG_DTT_ADM1021 | |
6d0f6bcf | 252 | #define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } |
8ba132ca | 253 | |
76b565b6 MF |
254 | #define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \ |
255 | "\\\"painit\\\" to preboot command" | |
8ba132ca MF |
256 | |
257 | #undef CONFIG_BOOTARGS | |
258 | ||
259 | /* Setup some board specific values for the default environment variables */ | |
260 | #define CONFIG_HOSTNAME pmc440 | |
76b565b6 MF |
261 | #define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" |
262 | #define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" | |
8ba132ca MF |
263 | |
264 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
76b565b6 MF |
265 | CONFIG_SYS_BOOTFILE \ |
266 | CONFIG_SYS_ROOTPATH \ | |
267 | "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \ | |
8ba132ca | 268 | "netdev=eth0\0" \ |
ff41ffc9 | 269 | "ethrotate=no\0" \ |
8ba132ca MF |
270 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
271 | "nfsroot=${serverip}:${rootpath}\0" \ | |
272 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
273 | "addip=setenv bootargs ${bootargs} " \ | |
76b565b6 MF |
274 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
275 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8ba132ca | 276 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ |
76b565b6 MF |
277 | "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ |
278 | "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \ | |
76b565b6 MF |
279 | "nand_boot_fdt=run nandargs addip addtty addmisc;" \ |
280 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
76b565b6 MF |
281 | "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \ |
282 | "tftp ${fdt_addr_r} ${fdt_file};" \ | |
283 | "run nfsargs addip addtty addmisc;" \ | |
284 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
285 | "kernel_addr=ffc00000\0" \ | |
286 | "kernel_addr_r=200000\0" \ | |
287 | "fpga_addr=fff00000\0" \ | |
288 | "fdt_addr=fff80000\0" \ | |
289 | "fdt_addr_r=800000\0" \ | |
290 | "fpga=fpga loadb 0 ${fpga_addr}\0" \ | |
8ba132ca | 291 | "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \ |
5baefbba MF |
292 | "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \ |
293 | "cp.b 200000 fff90000 70000\0" \ | |
8ba132ca MF |
294 | "" |
295 | ||
296 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
297 | ||
298 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8ba132ca | 300 | |
96e21f86 | 301 | #define CONFIG_PPC4xx_EMAC |
8ba132ca MF |
302 | #define CONFIG_IBM_EMAC4_V4 1 |
303 | #define CONFIG_MII 1 /* MII PHY management */ | |
304 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ | |
305 | ||
306 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
307 | ||
308 | #define CONFIG_HAS_ETH0 | |
6d0f6bcf | 309 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
8ba132ca | 310 | |
8ba132ca MF |
311 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
312 | #define CONFIG_PHY1_ADDR 1 | |
313 | #define CONFIG_RESET_PHY_R 1 | |
314 | ||
315 | /* USB */ | |
316 | #define CONFIG_USB_OHCI_NEW | |
317 | #define CONFIG_USB_STORAGE | |
6d0f6bcf | 318 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
8ba132ca | 319 | |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 |
321 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
322 | #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST | |
323 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
324 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
8ba132ca MF |
325 | |
326 | /* Comment this out to enable USB 1.1 device */ | |
327 | #define USB_2_0_DEVICE | |
328 | ||
329 | /* Partitions */ | |
330 | #define CONFIG_MAC_PARTITION | |
331 | #define CONFIG_DOS_PARTITION | |
332 | #define CONFIG_ISO_PARTITION | |
333 | ||
334 | #include <config_cmd_default.h> | |
335 | ||
336 | #define CONFIG_CMD_BSP | |
337 | #define CONFIG_CMD_DATE | |
8ba132ca MF |
338 | #define CONFIG_CMD_DHCP |
339 | #define CONFIG_CMD_DTT | |
8ba132ca MF |
340 | #define CONFIG_CMD_EEPROM |
341 | #define CONFIG_CMD_ELF | |
342 | #define CONFIG_CMD_FAT | |
343 | #define CONFIG_CMD_I2C | |
8ba132ca MF |
344 | #define CONFIG_CMD_MII |
345 | #define CONFIG_CMD_NAND | |
346 | #define CONFIG_CMD_NET | |
347 | #define CONFIG_CMD_NFS | |
348 | #define CONFIG_CMD_PCI | |
349 | #define CONFIG_CMD_PING | |
350 | #define CONFIG_CMD_USB | |
351 | #define CONFIG_CMD_REGINFO | |
8ba132ca MF |
352 | |
353 | /* POST support */ | |
6d0f6bcf JCPV |
354 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
355 | CONFIG_SYS_POST_CPU | \ | |
356 | CONFIG_SYS_POST_UART | \ | |
357 | CONFIG_SYS_POST_I2C | \ | |
358 | CONFIG_SYS_POST_CACHE | \ | |
359 | CONFIG_SYS_POST_FPU | \ | |
360 | CONFIG_SYS_POST_ETHER | \ | |
361 | CONFIG_SYS_POST_SPR) | |
8ba132ca | 362 | |
8ba132ca | 363 | #define CONFIG_LOGBUFFER |
76b565b6 | 364 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
8ba132ca | 365 | |
6d0f6bcf | 366 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
8ba132ca MF |
367 | |
368 | #define CONFIG_SUPPORT_VFAT | |
369 | ||
370 | /*----------------------------------------------------------------------- | |
371 | * Miscellaneous configurable options | |
372 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 373 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
be88b169 | 374 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 375 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ba132ca | 376 | #else |
6d0f6bcf | 377 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ba132ca | 378 | #endif |
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
380 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
381 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ba132ca | 382 | |
6d0f6bcf JCPV |
383 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
384 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
8ba132ca | 385 | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
387 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
8ba132ca | 388 | |
8ba132ca MF |
389 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
390 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
391 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
392 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
393 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
394 | ||
395 | #define CONFIG_AUTOBOOT_KEYED 1 | |
c37207d7 WD |
396 | #define CONFIG_AUTOBOOT_PROMPT \ |
397 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
8ba132ca MF |
398 | #undef CONFIG_AUTOBOOT_DELAY_STR |
399 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
400 | ||
401 | /*----------------------------------------------------------------------- | |
402 | * PCI stuff | |
403 | *----------------------------------------------------------------------*/ | |
404 | /* General PCI */ | |
405 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 406 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
8ba132ca | 407 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
6d0f6bcf | 408 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ |
8ba132ca | 409 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 410 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
8ba132ca MF |
411 | |
412 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
413 | #define CONFIG_SYS_PCI_TARGET_INIT |
414 | #define CONFIG_SYS_PCI_MASTER_INIT | |
a760b020 | 415 | #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ |
8ba132ca | 416 | |
2fe6b7f7 MF |
417 | #define CONFIG_PCI_BOOTDELAY 0 |
418 | ||
8ba132ca | 419 | /* PCI identification */ |
6d0f6bcf JCPV |
420 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
421 | #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */ | |
422 | #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */ | |
1095493a SR |
423 | /* for weak __pci_target_init() */ |
424 | #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH | |
6d0f6bcf JCPV |
425 | #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC |
426 | #define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST | |
8ba132ca MF |
427 | |
428 | /* | |
429 | * For booting Linux, the board info and command line data | |
430 | * have to be in the first 8 MB of memory, since this is | |
431 | * the maximum mapped by the Linux kernel during initialization. | |
432 | */ | |
6d0f6bcf | 433 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
8ba132ca MF |
434 | |
435 | /*----------------------------------------------------------------------- | |
436 | * FPGA stuff | |
437 | *----------------------------------------------------------------------*/ | |
438 | #define CONFIG_FPGA | |
439 | #define CONFIG_FPGA_XILINX | |
440 | #define CONFIG_FPGA_SPARTAN2 | |
441 | #define CONFIG_FPGA_SPARTAN3 | |
442 | ||
443 | #define CONFIG_FPGA_COUNT 2 | |
444 | /*----------------------------------------------------------------------- | |
445 | * External Bus Controller (EBC) Setup | |
446 | *----------------------------------------------------------------------*/ | |
447 | ||
448 | /* | |
449 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
450 | */ | |
451 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
6d0f6bcf | 452 | #define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */ |
8ba132ca MF |
453 | |
454 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
455 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
456 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
8ba132ca MF |
457 | |
458 | /* Memory Bank 2 (NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
459 | #define CONFIG_SYS_EBC_PB2AP 0x018003c0 |
460 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
8ba132ca | 461 | #else |
6d0f6bcf | 462 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
8ba132ca | 463 | /* Memory Bank 2 (NOR-FLASH) initialization */ |
6d0f6bcf JCPV |
464 | #define CONFIG_SYS_EBC_PB2AP 0x03017200 |
465 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
8ba132ca MF |
466 | |
467 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
468 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
469 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
8ba132ca MF |
470 | #endif |
471 | ||
76b565b6 | 472 | /* Memory Bank 1 (RESET) initialization */ |
455ae7e8 | 473 | #define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */ |
3aed3aa2 | 474 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000) |
76b565b6 | 475 | |
8ba132ca | 476 | /* Memory Bank 4 (FPGA / 32Bit) initialization */ |
6d0f6bcf JCPV |
477 | #define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ |
478 | #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */ | |
8ba132ca MF |
479 | |
480 | /* Memory Bank 5 (FPGA / 16Bit) initialization */ | |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */ |
482 | #define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */ | |
8ba132ca MF |
483 | |
484 | /*----------------------------------------------------------------------- | |
485 | * NAND FLASH | |
486 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 487 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
6d0f6bcf JCPV |
488 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
489 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
490 | #define CONFIG_SYS_NAND_QUIET_TEST 1 | |
8ba132ca | 491 | |
be88b169 | 492 | #if defined(CONFIG_CMD_KGDB) |
8ba132ca | 493 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
8ba132ca MF |
494 | #endif |
495 | ||
496 | /* pass open firmware flat tree */ | |
497 | #define CONFIG_OF_LIBFDT 1 | |
498 | #define CONFIG_OF_BOARD_SETUP 1 | |
499 | ||
76b565b6 MF |
500 | #define CONFIG_API 1 |
501 | ||
8ba132ca | 502 | #endif /* __CONFIG_H */ |