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8ba132ca 1/*
76b565b6 2 * (C) Copyright 2007-2008
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3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on the sequoia configuration file.
5 *
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
1a459660 13 * SPDX-License-Identifier: GPL-2.0+
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14 */
15
16/************************************************************************
17 * PMC440.h - configuration for esd PMC440 boards
18 ***********************************************************************/
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/*-----------------------------------------------------------------------
23 * High Level Configuration Options
24 *----------------------------------------------------------------------*/
25#define CONFIG_440EPX 1 /* Specific PPC440EPx */
26#define CONFIG_440 1 /* ... PPC440 family */
8ba132ca 27
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28#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xFFF90000
30#endif
31
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32#define CONFIG_SYS_GENERIC_BOARD
33#define CONFIG_DISPLAY_BOARDINFO
34
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35#define CONFIG_SYS_CLK_FREQ 33333400
36
ff41ffc9 37#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
8ba132ca 38#define CONFIG_4xx_DCACHE /* enable dcache */
ff41ffc9 39#endif
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40
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
76b565b6 42#define CONFIG_MISC_INIT_F 1
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43#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
44#define CONFIG_BOARD_TYPES 1 /* support board types */
45/*-----------------------------------------------------------------------
46 * Base addresses -- Note these are effective addresses where the
47 * actual resources get mapped (not physical addresses)
48 *----------------------------------------------------------------------*/
14d0a02a 49#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
6d0f6bcf 50#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
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51
52#define CONFIG_PRAM 0 /* use pram variable to overwrite */
53
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54#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
55#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
56#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
14d0a02a 57#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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58#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
59#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
60#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
61#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
62#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
63#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
64#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
65#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
66#define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
8ba132ca 67
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68#define CONFIG_SYS_USB2D0_BASE 0xe0000100
69#define CONFIG_SYS_USB_DEVICE 0xe0000000
70#define CONFIG_SYS_USB_HOST 0xe0000400
71#define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */
72#define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */
76b565b6 73#define CONFIG_SYS_RESET_BASE 0xef200000
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74
75/*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer
77 *----------------------------------------------------------------------*/
78/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf 79#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
553f0982 80#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb 81#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096 82#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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83
84/*-----------------------------------------------------------------------
85 * Serial Port
86 *----------------------------------------------------------------------*/
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87#define CONFIG_CONS_INDEX 1 /* Use UART0 */
88#define CONFIG_SYS_NS16550
89#define CONFIG_SYS_NS16550_SERIAL
90#define CONFIG_SYS_NS16550_REG_SIZE 1
91#define CONFIG_SYS_NS16550_CLK get_serial_clock()
6d0f6bcf 92#undef CONFIG_SYS_EXT_SERIAL_CLOCK
8ba132ca 93#define CONFIG_BAUDRATE 115200
8ba132ca 94
6d0f6bcf 95#define CONFIG_SYS_BAUDRATE_TABLE \
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96 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
97
98/*-----------------------------------------------------------------------
99 * Environment
100 *----------------------------------------------------------------------*/
bb1f8b4f 101#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
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102
103/*-----------------------------------------------------------------------
104 * RTC
105 *----------------------------------------------------------------------*/
106#define CONFIG_RTC_RX8025
107
108/*-----------------------------------------------------------------------
109 * FLASH related
110 *----------------------------------------------------------------------*/
6d0f6bcf 111#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a 112#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
8ba132ca 113
6d0f6bcf 114#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
8ba132ca 115
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116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
8ba132ca 118
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119#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
8ba132ca 121
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122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
123#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
8ba132ca 124
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125#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
126#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
8ba132ca 127
5a1aceb0 128#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 129#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf 130#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
76b565b6 131#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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132
133/* Address and size of Redundant Environment Sector */
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134#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
135#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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136#endif
137
bb1f8b4f 138#ifdef CONFIG_ENV_IS_IN_EEPROM
f39c5d1e 139#define CONFIG_I2C_ENV_EEPROM_BUS 0
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140#define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
141#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
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142#endif
143
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144/*-----------------------------------------------------------------------
145 * DDR SDRAM
146 *----------------------------------------------------------------------*/
8ba132ca 147#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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148#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
149 /* 440EPx errata CHIP 11 */
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150
151/*-----------------------------------------------------------------------
152 * I2C
153 *----------------------------------------------------------------------*/
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154#define CONFIG_SYS_I2C
155#define CONFIG_SYS_I2C_PPC4XX
156#define CONFIG_SYS_I2C_PPC4XX_CH0
157#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
158#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
159#define CONFIG_SYS_I2C_PPC4XX_CH1
160#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
161#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
8ba132ca 162
6d0f6bcf 163#define CONFIG_SYS_I2C_MULTI_EEPROMS
8ba132ca 164
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165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
169#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
8ba132ca 170
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171#define CONFIG_SYS_EEPROM_WREN 1
172#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
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173
174/*
175 * standard dtt sensor configuration - bottom bit will determine local or
176 * remote sensor of the TMP401
177 */
178#define CONFIG_DTT_SENSORS { 0, 1 }
179
180/*
181 * The PMC440 uses a TI TMP401 temperature sensor. This part
182 * is basically compatible to the ADM1021 that is supported
183 * by U-Boot.
184 *
185 * - i2c addr 0x4c
186 * - conversion rate 0x02 = 0.25 conversions/second
187 * - ALERT ouput disabled
188 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
189 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
190 */
191#define CONFIG_DTT_ADM1021
6d0f6bcf 192#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
8ba132ca 193
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194#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
195 "\\\"painit\\\" to preboot command"
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196
197#undef CONFIG_BOOTARGS
198
199/* Setup some board specific values for the default environment variables */
200#define CONFIG_HOSTNAME pmc440
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201#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
202#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
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203
204#define CONFIG_EXTRA_ENV_SETTINGS \
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205 CONFIG_SYS_BOOTFILE \
206 CONFIG_SYS_ROOTPATH \
207 "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
8ba132ca 208 "netdev=eth0\0" \
ff41ffc9 209 "ethrotate=no\0" \
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210 "nfsargs=setenv bootargs root=/dev/nfs rw " \
211 "nfsroot=${serverip}:${rootpath}\0" \
212 "ramargs=setenv bootargs root=/dev/ram rw\0" \
213 "addip=setenv bootargs ${bootargs} " \
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214 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
215 ":${hostname}:${netdev}:off panic=1\0" \
8ba132ca 216 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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217 "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
218 "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
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219 "nand_boot_fdt=run nandargs addip addtty addmisc;" \
220 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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221 "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
222 "tftp ${fdt_addr_r} ${fdt_file};" \
223 "run nfsargs addip addtty addmisc;" \
224 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
225 "kernel_addr=ffc00000\0" \
226 "kernel_addr_r=200000\0" \
227 "fpga_addr=fff00000\0" \
228 "fdt_addr=fff80000\0" \
229 "fdt_addr_r=800000\0" \
230 "fpga=fpga loadb 0 ${fpga_addr}\0" \
8ba132ca 231 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
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232 "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
233 "cp.b 200000 fff90000 70000\0" \
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234 ""
235
236#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
237
238#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 239#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
8ba132ca 240
96e21f86 241#define CONFIG_PPC4xx_EMAC
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242#define CONFIG_IBM_EMAC4_V4 1
243#define CONFIG_MII 1 /* MII PHY management */
244#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
245
246#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
247
248#define CONFIG_HAS_ETH0
6d0f6bcf 249#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
8ba132ca 250
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251#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
252#define CONFIG_PHY1_ADDR 1
253#define CONFIG_RESET_PHY_R 1
254
255/* USB */
256#define CONFIG_USB_OHCI_NEW
257#define CONFIG_USB_STORAGE
6d0f6bcf 258#define CONFIG_SYS_OHCI_BE_CONTROLLER
8ba132ca 259
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260#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
261#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
262#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
263#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
264#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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265
266/* Comment this out to enable USB 1.1 device */
267#define USB_2_0_DEVICE
268
269/* Partitions */
270#define CONFIG_MAC_PARTITION
271#define CONFIG_DOS_PARTITION
272#define CONFIG_ISO_PARTITION
273
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274#define CONFIG_CMD_BSP
275#define CONFIG_CMD_DATE
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276#define CONFIG_CMD_DHCP
277#define CONFIG_CMD_DTT
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278#define CONFIG_CMD_EEPROM
279#define CONFIG_CMD_ELF
280#define CONFIG_CMD_FAT
281#define CONFIG_CMD_I2C
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282#define CONFIG_CMD_MII
283#define CONFIG_CMD_NAND
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284#define CONFIG_CMD_PCI
285#define CONFIG_CMD_PING
286#define CONFIG_CMD_USB
287#define CONFIG_CMD_REGINFO
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288
289/* POST support */
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290#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
291 CONFIG_SYS_POST_CPU | \
292 CONFIG_SYS_POST_UART | \
293 CONFIG_SYS_POST_I2C | \
294 CONFIG_SYS_POST_CACHE | \
295 CONFIG_SYS_POST_FPU | \
296 CONFIG_SYS_POST_ETHER | \
297 CONFIG_SYS_POST_SPR)
8ba132ca 298
8ba132ca 299#define CONFIG_LOGBUFFER
76b565b6 300#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
8ba132ca 301
6d0f6bcf 302#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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303
304#define CONFIG_SUPPORT_VFAT
305
306/*-----------------------------------------------------------------------
307 * Miscellaneous configurable options
308 *----------------------------------------------------------------------*/
6d0f6bcf 309#define CONFIG_SYS_LONGHELP /* undef to save memory */
be88b169 310#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 311#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
8ba132ca 312#else
6d0f6bcf 313#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8ba132ca 314#endif
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315#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
316#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
317#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8ba132ca 318
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319#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
320#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
8ba132ca 321
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322#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
323#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
8ba132ca 324
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325#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
326#define CONFIG_LOOPW 1 /* enable loopw command */
327#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
328#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
329#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
330
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331/*-----------------------------------------------------------------------
332 * PCI stuff
333 *----------------------------------------------------------------------*/
334/* General PCI */
335#define CONFIG_PCI /* include pci support */
842033e6 336#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
8ba132ca 337#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
6d0f6bcf 338#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
8ba132ca 339#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf 340#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
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341
342/* Board-specific PCI */
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343#define CONFIG_SYS_PCI_TARGET_INIT
344#define CONFIG_SYS_PCI_MASTER_INIT
a760b020 345#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
8ba132ca 346
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347#define CONFIG_PCI_BOOTDELAY 0
348
8ba132ca 349/* PCI identification */
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350#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
351#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
352#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
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353/* for weak __pci_target_init() */
354#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
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355#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
356#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
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357
358/*
359 * For booting Linux, the board info and command line data
360 * have to be in the first 8 MB of memory, since this is
361 * the maximum mapped by the Linux kernel during initialization.
362 */
6d0f6bcf 363#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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364
365/*-----------------------------------------------------------------------
366 * FPGA stuff
367 *----------------------------------------------------------------------*/
368#define CONFIG_FPGA
369#define CONFIG_FPGA_XILINX
370#define CONFIG_FPGA_SPARTAN2
371#define CONFIG_FPGA_SPARTAN3
372
373#define CONFIG_FPGA_COUNT 2
374/*-----------------------------------------------------------------------
375 * External Bus Controller (EBC) Setup
376 *----------------------------------------------------------------------*/
377
378/*
379 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
380 */
6d0f6bcf 381#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
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382
383/* Memory Bank 0 (NOR-FLASH) initialization */
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384#define CONFIG_SYS_EBC_PB0AP 0x03017200
385#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
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386
387/* Memory Bank 2 (NAND-FLASH) initialization */
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388#define CONFIG_SYS_EBC_PB2AP 0x018003c0
389#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
8ba132ca 390
76b565b6 391/* Memory Bank 1 (RESET) initialization */
455ae7e8 392#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
3aed3aa2 393#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
76b565b6 394
8ba132ca 395/* Memory Bank 4 (FPGA / 32Bit) initialization */
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396#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
397#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
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398
399/* Memory Bank 5 (FPGA / 16Bit) initialization */
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400#define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
401#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
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402
403/*-----------------------------------------------------------------------
404 * NAND FLASH
405 *----------------------------------------------------------------------*/
6d0f6bcf 406#define CONFIG_SYS_MAX_NAND_DEVICE 1
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407#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
408#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
409#define CONFIG_SYS_NAND_QUIET_TEST 1
8ba132ca 410
be88b169 411#if defined(CONFIG_CMD_KGDB)
8ba132ca 412#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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413#endif
414
415/* pass open firmware flat tree */
416#define CONFIG_OF_LIBFDT 1
417#define CONFIG_OF_BOARD_SETUP 1
418
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419#define CONFIG_API 1
420
8ba132ca 421#endif /* __CONFIG_H */