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7d436078 | 1 | /* |
c60dee03 | 2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. |
7d436078 PK |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __CONFIG_H | |
24 | #define __CONFIG_H | |
25 | ||
26 | /* | |
27 | * T1040 QDS board configuration file | |
28 | */ | |
29 | #define CONFIG_T1040QDS | |
30 | #define CONFIG_PHYS_64BIT | |
31 | ||
32 | #ifdef CONFIG_RAMBOOT_PBL | |
33 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
34 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
e4536f8e MY |
35 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg |
36 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg | |
7d436078 PK |
37 | #endif |
38 | ||
39 | /* High Level Configuration Options */ | |
40 | #define CONFIG_BOOKE | |
41 | #define CONFIG_E500 /* BOOKE e500 family */ | |
42 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
43 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
7d436078 PK |
44 | #define CONFIG_MP /* support multiple processors */ |
45 | ||
48f6a9a2 TY |
46 | /* support deep sleep */ |
47 | #define CONFIG_DEEP_SLEEP | |
48 | #define CONFIG_SILENT_CONSOLE | |
49 | ||
7d436078 | 50 | #ifndef CONFIG_SYS_TEXT_BASE |
e222b1f3 | 51 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
7d436078 PK |
52 | #endif |
53 | ||
54 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
55 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
56 | #endif | |
57 | ||
58 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
59 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
60 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
737537ef | 61 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
7d436078 PK |
62 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
63 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
64 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
65 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
66 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
67 | #define CONFIG_PCIE4 /* PCIE controler 4 */ | |
68 | ||
69 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
70 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
71 | ||
72 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
73 | ||
74 | #define CONFIG_ENV_OVERWRITE | |
75 | ||
76 | #ifdef CONFIG_SYS_NO_FLASH | |
77 | #define CONFIG_ENV_IS_NOWHERE | |
78 | #else | |
79 | #define CONFIG_FLASH_CFI_DRIVER | |
80 | #define CONFIG_SYS_FLASH_CFI | |
81 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
82 | #endif | |
83 | ||
84 | #ifndef CONFIG_SYS_NO_FLASH | |
85 | #if defined(CONFIG_SPIFLASH) | |
86 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
87 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
88 | #define CONFIG_ENV_SPI_BUS 0 | |
89 | #define CONFIG_ENV_SPI_CS 0 | |
90 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
91 | #define CONFIG_ENV_SPI_MODE 0 | |
92 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
93 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
94 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
95 | #elif defined(CONFIG_SDCARD) | |
96 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
97 | #define CONFIG_ENV_IS_IN_MMC | |
98 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
99 | #define CONFIG_ENV_SIZE 0x2000 | |
e222b1f3 | 100 | #define CONFIG_ENV_OFFSET (512 * 1658) |
7d436078 PK |
101 | #elif defined(CONFIG_NAND) |
102 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
103 | #define CONFIG_ENV_IS_IN_NAND | |
104 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
e222b1f3 | 105 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
7d436078 PK |
106 | #else |
107 | #define CONFIG_ENV_IS_IN_FLASH | |
108 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
109 | #define CONFIG_ENV_SIZE 0x2000 | |
110 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
111 | #endif | |
112 | #else /* CONFIG_SYS_NO_FLASH */ | |
113 | #define CONFIG_ENV_SIZE 0x2000 | |
114 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
115 | #endif | |
116 | ||
117 | #ifndef __ASSEMBLY__ | |
118 | unsigned long get_board_sys_clk(void); | |
119 | unsigned long get_board_ddr_clk(void); | |
120 | #endif | |
121 | ||
122 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
123 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
124 | ||
125 | /* | |
126 | * These can be toggled for performance analysis, otherwise use default. | |
127 | */ | |
128 | #define CONFIG_SYS_CACHE_STASHING | |
129 | #define CONFIG_BACKSIDE_L2_CACHE | |
130 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
131 | #define CONFIG_BTB /* toggle branch predition */ | |
132 | #define CONFIG_DDR_ECC | |
133 | #ifdef CONFIG_DDR_ECC | |
134 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
135 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
136 | #endif | |
137 | ||
138 | #define CONFIG_ENABLE_36BIT_PHYS | |
139 | ||
140 | #define CONFIG_ADDR_MAP | |
141 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
142 | ||
143 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
144 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
145 | #define CONFIG_SYS_ALT_MEMTEST | |
146 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
147 | ||
148 | /* | |
149 | * Config the L3 Cache as L3 SRAM | |
150 | */ | |
151 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
152 | ||
153 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
154 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
155 | ||
156 | /* EEPROM */ | |
157 | #define CONFIG_ID_EEPROM | |
158 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
159 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
160 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
161 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
162 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
163 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
164 | ||
165 | /* | |
166 | * DDR Setup | |
167 | */ | |
168 | #define CONFIG_VERY_BIG_RAM | |
169 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
170 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
171 | ||
172 | /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ | |
173 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
2eb3ac7f | 174 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
7d436078 PK |
175 | |
176 | #define CONFIG_DDR_SPD | |
c60dee03 | 177 | #ifndef CONFIG_SYS_FSL_DDR4 |
5614e71b | 178 | #define CONFIG_SYS_FSL_DDR3 |
7d436078 | 179 | #define CONFIG_FSL_DDR_INTERACTIVE |
c60dee03 | 180 | #endif |
7d436078 PK |
181 | |
182 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
183 | #define SPD_EEPROM_ADDRESS 0x51 | |
184 | ||
185 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
186 | ||
187 | /* | |
188 | * IFC Definitions | |
189 | */ | |
190 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
191 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
192 | ||
193 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
194 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
195 | + 0x8000000) | \ | |
196 | CSPR_PORT_SIZE_16 | \ | |
197 | CSPR_MSEL_NOR | \ | |
198 | CSPR_V) | |
199 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
200 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
201 | CSPR_PORT_SIZE_16 | \ | |
202 | CSPR_MSEL_NOR | \ | |
203 | CSPR_V) | |
204 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
377ffcfa SS |
205 | |
206 | /* | |
207 | * TDM Definition | |
208 | */ | |
209 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
210 | ||
7d436078 PK |
211 | /* NOR Flash Timing Params */ |
212 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
213 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
214 | FTIM0_NOR_TEADC(0x5) | \ | |
215 | FTIM0_NOR_TEAHC(0x5)) | |
216 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
217 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
218 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
219 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
220 | FTIM2_NOR_TCH(0x4) | \ | |
221 | FTIM2_NOR_TWPH(0x0E) | \ | |
222 | FTIM2_NOR_TWP(0x1c)) | |
223 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
224 | ||
225 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
226 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
227 | ||
228 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
229 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
230 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
231 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
232 | ||
233 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
234 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
235 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
236 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
237 | #define QIXIS_BASE 0xffdf0000 | |
238 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) | |
239 | #define QIXIS_LBMAP_SWITCH 0x06 | |
240 | #define QIXIS_LBMAP_MASK 0x0f | |
241 | #define QIXIS_LBMAP_SHIFT 0 | |
242 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
243 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
244 | #define QIXIS_RST_CTL_RESET 0x31 | |
245 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
246 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
247 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
8c618dd6 | 248 | #define QIXIS_RST_FORCE_MEM 0x01 |
7d436078 PK |
249 | |
250 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
251 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
252 | | CSPR_PORT_SIZE_8 \ | |
253 | | CSPR_MSEL_GPCM \ | |
254 | | CSPR_V) | |
255 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
256 | #define CONFIG_SYS_CSOR3 0x0 | |
257 | /* QIXIS Timing parameters for IFC CS3 */ | |
258 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
259 | FTIM0_GPCM_TEADC(0x0e) | \ | |
260 | FTIM0_GPCM_TEAHC(0x0e)) | |
261 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
262 | FTIM1_GPCM_TRAD(0x3f)) | |
263 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
562de1d6 | 264 | FTIM2_GPCM_TCH(0x8) | \ |
7d436078 PK |
265 | FTIM2_GPCM_TWP(0x1f)) |
266 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
267 | ||
268 | #define CONFIG_NAND_FSL_IFC | |
269 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
270 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
271 | ||
272 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
273 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
274 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
275 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
276 | | CSPR_V) | |
277 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
278 | ||
279 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
280 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
281 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
282 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
283 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
284 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
285 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
286 | ||
287 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
288 | ||
289 | /* ONFI NAND Flash mode0 Timing Params */ | |
290 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
291 | FTIM0_NAND_TWP(0x18) | \ | |
292 | FTIM0_NAND_TWCHT(0x07) | \ | |
293 | FTIM0_NAND_TWH(0x0a)) | |
294 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
295 | FTIM1_NAND_TWBE(0x39) | \ | |
296 | FTIM1_NAND_TRR(0x0e) | \ | |
297 | FTIM1_NAND_TRP(0x18)) | |
298 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
299 | FTIM2_NAND_TREH(0x0a) | \ | |
300 | FTIM2_NAND_TWHRE(0x1e)) | |
301 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
302 | ||
303 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
304 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
305 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
306 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
307 | #define CONFIG_CMD_NAND | |
308 | ||
309 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
310 | ||
311 | #if defined(CONFIG_NAND) | |
312 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
313 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
314 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
315 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
316 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
317 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
318 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
319 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
320 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
321 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
322 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
323 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
324 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
325 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
326 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
327 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
328 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
329 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
330 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
331 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
332 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
333 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
334 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
335 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
336 | #else | |
337 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
338 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
339 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
340 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
341 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
342 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
343 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
344 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
345 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
346 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
347 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
348 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
349 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
350 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
351 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
352 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
353 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
354 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
355 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
356 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
357 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
358 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
359 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
360 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
361 | #endif | |
362 | ||
363 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
364 | ||
365 | #if defined(CONFIG_RAMBOOT_PBL) | |
366 | #define CONFIG_SYS_RAMBOOT | |
367 | #endif | |
368 | ||
369 | #define CONFIG_BOARD_EARLY_INIT_R | |
370 | #define CONFIG_MISC_INIT_R | |
371 | ||
372 | #define CONFIG_HWCONFIG | |
373 | ||
374 | /* define to use L1 as initial stack */ | |
375 | #define CONFIG_L1_INIT_RAM | |
376 | #define CONFIG_SYS_INIT_RAM_LOCK | |
377 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
378 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
379 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 | |
380 | /* The assembler doesn't like typecast */ | |
381 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
382 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
383 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
384 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
385 | ||
386 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
387 | GENERATED_GBL_DATA_SIZE) | |
388 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
389 | ||
9307cbab | 390 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
337b0c52 | 391 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
7d436078 PK |
392 | |
393 | /* Serial Port - controlled on board with jumper J8 | |
394 | * open - index 2 | |
395 | * shorted - index 1 | |
396 | */ | |
397 | #define CONFIG_CONS_INDEX 1 | |
398 | #define CONFIG_SYS_NS16550 | |
399 | #define CONFIG_SYS_NS16550_SERIAL | |
400 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
401 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
402 | ||
403 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
404 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
405 | ||
406 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
407 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
408 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
409 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
410 | #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ | |
411 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
412 | ||
413 | /* Use the HUSH parser */ | |
414 | #define CONFIG_SYS_HUSH_PARSER | |
415 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
416 | ||
337b0c52 PJ |
417 | /* Video */ |
418 | #define CONFIG_FSL_DIU_FB | |
419 | #ifdef CONFIG_FSL_DIU_FB | |
c53711bb | 420 | #define CONFIG_FSL_DIU_CH7301 |
337b0c52 PJ |
421 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) |
422 | #define CONFIG_VIDEO | |
423 | #define CONFIG_CMD_BMP | |
424 | #define CONFIG_CFB_CONSOLE | |
425 | #define CONFIG_VIDEO_SW_CURSOR | |
426 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
427 | #define CONFIG_VIDEO_LOGO | |
428 | #define CONFIG_VIDEO_BMP_LOGO | |
429 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
430 | /* | |
431 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
432 | * disable empty flash sector detection, which is I/O-intensive. | |
433 | */ | |
434 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
435 | #endif | |
436 | ||
7d436078 PK |
437 | /* pass open firmware flat tree */ |
438 | #define CONFIG_OF_LIBFDT | |
439 | #define CONFIG_OF_BOARD_SETUP | |
440 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
441 | ||
442 | /* new uImage format support */ | |
443 | #define CONFIG_FIT | |
444 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
445 | ||
446 | /* I2C */ | |
447 | #define CONFIG_SYS_I2C | |
448 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
2eb3ac7f | 449 | #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ |
b0d97cd2 SL |
450 | #define CONFIG_SYS_FSL_I2C2_SPEED 50000 |
451 | #define CONFIG_SYS_FSL_I2C3_SPEED 50000 | |
452 | #define CONFIG_SYS_FSL_I2C4_SPEED 50000 | |
7d436078 | 453 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
7d436078 | 454 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
b0d97cd2 SL |
455 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
456 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
7d436078 | 457 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
b0d97cd2 SL |
458 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
459 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
460 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
7d436078 PK |
461 | |
462 | #define I2C_MUX_PCA_ADDR 0x77 | |
463 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ | |
464 | ||
465 | ||
466 | /* I2C bus multiplexer */ | |
467 | #define I2C_MUX_CH_DEFAULT 0x8 | |
337b0c52 PJ |
468 | #define I2C_MUX_CH_DIU 0xC |
469 | ||
470 | /* LDI/DVI Encoder for display */ | |
471 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
472 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
7d436078 PK |
473 | |
474 | /* | |
475 | * RTC configuration | |
476 | */ | |
477 | #define RTC | |
478 | #define CONFIG_RTC_DS3231 1 | |
479 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
480 | ||
481 | /* | |
482 | * eSPI - Enhanced SPI | |
483 | */ | |
484 | #define CONFIG_FSL_ESPI | |
485 | #define CONFIG_SPI_FLASH | |
486 | #define CONFIG_SPI_FLASH_STMICRO | |
487 | #define CONFIG_SPI_FLASH_SST | |
488 | #define CONFIG_SPI_FLASH_EON | |
489 | #define CONFIG_CMD_SF | |
490 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
491 | #define CONFIG_SF_DEFAULT_MODE 0 | |
492 | ||
493 | /* | |
494 | * General PCI | |
495 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
496 | */ | |
497 | ||
498 | #ifdef CONFIG_PCI | |
499 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
500 | #ifdef CONFIG_PCIE1 | |
501 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
502 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
503 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
504 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
505 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
506 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
507 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
508 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
509 | #endif | |
510 | ||
511 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
512 | #ifdef CONFIG_PCIE2 | |
513 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
514 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
515 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
516 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
517 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
518 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
519 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
520 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
521 | #endif | |
522 | ||
523 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
524 | #ifdef CONFIG_PCIE3 | |
525 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
526 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
527 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
528 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
529 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
530 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
531 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
532 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
533 | #endif | |
534 | ||
535 | /* controller 4, Base address 203000 */ | |
536 | #ifdef CONFIG_PCIE4 | |
537 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
538 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
539 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
540 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
541 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
542 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
543 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
544 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
545 | #endif | |
546 | ||
547 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
548 | #define CONFIG_E1000 | |
549 | ||
550 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
551 | #define CONFIG_DOS_PARTITION | |
552 | #endif /* CONFIG_PCI */ | |
553 | ||
554 | /* SATA */ | |
555 | #define CONFIG_FSL_SATA_V2 | |
556 | #ifdef CONFIG_FSL_SATA_V2 | |
557 | #define CONFIG_LIBATA | |
558 | #define CONFIG_FSL_SATA | |
559 | ||
560 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
561 | #define CONFIG_SATA1 | |
562 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
563 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
564 | #define CONFIG_SATA2 | |
565 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
566 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
567 | ||
568 | #define CONFIG_LBA48 | |
569 | #define CONFIG_CMD_SATA | |
570 | #define CONFIG_DOS_PARTITION | |
571 | #define CONFIG_CMD_EXT2 | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * USB | |
576 | */ | |
577 | #define CONFIG_HAS_FSL_DR_USB | |
578 | ||
579 | #ifdef CONFIG_HAS_FSL_DR_USB | |
580 | #define CONFIG_USB_EHCI | |
581 | ||
582 | #ifdef CONFIG_USB_EHCI | |
583 | #define CONFIG_CMD_USB | |
584 | #define CONFIG_USB_STORAGE | |
585 | #define CONFIG_USB_EHCI_FSL | |
586 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
587 | #define CONFIG_CMD_EXT2 | |
588 | #endif | |
589 | #endif | |
590 | ||
591 | #define CONFIG_MMC | |
592 | ||
593 | #ifdef CONFIG_MMC | |
594 | #define CONFIG_FSL_ESDHC | |
595 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
596 | #define CONFIG_CMD_MMC | |
597 | #define CONFIG_GENERIC_MMC | |
598 | #define CONFIG_CMD_EXT2 | |
599 | #define CONFIG_CMD_FAT | |
600 | #define CONFIG_DOS_PARTITION | |
601 | #endif | |
602 | ||
603 | /* Qman/Bman */ | |
604 | #ifndef CONFIG_NOBQFMAN | |
605 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
606 | #define CONFIG_SYS_BMAN_NUM_PORTALS 25 | |
607 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
608 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
609 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
610 | #define CONFIG_SYS_QMAN_NUM_PORTALS 25 | |
611 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
612 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
613 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
614 | ||
615 | #define CONFIG_SYS_DPAA_FMAN | |
616 | #define CONFIG_SYS_DPAA_PME | |
617 | ||
6259e291 ZQ |
618 | #define CONFIG_QE |
619 | #define CONFIG_U_QE | |
7d436078 PK |
620 | /* Default address of microcode for the Linux Fman driver */ |
621 | #if defined(CONFIG_SPIFLASH) | |
622 | /* | |
623 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
624 | * env, so we got 0x110000. | |
625 | */ | |
626 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
dcf1d774 | 627 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
7d436078 PK |
628 | #elif defined(CONFIG_SDCARD) |
629 | /* | |
630 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
e222b1f3 PK |
631 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
632 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
7d436078 PK |
633 | */ |
634 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
dcf1d774 | 635 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
7d436078 PK |
636 | #elif defined(CONFIG_NAND) |
637 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
dcf1d774 | 638 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
7d436078 PK |
639 | #else |
640 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
dcf1d774 | 641 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
6259e291 | 642 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
7d436078 PK |
643 | #endif |
644 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
645 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
646 | #endif /* CONFIG_NOBQFMAN */ | |
647 | ||
648 | #ifdef CONFIG_SYS_DPAA_FMAN | |
649 | #define CONFIG_FMAN_ENET | |
650 | #define CONFIG_PHYLIB_10G | |
651 | #define CONFIG_PHY_VITESSE | |
652 | #define CONFIG_PHY_REALTEK | |
653 | #define CONFIG_PHY_TERANETICS | |
654 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
655 | #define SGMII_CARD_PORT2_PHY_ADDR 0x10 | |
656 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
657 | #define SGMII_CARD_PORT4_PHY_ADDR 0x11 | |
658 | #endif | |
659 | ||
660 | #ifdef CONFIG_FMAN_ENET | |
5b7672fc PK |
661 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 |
662 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 | |
7d436078 PK |
663 | |
664 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
665 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
666 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
667 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
668 | ||
669 | #define CONFIG_MII /* MII PHY management */ | |
670 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
671 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
672 | #endif | |
673 | ||
68b74739 PK |
674 | /* |
675 | * Dynamic MTD Partition support with mtdparts | |
676 | */ | |
677 | #ifndef CONFIG_SYS_NO_FLASH | |
678 | #define CONFIG_MTD_DEVICE | |
679 | #define CONFIG_MTD_PARTITIONS | |
680 | #define CONFIG_CMD_MTDPARTS | |
681 | #define CONFIG_FLASH_CFI_MTD | |
682 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ | |
683 | "spi0=spife110000.0" | |
684 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ | |
685 | "128k(dtb),96m(fs),-(user);"\ | |
686 | "fff800000.flash:2m(uboot),9m(kernel),"\ | |
687 | "128k(dtb),96m(fs),-(user);spife110000.0:" \ | |
688 | "2m(uboot),9m(kernel),128k(dtb),-(user)" | |
689 | #endif | |
690 | ||
7d436078 PK |
691 | /* |
692 | * Environment | |
693 | */ | |
694 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
695 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
696 | ||
697 | /* | |
698 | * Command line configuration. | |
699 | */ | |
700 | #include <config_cmd_default.h> | |
701 | ||
702 | #define CONFIG_CMD_DATE | |
703 | #define CONFIG_CMD_DHCP | |
704 | #define CONFIG_CMD_EEPROM | |
705 | #define CONFIG_CMD_ELF | |
706 | #define CONFIG_CMD_ERRATA | |
707 | #define CONFIG_CMD_GREPENV | |
708 | #define CONFIG_CMD_IRQ | |
709 | #define CONFIG_CMD_I2C | |
710 | #define CONFIG_CMD_MII | |
711 | #define CONFIG_CMD_PING | |
712 | #define CONFIG_CMD_REGINFO | |
713 | #define CONFIG_CMD_SETEXPR | |
714 | ||
715 | #ifdef CONFIG_PCI | |
716 | #define CONFIG_CMD_PCI | |
717 | #define CONFIG_CMD_NET | |
718 | #endif | |
719 | ||
737537ef RG |
720 | /* Hash command with SHA acceleration supported in hardware */ |
721 | #ifdef CONFIG_FSL_CAAM | |
722 | #define CONFIG_CMD_HASH | |
723 | #define CONFIG_SHA_HW_ACCEL | |
724 | #endif | |
725 | ||
7d436078 PK |
726 | /* |
727 | * Miscellaneous configurable options | |
728 | */ | |
729 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
730 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
731 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
732 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
7d436078 PK |
733 | #ifdef CONFIG_CMD_KGDB |
734 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
735 | #else | |
736 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
737 | #endif | |
738 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
739 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
740 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
7d436078 PK |
741 | |
742 | /* | |
743 | * For booting Linux, the board info and command line data | |
744 | * have to be in the first 64 MB of memory, since this is | |
745 | * the maximum mapped by the Linux kernel during initialization. | |
746 | */ | |
747 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
748 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
749 | ||
750 | #ifdef CONFIG_CMD_KGDB | |
751 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
7d436078 PK |
752 | #endif |
753 | ||
754 | /* | |
755 | * Environment Configuration | |
756 | */ | |
757 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
758 | #define CONFIG_BOOTFILE "uImage" | |
759 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
760 | ||
761 | /* default location for tftp and bootm */ | |
762 | #define CONFIG_LOADADDR 1000000 | |
763 | ||
764 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
765 | ||
766 | #define CONFIG_BAUDRATE 115200 | |
767 | ||
768 | #define __USB_PHY_TYPE utmi | |
769 | ||
770 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
771 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
772 | "bank_intlv=cs0_cs1;" \ | |
773 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
774 | "netdev=eth0\0" \ | |
337b0c52 | 775 | "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ |
7d436078 PK |
776 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
777 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
778 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
779 | "protect off $ubootaddr +$filesize && " \ | |
780 | "erase $ubootaddr +$filesize && " \ | |
781 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
782 | "protect on $ubootaddr +$filesize && " \ | |
783 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
784 | "consoledev=ttyS0\0" \ | |
785 | "ramdiskaddr=2000000\0" \ | |
786 | "ramdiskfile=t1040qds/ramdisk.uboot\0" \ | |
787 | "fdtaddr=c00000\0" \ | |
788 | "fdtfile=t1040qds/t1040qds.dtb\0" \ | |
3246584d | 789 | "bdev=sda3\0" |
7d436078 PK |
790 | |
791 | #define CONFIG_LINUX \ | |
792 | "setenv bootargs root=/dev/ram rw " \ | |
793 | "console=$consoledev,$baudrate $othbootargs;" \ | |
794 | "setenv ramdiskaddr 0x02000000;" \ | |
795 | "setenv fdtaddr 0x00c00000;" \ | |
796 | "setenv loadaddr 0x1000000;" \ | |
797 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
798 | ||
799 | #define CONFIG_HDBOOT \ | |
800 | "setenv bootargs root=/dev/$bdev rw " \ | |
801 | "console=$consoledev,$baudrate $othbootargs;" \ | |
802 | "tftp $loadaddr $bootfile;" \ | |
803 | "tftp $fdtaddr $fdtfile;" \ | |
804 | "bootm $loadaddr - $fdtaddr" | |
805 | ||
806 | #define CONFIG_NFSBOOTCOMMAND \ | |
807 | "setenv bootargs root=/dev/nfs rw " \ | |
808 | "nfsroot=$serverip:$rootpath " \ | |
809 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
810 | "console=$consoledev,$baudrate $othbootargs;" \ | |
811 | "tftp $loadaddr $bootfile;" \ | |
812 | "tftp $fdtaddr $fdtfile;" \ | |
813 | "bootm $loadaddr - $fdtaddr" | |
814 | ||
815 | #define CONFIG_RAMBOOTCOMMAND \ | |
816 | "setenv bootargs root=/dev/ram rw " \ | |
817 | "console=$consoledev,$baudrate $othbootargs;" \ | |
818 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
819 | "tftp $loadaddr $bootfile;" \ | |
820 | "tftp $fdtaddr $fdtfile;" \ | |
821 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
822 | ||
823 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
824 | ||
825 | #ifdef CONFIG_SECURE_BOOT | |
826 | #include <asm/fsl_secure_boot.h> | |
789490b6 | 827 | #define CONFIG_CMD_BLOB |
7d436078 PK |
828 | #endif |
829 | ||
830 | #endif /* __CONFIG_H */ |