projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ee52b188 YS |
1 | /* |
| 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| ee52b188 YS |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * T4240 QDS board configuration file | |
| 9 | */ | |
| 1cb19fbb YS |
10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H | |
| 12 | ||
| ee52b188 YS |
13 | #define CONFIG_FSL_SATA_V2 |
| 14 | #define CONFIG_PCIE4 | |
| 737537ef | 15 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| ee52b188 YS |
16 | |
| 17 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ | |
| 18 | ||
| 1cb19fbb | 19 | #ifdef CONFIG_RAMBOOT_PBL |
| e4536f8e | 20 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg |
| b6036993 SX |
21 | #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) |
| 22 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
| 23 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| 24 | #else | |
| b6036993 SX |
25 | #define CONFIG_SPL_FLUSH_IMAGE |
| 26 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| b6036993 SX |
27 | #define CONFIG_SYS_TEXT_BASE 0x00201000 |
| 28 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 | |
| 29 | #define CONFIG_SPL_PAD_TO 0x40000 | |
| 30 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
| 31 | #define RESET_VECTOR_OFFSET 0x27FFC | |
| 32 | #define BOOT_PAGE_OFFSET 0x27000 | |
| 33 | ||
| 34 | #ifdef CONFIG_NAND | |
| b6036993 SX |
35 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 36 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
| 37 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 38 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) | |
| 39 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| ec90ac73 | 40 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg |
| b6036993 SX |
41 | #define CONFIG_SPL_NAND_BOOT |
| 42 | #endif | |
| 43 | ||
| 44 | #ifdef CONFIG_SDCARD | |
| 45 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| b6036993 SX |
46 | #define CONFIG_SPL_MMC_MINIMAL |
| 47 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
| 48 | #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 | |
| 49 | #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 | |
| 50 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
| 51 | #ifndef CONFIG_SPL_BUILD | |
| 52 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 53 | #endif | |
| 54 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| ec90ac73 | 55 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg |
| b6036993 SX |
56 | #define CONFIG_SPL_MMC_BOOT |
| 57 | #endif | |
| 58 | ||
| 59 | #ifdef CONFIG_SPL_BUILD | |
| 60 | #define CONFIG_SPL_SKIP_RELOCATE | |
| 61 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 62 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| b6036993 SX |
63 | #endif |
| 64 | ||
| 1cb19fbb | 65 | #endif |
| b6036993 | 66 | #endif /* CONFIG_RAMBOOT_PBL */ |
| 1cb19fbb YS |
67 | |
| 68 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 69 | /* Set 1M boot space */ | |
| 70 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
| 71 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
| 72 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
| 73 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| 1cb19fbb YS |
74 | #endif |
| 75 | ||
| 76 | #define CONFIG_SRIO_PCIE_BOOT_MASTER | |
| 77 | #define CONFIG_DDR_ECC | |
| 78 | ||
| ee52b188 | 79 | #include "t4qds.h" |
| 1cb19fbb | 80 | |
| e856bdcf | 81 | #ifndef CONFIG_MTD_NOR_FLASH |
| 1cb19fbb YS |
82 | #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) |
| 83 | #define CONFIG_ENV_IS_NOWHERE | |
| 84 | #endif | |
| 85 | #else | |
| 86 | #define CONFIG_FLASH_CFI_DRIVER | |
| 87 | #define CONFIG_SYS_FLASH_CFI | |
| 88 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 89 | #endif | |
| 90 | ||
| 91 | #if defined(CONFIG_SPIFLASH) | |
| 92 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 93 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 94 | #define CONFIG_ENV_SPI_BUS 0 | |
| 95 | #define CONFIG_ENV_SPI_CS 0 | |
| 96 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 97 | #define CONFIG_ENV_SPI_MODE 0 | |
| 98 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 99 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 100 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 101 | #elif defined(CONFIG_SDCARD) | |
| 102 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 103 | #define CONFIG_ENV_IS_IN_MMC | |
| 104 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 105 | #define CONFIG_ENV_SIZE 0x2000 | |
| b6036993 | 106 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
| 1cb19fbb YS |
107 | #elif defined(CONFIG_NAND) |
| 108 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 109 | #define CONFIG_ENV_IS_IN_NAND | |
| b6036993 SX |
110 | #define CONFIG_ENV_SIZE 0x2000 |
| 111 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 1cb19fbb YS |
112 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 113 | #define CONFIG_ENV_IS_IN_REMOTE | |
| 114 | #define CONFIG_ENV_ADDR 0xffe20000 | |
| 115 | #define CONFIG_ENV_SIZE 0x2000 | |
| 116 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
| 117 | #define CONFIG_ENV_SIZE 0x2000 | |
| 118 | #else | |
| 119 | #define CONFIG_ENV_IS_IN_FLASH | |
| 120 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 121 | #define CONFIG_ENV_SIZE 0x2000 | |
| 122 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 123 | #endif | |
| 124 | ||
| 125 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
| 126 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| 127 | ||
| 128 | #ifndef __ASSEMBLY__ | |
| 129 | unsigned long get_board_sys_clk(void); | |
| 130 | unsigned long get_board_ddr_clk(void); | |
| 131 | #endif | |
| 132 | ||
| 133 | /* EEPROM */ | |
| 134 | #define CONFIG_ID_EEPROM | |
| 135 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 136 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 137 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 138 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 139 | ||
| 140 | /* | |
| 141 | * DDR Setup | |
| 142 | */ | |
| 143 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 144 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 145 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| 146 | #define SPD_EEPROM_ADDRESS3 0x53 | |
| 147 | #define SPD_EEPROM_ADDRESS4 0x54 | |
| 148 | #define SPD_EEPROM_ADDRESS5 0x55 | |
| 149 | #define SPD_EEPROM_ADDRESS6 0x56 | |
| 150 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ | |
| 151 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
| 152 | ||
| 153 | /* | |
| 154 | * IFC Definitions | |
| 155 | */ | |
| 156 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
| 157 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 158 | + 0x8000000) | \ | |
| 159 | CSPR_PORT_SIZE_16 | \ | |
| 160 | CSPR_MSEL_NOR | \ | |
| 161 | CSPR_V) | |
| 162 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
| 163 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 164 | CSPR_PORT_SIZE_16 | \ | |
| 165 | CSPR_MSEL_NOR | \ | |
| 166 | CSPR_V) | |
| 167 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 168 | /* NOR Flash Timing Params */ | |
| 169 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 170 | ||
| 171 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 172 | FTIM0_NOR_TEADC(0x5) | \ | |
| 173 | FTIM0_NOR_TEAHC(0x5)) | |
| 174 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 175 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 176 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 177 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 178 | FTIM2_NOR_TCH(0x4) | \ | |
| 179 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 180 | FTIM2_NOR_TWP(0x1c)) | |
| 181 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 182 | ||
| 183 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 184 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 185 | ||
| 186 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 187 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 188 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 189 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 190 | ||
| 191 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 192 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 193 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
| 194 | ||
| 195 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
| 196 | #define QIXIS_BASE 0xffdf0000 | |
| 197 | #define QIXIS_LBMAP_SWITCH 6 | |
| 198 | #define QIXIS_LBMAP_MASK 0x0f | |
| 199 | #define QIXIS_LBMAP_SHIFT 0 | |
| 200 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 201 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 202 | #define QIXIS_RST_CTL_RESET 0x83 | |
| c63e1370 | 203 | #define QIXIS_RST_FORCE_MEM 0x1 |
| 1cb19fbb YS |
204 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 205 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 206 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| f7e27cc5 HZ |
207 | #define QIXIS_BRDCFG5 0x55 |
| 208 | #define QIXIS_MUX_SDHC 2 | |
| d47e3d27 | 209 | #define QIXIS_MUX_SDHC_WIDTH8 1 |
| 1cb19fbb YS |
210 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
| 211 | ||
| 212 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
| 213 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 214 | | CSPR_PORT_SIZE_8 \ | |
| 215 | | CSPR_MSEL_GPCM \ | |
| 216 | | CSPR_V) | |
| 217 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
| 218 | #define CONFIG_SYS_CSOR3 0x0 | |
| 219 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 220 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 221 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 222 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 223 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 224 | FTIM1_GPCM_TRAD(0x3f)) | |
| 225 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 226 | FTIM2_GPCM_TCH(0x8) | \ |
| 1cb19fbb YS |
227 | FTIM2_GPCM_TWP(0x1f)) |
| 228 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 229 | ||
| 230 | /* NAND Flash on IFC */ | |
| 231 | #define CONFIG_NAND_FSL_IFC | |
| 232 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 233 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 234 | ||
| 235 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 236 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 237 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 238 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 239 | | CSPR_V) | |
| 240 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 241 | ||
| 242 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 243 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 244 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 245 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
| 246 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 247 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
| 248 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 249 | ||
| 250 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 251 | ||
| 252 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 253 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 254 | FTIM0_NAND_TWP(0x18) | \ | |
| 255 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 256 | FTIM0_NAND_TWH(0x0a)) | |
| 257 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 258 | FTIM1_NAND_TWBE(0x39) | \ | |
| 259 | FTIM1_NAND_TRR(0x0e) | \ | |
| 260 | FTIM1_NAND_TRP(0x18)) | |
| 261 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 262 | FTIM2_NAND_TREH(0x0a) | \ | |
| 263 | FTIM2_NAND_TWHRE(0x1e)) | |
| 264 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 265 | ||
| 266 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 267 | ||
| 268 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 269 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 1cb19fbb YS |
270 | #define CONFIG_CMD_NAND |
| 271 | ||
| 272 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 68ec9c85 PK |
273 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
| 274 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
| 1cb19fbb YS |
275 | |
| 276 | #if defined(CONFIG_NAND) | |
| 277 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 278 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 279 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 280 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 281 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 282 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 283 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 284 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| b6036993 SX |
285 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 286 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 287 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 288 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 289 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 290 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 291 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 292 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 293 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 294 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| 1cb19fbb YS |
295 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 296 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 297 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 298 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 299 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 300 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 301 | #else | |
| 302 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 303 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 304 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 305 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 306 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 307 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 308 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 309 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| b6036993 SX |
310 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 311 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 312 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 313 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 314 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 315 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 316 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 317 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 1cb19fbb YS |
318 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 319 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 320 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 321 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 322 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 323 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 324 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 325 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 326 | #endif | |
| 1cb19fbb YS |
327 | |
| 328 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 329 | #define CONFIG_SYS_RAMBOOT | |
| 330 | #endif | |
| 331 | ||
| 1cb19fbb YS |
332 | /* I2C */ |
| 333 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ | |
| 334 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ | |
| 335 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
| 336 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ | |
| 337 | ||
| 338 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 339 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
| 340 | #define I2C_MUX_CH_VSC3316_FS 0xc | |
| 341 | #define I2C_MUX_CH_VSC3316_BS 0xd | |
| 342 | ||
| 343 | /* Voltage monitor on channel 2*/ | |
| 344 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
| 345 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
| 346 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
| 347 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
| 348 | ||
| 349 | /* VSC Crossbar switches */ | |
| 350 | #define CONFIG_VSC_CROSSBAR | |
| 351 | #define VSC3316_FSM_TX_ADDR 0x70 | |
| 352 | #define VSC3316_FSM_RX_ADDR 0x71 | |
| 353 | ||
| 354 | /* | |
| 355 | * RapidIO | |
| 356 | */ | |
| 357 | ||
| 358 | /* | |
| 359 | * for slave u-boot IMAGE instored in master memory space, | |
| 360 | * PHYS must be aligned based on the SIZE | |
| 361 | */ | |
| e4911815 LG |
362 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 363 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
| 364 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
| 365 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
| 1cb19fbb YS |
366 | /* |
| 367 | * for slave UCODE and ENV instored in master memory space, | |
| 368 | * PHYS must be aligned based on the SIZE | |
| 369 | */ | |
| e4911815 | 370 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| 1cb19fbb YS |
371 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 372 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
| 373 | ||
| 374 | /* slave core release by master*/ | |
| 375 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
| 376 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
| 377 | ||
| 378 | /* | |
| 379 | * SRIO_PCIE_BOOT - SLAVE | |
| 380 | */ | |
| 381 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 382 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
| 383 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
| 384 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
| 385 | #endif | |
| 386 | /* | |
| 387 | * eSPI - Enhanced SPI | |
| 388 | */ | |
| 1cb19fbb YS |
389 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 390 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 391 | ||
| 1cb19fbb YS |
392 | /* Qman/Bman */ |
| 393 | #ifndef CONFIG_NOBQFMAN | |
| 394 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
| 395 | #define CONFIG_SYS_BMAN_NUM_PORTALS 50 | |
| 396 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
| 397 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 398 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
399 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 400 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 401 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 402 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 403 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 404 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 405 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 406 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| 1cb19fbb YS |
407 | #define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
| 408 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
| 409 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 410 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
411 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 412 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 413 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 414 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 415 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 416 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 417 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 418 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| 1cb19fbb YS |
419 | |
| 420 | #define CONFIG_SYS_DPAA_FMAN | |
| 421 | #define CONFIG_SYS_DPAA_PME | |
| 422 | #define CONFIG_SYS_PMAN | |
| 423 | #define CONFIG_SYS_DPAA_DCE | |
| 0795eff3 | 424 | #define CONFIG_SYS_DPAA_RMAN |
| 1cb19fbb YS |
425 | #define CONFIG_SYS_INTERLAKEN |
| 426 | ||
| 427 | /* Default address of microcode for the Linux Fman driver */ | |
| 428 | #if defined(CONFIG_SPIFLASH) | |
| 429 | /* | |
| 430 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 431 | * env, so we got 0x110000. | |
| 432 | */ | |
| 433 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
| dcf1d774 | 434 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 1cb19fbb YS |
435 | #elif defined(CONFIG_SDCARD) |
| 436 | /* | |
| 437 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| b6036993 SX |
438 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 439 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
| 1cb19fbb YS |
440 | */ |
| 441 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
| b6036993 | 442 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 1cb19fbb YS |
443 | #elif defined(CONFIG_NAND) |
| 444 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
| b6036993 | 445 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 1cb19fbb YS |
446 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 447 | /* | |
| 448 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
| 449 | * in two corenet boards, slave's ucode could be stored in master's memory | |
| 450 | * space, the address can be mapped from slave TLB->slave LAW-> | |
| 451 | * slave SRIO or PCIE outbound window->master inbound window-> | |
| 452 | * master LAW->the ucode address in master's memory space. | |
| 453 | */ | |
| 454 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
| dcf1d774 | 455 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
| 1cb19fbb YS |
456 | #else |
| 457 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
| dcf1d774 | 458 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 1cb19fbb YS |
459 | #endif |
| 460 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
| 461 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 462 | #endif /* CONFIG_NOBQFMAN */ | |
| 463 | ||
| 464 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 465 | #define CONFIG_FMAN_ENET | |
| 466 | #define CONFIG_PHYLIB_10G | |
| 467 | #define CONFIG_PHY_VITESSE | |
| 468 | #define CONFIG_PHY_TERANETICS | |
| 469 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
| 470 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D | |
| 471 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
| 472 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
| 473 | #define FM1_10GEC1_PHY_ADDR 0x0 | |
| 474 | #define FM1_10GEC2_PHY_ADDR 0x1 | |
| 475 | #define FM2_10GEC1_PHY_ADDR 0x2 | |
| 476 | #define FM2_10GEC2_PHY_ADDR 0x3 | |
| 477 | #endif | |
| 478 | ||
| 1cb19fbb YS |
479 | /* SATA */ |
| 480 | #ifdef CONFIG_FSL_SATA_V2 | |
| 481 | #define CONFIG_LIBATA | |
| 482 | #define CONFIG_FSL_SATA | |
| 483 | ||
| 484 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 485 | #define CONFIG_SATA1 | |
| 486 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 487 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 488 | #define CONFIG_SATA2 | |
| 489 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 490 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 491 | ||
| 492 | #define CONFIG_LBA48 | |
| 493 | #define CONFIG_CMD_SATA | |
| 1cb19fbb YS |
494 | #endif |
| 495 | ||
| 496 | #ifdef CONFIG_FMAN_ENET | |
| 497 | #define CONFIG_MII /* MII PHY management */ | |
| 498 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
| 499 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 500 | #endif | |
| 501 | ||
| 737537ef RG |
502 | /* Hash command with SHA acceleration supported in hardware */ |
| 503 | #ifdef CONFIG_FSL_CAAM | |
| 504 | #define CONFIG_CMD_HASH | |
| 505 | #define CONFIG_SHA_HW_ACCEL | |
| 506 | #endif | |
| 507 | ||
| 1cb19fbb YS |
508 | /* |
| 509 | * USB | |
| 510 | */ | |
| 1cb19fbb YS |
511 | #define CONFIG_USB_EHCI |
| 512 | #define CONFIG_USB_EHCI_FSL | |
| 513 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 1cb19fbb YS |
514 | #define CONFIG_HAS_FSL_DR_USB |
| 515 | ||
| 1cb19fbb YS |
516 | #ifdef CONFIG_MMC |
| 517 | #define CONFIG_FSL_ESDHC | |
| 518 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 519 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
| ef38f3ff | 520 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| f7e27cc5 HZ |
521 | #define CONFIG_ESDHC_DETECT_QUIRK \ |
| 522 | (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ | |
| 523 | IS_SVR_REV(get_svr(), 1, 0)) | |
| d47e3d27 HZ |
524 | #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ |
| 525 | (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) | |
| 1cb19fbb YS |
526 | #endif |
| 527 | ||
| 1cb19fbb YS |
528 | |
| 529 | #define __USB_PHY_TYPE utmi | |
| 530 | ||
| 531 | /* | |
| 532 | * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be | |
| 533 | * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way | |
| 534 | * interleaving. It can be cacheline, page, bank, superbank. | |
| 535 | * See doc/README.fsl-ddr for details. | |
| 536 | */ | |
| 26bc57da | 537 | #ifdef CONFIG_ARCH_T4240 |
| 1cb19fbb YS |
538 | #define CTRL_INTLV_PREFERED 3way_4KB |
| 539 | #else | |
| 540 | #define CTRL_INTLV_PREFERED cacheline | |
| 541 | #endif | |
| 542 | ||
| 543 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 544 | "hwconfig=fsl_ddr:" \ | |
| 545 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
| 546 | "bank_intlv=auto;" \ | |
| 547 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| 548 | "netdev=eth0\0" \ | |
| 549 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 550 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 551 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 552 | "protect off $ubootaddr +$filesize && " \ | |
| 553 | "erase $ubootaddr +$filesize && " \ | |
| 554 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 555 | "protect on $ubootaddr +$filesize && " \ | |
| 556 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 557 | "consoledev=ttyS0\0" \ | |
| 558 | "ramdiskaddr=2000000\0" \ | |
| 559 | "ramdiskfile=t4240qds/ramdisk.uboot\0" \ | |
| b24a4f62 | 560 | "fdtaddr=1e00000\0" \ |
| 1cb19fbb | 561 | "fdtfile=t4240qds/t4240qds.dtb\0" \ |
| 3246584d | 562 | "bdev=sda3\0" |
| 1cb19fbb YS |
563 | |
| 564 | #define CONFIG_HVBOOT \ | |
| 565 | "setenv bootargs config-addr=0x60000000; " \ | |
| 566 | "bootm 0x01000000 - 0x00f00000" | |
| 567 | ||
| 568 | #define CONFIG_ALU \ | |
| 569 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 570 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 571 | "cpu 1 release 0x01000000 - - -;" \ | |
| 572 | "cpu 2 release 0x01000000 - - -;" \ | |
| 573 | "cpu 3 release 0x01000000 - - -;" \ | |
| 574 | "cpu 4 release 0x01000000 - - -;" \ | |
| 575 | "cpu 5 release 0x01000000 - - -;" \ | |
| 576 | "cpu 6 release 0x01000000 - - -;" \ | |
| 577 | "cpu 7 release 0x01000000 - - -;" \ | |
| 578 | "go 0x01000000" | |
| 579 | ||
| 580 | #define CONFIG_LINUX \ | |
| 581 | "setenv bootargs root=/dev/ram rw " \ | |
| 582 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 583 | "setenv ramdiskaddr 0x02000000;" \ | |
| 584 | "setenv fdtaddr 0x00c00000;" \ | |
| 585 | "setenv loadaddr 0x1000000;" \ | |
| 586 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 587 | ||
| 588 | #define CONFIG_HDBOOT \ | |
| 589 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 590 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 591 | "tftp $loadaddr $bootfile;" \ | |
| 592 | "tftp $fdtaddr $fdtfile;" \ | |
| 593 | "bootm $loadaddr - $fdtaddr" | |
| 594 | ||
| 595 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 596 | "setenv bootargs root=/dev/nfs rw " \ | |
| 597 | "nfsroot=$serverip:$rootpath " \ | |
| 598 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 599 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 600 | "tftp $loadaddr $bootfile;" \ | |
| 601 | "tftp $fdtaddr $fdtfile;" \ | |
| 602 | "bootm $loadaddr - $fdtaddr" | |
| 603 | ||
| 604 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 605 | "setenv bootargs root=/dev/ram rw " \ | |
| 606 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 607 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 608 | "tftp $loadaddr $bootfile;" \ | |
| 609 | "tftp $fdtaddr $fdtfile;" \ | |
| 610 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 611 | ||
| 612 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
| 613 | ||
| 1cb19fbb | 614 | #include <asm/fsl_secure_boot.h> |
| 1cb19fbb YS |
615 | |
| 616 | #endif /* __CONFIG_H */ |