[people/ms/u-boot.git] / include / configs / TQM855L.h

/*
 * (C) Copyright 2000-2014
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
#define CONFIG_TQM855L		1	/* ...on a TQM8xxL module	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10

#define	CONFIG_BOOTCOUNT_LIMIT


#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"hostname=TQM855L\0"						\
	"bootfile=TQM855L/uImage\0"					\
	"fdt_addr=40040000\0"						\
	"kernel_addr=40060000\0"					\
	"ramdisk_addr=40200000\0"					\
	"u-boot=TQM855L/u-image.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=prot off 40000000 +${filesize};"			\
		"era 40000000 +${filesize};"				\
		"cp.b 200000 40000000 ${filesize};"			\
		"sete filesize;save\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

/*
 * Command line configuration.
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2

#define CONFIG_NETCONSOLE

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */

/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */

/*-----------------------------------------------------------------------
 * Dynamic MTD partition support
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"

#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
						"128k(dtb),"		\
						"1664k(kernel),"	\
						"2m(rootfs),"		\
						"4m(data)"

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
#define CONFIG_SYS_MAMR_PTA	98

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME		"SCC"

#define CONFIG_HWCONFIG		1

#endif	/* __CONFIG_H */
Commit	Line	Data
f4675560	1	/*
23c5d253	2	* (C) Copyright 2000-2014
f4675560 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
f4675560 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
f4675560 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
	21	#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	24
f4675560	25	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
3cb7a480 WD	26	#define CONFIG_SYS_SMC_RXBUFLEN 128
3cb7a480 WD	27	#define CONFIG_SYS_MAXIDLE 10
6aff3115	28
ae3af05e	29	#define CONFIG_BOOTCOUNT_LIMIT
f4675560	30
f4675560 WD	31
	32	#define CONFIG_BOARD_TYPES 1 /* support board types */
	33
6aff3115	34	#define CONFIG_PREBOOT "echo;" \
32bf3d14	35	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6aff3115	36	"echo"
f4675560 WD	37
f4675560 WD	38	#undef CONFIG_BOOTARGS
6aff3115 WD	39
6aff3115 WD	40	#define CONFIG_EXTRA_ENV_SETTINGS \
ae3af05e	41	"netdev=eth0\0" \
6aff3115	42	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	43	"nfsroot=${serverip}:${rootpath}\0" \
6aff3115	44	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	45	"addip=setenv bootargs ${bootargs} " \
	46	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	47	":${hostname}:${netdev}:off panic=1\0" \
6aff3115	48	"flash_nfs=run nfsargs addip;" \
fe126d8b	49	"bootm ${kernel_addr}\0" \
6aff3115	50	"flash_self=run ramargs addip;" \
fe126d8b WD	51	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	52	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
6aff3115	53	"rootpath=/opt/eldk/ppc_8xx\0" \
29f8f58f WD	54	"hostname=TQM855L\0" \
29f8f58f WD	55	"bootfile=TQM855L/uImage\0" \
eb6da805 WD	56	"fdt_addr=40040000\0" \
	57	"kernel_addr=40060000\0" \
	58	"ramdisk_addr=40200000\0" \
29f8f58f WD	59	"u-boot=TQM855L/u-image.bin\0" \
	60	"load=tftp 200000 ${u-boot}\0" \
	61	"update=prot off 40000000 +${filesize};" \
	62	"era 40000000 +${filesize};" \
	63	"cp.b 200000 40000000 ${filesize};" \
	64	"sete filesize;save\0" \
6aff3115 WD	65	""
6aff3115 WD	66	#define CONFIG_BOOTCOMMAND "run flash_self"
f4675560 WD	67
f4675560 WD	68	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	69	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
f4675560 WD	70
	71	#undef CONFIG_WATCHDOG /* watchdog disabled */
	72
f4675560 WD	73	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
f4675560 WD	74
37d4bb70 JL	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_SUBNETMASK
	79	#define CONFIG_BOOTP_GATEWAY
	80	#define CONFIG_BOOTP_HOSTNAME
	81	#define CONFIG_BOOTP_BOOTPATH
	82	#define CONFIG_BOOTP_BOOTFILESIZE
	83
f4675560 WD	84	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
f4675560 WD	85
2694690e JL	86	/*
	87	* Command line configuration.
	88	*/
2694690e	89	#define CONFIG_CMD_DATE
2694690e	90	#define CONFIG_CMD_IDE
29f8f58f	91	#define CONFIG_CMD_JFFS2
f4675560	92
29f8f58f WD	93	#define CONFIG_NETCONSOLE
29f8f58f WD	94
f4675560 WD	95	/*
	96	* Miscellaneous configurable options
	97	*/
6d0f6bcf	98	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6aff3115	99
2751a95a	100	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6aff3115	101
2694690e	102	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	103	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
f4675560	104	#else
6d0f6bcf	105	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
f4675560	106	#endif
6d0f6bcf JCPV	107	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	108	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	109	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
f4675560	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	112	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
f4675560	113
6d0f6bcf	114	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
f4675560	115
f4675560 WD	116	/*
	117	* Low Level Configuration Settings
	118	* (address mappings, register initial values, etc.)
	119	* You should know what you are doing if you make changes here.
	120	*/
	121	/*-----------------------------------------------------------------------
	122	* Internal Memory Mapped Register
	123	*/
6d0f6bcf	124	#define CONFIG_SYS_IMMR 0xFFF00000
f4675560 WD	125
	126	/*-----------------------------------------------------------------------
	127	* Definitions for initial stack pointer and data area (in DPRAM)
	128	*/
6d0f6bcf	129	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	130	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	131	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	132	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
f4675560 WD	133
	134	/*-----------------------------------------------------------------------
	135	* Start addresses for the final memory configuration
	136	* (Set up by the startup code)
6d0f6bcf	137	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
f4675560	138	*/
6d0f6bcf JCPV	139	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	140	#define CONFIG_SYS_FLASH_BASE 0x40000000
	141	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	142	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	143	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
f4675560 WD	144
	145	/*
	146	* For booting Linux, the board info and command line data
	147	* have to be in the first 8 MB of memory, since this is
	148	* the maximum mapped by the Linux kernel during initialization.
	149	*/
6d0f6bcf	150	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
f4675560 WD	151
	152	/*-----------------------------------------------------------------------
	153	* FLASH organization
	154	*/
f4675560	155
e318d9e9	156	/* use CFI flash driver */
6d0f6bcf	157	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	158	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	159	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
	160	#define CONFIG_SYS_FLASH_EMPTY_INFO
	161	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	162	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	163	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
f4675560	164
5a1aceb0	165	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	166	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	167	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
f4675560 WD	168
f4675560 WD	169	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	170	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	171	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
f4675560	172
6d0f6bcf	173	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
67c31036	174
7c803be2 WD	175	#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
7c803be2 WD	176
29f8f58f WD	177	/*-----------------------------------------------------------------------
	178	* Dynamic MTD partition support
	179	*/
68d7d651	180	#define CONFIG_CMD_MTDPARTS
942556a9 SR	181	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	182	#define CONFIG_FLASH_CFI_MTD
29f8f58f WD	183	#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
	184
	185	#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
	186	"128k(dtb)," \
	187	"1664k(kernel)," \
	188	"2m(rootfs)," \
cd82919e	189	"4m(data)"
29f8f58f	190
f4675560 WD	191	/*-----------------------------------------------------------------------
	192	* Hardware Information Block
	193	*/
6d0f6bcf JCPV	194	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	195	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	196	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
f4675560 WD	197
	198	/*-----------------------------------------------------------------------
	199	* Cache Configuration
	200	*/
6d0f6bcf	201	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
2694690e	202	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	203	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
f4675560 WD	204	#endif
	205
	206	/*-----------------------------------------------------------------------
	207	* SYPCR - System Protection Control 11-9
	208	* SYPCR can only be written once after reset!
	209	*-----------------------------------------------------------------------
	210	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	211	*/
	212	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	213	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
f4675560 WD	214	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
f4675560 WD	215	#else
6d0f6bcf	216	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
f4675560 WD	217	#endif
	218
	219	/*-----------------------------------------------------------------------
	220	* SIUMCR - SIU Module Configuration 11-6
	221	*-----------------------------------------------------------------------
	222	* PCMCIA config., multi-function pin tri-state
	223	*/
	224	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	225	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
f4675560	226	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	227	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
f4675560 WD	228	#endif /* CONFIG_CAN_DRIVER */
	229
	230	/*-----------------------------------------------------------------------
	231	* TBSCR - Time Base Status and Control 11-26
	232	*-----------------------------------------------------------------------
	233	* Clear Reference Interrupt Status, Timebase freezing enabled
	234	*/
6d0f6bcf	235	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
f4675560 WD	236
	237	/*-----------------------------------------------------------------------
	238	* RTCSC - Real-Time Clock Status and Control Register 11-27
	239	*-----------------------------------------------------------------------
	240	*/
6d0f6bcf	241	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
f4675560 WD	242
	243	/*-----------------------------------------------------------------------
	244	* PISCR - Periodic Interrupt Status and Control 11-31
	245	*-----------------------------------------------------------------------
	246	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	247	*/
6d0f6bcf	248	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
f4675560 WD	249
	250	/*-----------------------------------------------------------------------
	251	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	252	*-----------------------------------------------------------------------
	253	* Reset PLL lock status sticky bit, timer expired status bit and timer
	254	* interrupt status bit
f4675560	255	*/
6d0f6bcf	256	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
f4675560 WD	257
	258	/*-----------------------------------------------------------------------
	259	* SCCR - System Clock and reset Control Register 15-27
	260	*-----------------------------------------------------------------------
	261	* Set clock output, timebase and RTC source and divider,
	262	* power management and some other internal clocks
	263	*/
	264	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	265	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
f4675560 WD	266	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
f4675560 WD	267	SCCR_DFALCD00)
f4675560 WD	268
	269	/*-----------------------------------------------------------------------
	270	* PCMCIA stuff
	271	*-----------------------------------------------------------------------
	272	*
	273	*/
6d0f6bcf JCPV	274	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	275	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	276	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	277	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	278	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	279	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	280	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	281	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
f4675560 WD	282
	283	/*-----------------------------------------------------------------------
	284	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	285	*-----------------------------------------------------------------------
	286	*/
	287
8d1165e1	288	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
f4675560 WD	289	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	290
	291	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	292	#undef CONFIG_IDE_LED /* LED for ide not supported */
	293	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	294
6d0f6bcf JCPV	295	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	296	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
f4675560	297
6d0f6bcf	298	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
f4675560	299
6d0f6bcf	300	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
f4675560 WD	301
f4675560 WD	302	/* Offset for data I/O */
6d0f6bcf	303	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
f4675560 WD	304
f4675560 WD	305	/* Offset for normal register accesses */
6d0f6bcf	306	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
f4675560 WD	307
f4675560 WD	308	/* Offset for alternate registers */
6d0f6bcf	309	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
f4675560	310
f4675560 WD	311	/*-----------------------------------------------------------------------
	312	*
	313	*-----------------------------------------------------------------------
	314	*
	315	*/
6d0f6bcf	316	#define CONFIG_SYS_DER 0
f4675560 WD	317
	318	/*
	319	* Init Memory Controller:
	320	*
	321	* BR0/1 and OR0/1 (FLASH)
	322	*/
	323
	324	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	325	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	326
	327	/* used to re-map FLASH both when starting from SRAM or FLASH:
	328	* restrict access enough to keep SRAM working (if any)
	329	* but not too much to meddle with FLASH accesses
	330	*/
6d0f6bcf JCPV	331	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	332	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
f4675560 WD	333
	334	/*
	335	* FLASH timing:
	336	*/
6d0f6bcf	337	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
f4675560	338	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
f4675560	339
6d0f6bcf JCPV	340	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	341	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	342	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
f4675560	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	345	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	346	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
f4675560 WD	347
	348	/*
	349	* BR2/3 and OR2/3 (SDRAM)
	350	*
	351	*/
	352	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	353	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	354	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	355
	356	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	357	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
f4675560	358
6d0f6bcf JCPV	359	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	360	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
f4675560 WD	361
f4675560 WD	362	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	363	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	364	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
f4675560	365	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	366	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	367	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	368	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	369	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
f4675560 WD	370	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	371	#endif /* CONFIG_CAN_DRIVER */
	372
	373	/*
	374	* Memory Periodic Timer Prescaler
	375	*
	376	* The Divider for PTA (refresh timer) configuration is based on an
	377	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	378	* the number of chip selects (NCS) and the actually needed refresh
	379	* rate is done by setting MPTPR.
	380	*
	381	* PTA is calculated from
	382	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	383	*
	384	* gclk CPU clock (not bus clock!)
	385	* Trefresh Refresh cycle * 4 (four word bursts used)
	386	*
	387	* 4096 Rows from SDRAM example configuration
	388	* 1000 factor s -> ms
	389	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	390	* 4 Number of refresh cycles per period
	391	* 64 Refresh cycle in ms per number of rows
	392	* --------------------------------------------
	393	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	394	*
	395	* 50 MHz => 50.000.000 / Divider = 98
	396	* 66 Mhz => 66.000.000 / Divider = 129
	397	* 80 Mhz => 80.000.000 / Divider = 156
	398	*/
e9132ea9	399
6d0f6bcf JCPV	400	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
6d0f6bcf JCPV	401	#define CONFIG_SYS_MAMR_PTA 98
f4675560 WD	402
	403	/*
	404	* For 16 MBit, refresh rates could be 31.3 us
	405	* (= 64 ms / 2K = 125 / quad bursts).
	406	* For a simpler initialization, 15.6 us is used instead.
	407	*
6d0f6bcf JCPV	408	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	409	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
f4675560	410	*/
6d0f6bcf JCPV	411	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	412	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
f4675560 WD	413
f4675560 WD	414	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	415	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	416	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
f4675560 WD	417
	418	/*
	419	* MAMR settings for SDRAM
	420	*/
	421
	422	/* 8 column SDRAM */
6d0f6bcf	423	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
f4675560 WD	424	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	425	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	426	/* 9 column SDRAM */
6d0f6bcf	427	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
f4675560 WD	428	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	429	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	430
f4675560	431	#define CONFIG_SCC1_ENET
6aff3115	432	#define CONFIG_FEC_ENET
48690d80	433	#define CONFIG_ETHPRIME "SCC"
f4675560	434
7026ead0 HS	435	#define CONFIG_HWCONFIG 1
7026ead0 HS	436
f4675560	437	#endif /* __CONFIG_H */