[people/ms/u-boot.git] / include / configs / TQM866M.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
#define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/

#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
#define CONFIG_8xx_CPUCLK_DEFAULT	50000000	/*  50 MHz - CPU default clock	*/
						/* (it will be used if there is no	*/
						/* 'cpuclk' variable with valid value)	*/

#undef CFG_MEASURE_CPUCLK			/* Measure real cpu clock	*/
						/* (function measure_gclk()	*/
						/* will be called)		*/
#ifdef CFG_MEASURE_CPUCLK
#define CFG_8XX_XIN		10000000	/* measure_gclk() needs this	*/
#endif

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"bootfile=/tftpboot/TQM866M/uImage\0"				\
	"kernel_addr=40080000\0"					\
	"ramdisk_addr=40180000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/

#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
#define CFG_I2C_SLAVE		0xFE

#ifdef CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SOFT_I2C */

#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/

#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CFG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
#define CFG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing: Default value of OR0 after reset
 */
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
				 OR_SCY_15_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef CONFIG_CAN_DRIVER
#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * 4096	Rows from SDRAM example configuration
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))

/*
 * Memory Periodic Timer Prescaler
 * Periodic timer for refresh, start with refresh rate for 40 MHz clock
 * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
 */
#define CFG_MAMR_PTA		39

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 10 column SDRAM */
#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME		"SCC ETHERNET"

#endif	/* __CONFIG_H */
Commit	Line	Data
d4ca31c4	1	/*
414eec35	2	* (C) Copyright 2000-2005
d4ca31c4 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
c178d3da	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
d4ca31c4 WD	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
	37	#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
	38
66ca92a5 WD	39	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
	40	#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
	41	#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
	42	#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
c178d3da WD	43	/* (it will be used if there is no */
c178d3da WD	44	/* 'cpuclk' variable with valid value) */
d4ca31c4	45
75d1ea7f WD	46	#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */
	47	/* (function measure_gclk() */
	48	/* will be called) */
	49	#ifdef CFG_MEASURE_CPUCLK
	50	#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
	51	#endif
	52
c178d3da	53	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
d4ca31c4 WD	54
	55	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	56
c178d3da	57	#define CONFIG_BOOTCOUNT_LIMIT
d4ca31c4 WD	58
	59	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	60
	61	#define CONFIG_BOARD_TYPES 1 /* support board types */
	62
c178d3da	63	#define CONFIG_PREBOOT "echo;" \
d4ca31c4 WD	64	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	65	"echo"
	66
	67	#undef CONFIG_BOOTARGS
	68
c178d3da	69	#define CONFIG_EXTRA_ENV_SETTINGS \
d4ca31c4 WD	70	"netdev=eth0\0" \
d4ca31c4 WD	71	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	72	"nfsroot=${serverip}:${rootpath}\0" \
d4ca31c4	73	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	74	"addip=setenv bootargs ${bootargs} " \
	75	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	76	":${hostname}:${netdev}:off panic=1\0" \
d4ca31c4	77	"flash_nfs=run nfsargs addip;" \
fe126d8b	78	"bootm ${kernel_addr}\0" \
d4ca31c4	79	"flash_self=run ramargs addip;" \
fe126d8b WD	80	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	81	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
d4ca31c4	82	"rootpath=/opt/eldk/ppc_8xx\0" \
5e4be00f	83	"bootfile=/tftpboot/TQM866M/uImage\0" \
d4ca31c4 WD	84	"kernel_addr=40080000\0" \
	85	"ramdisk_addr=40180000\0" \
	86	""
	87	#define CONFIG_BOOTCOMMAND "run flash_self"
	88
	89	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	90	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	91
	92	#undef CONFIG_WATCHDOG /* watchdog disabled */
	93
c178d3da	94	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
d4ca31c4 WD	95
	96	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	97
	98	/* enable I2C and select the hardware/software driver */
	99	#undef CONFIG_HARD_I2C /* I2C with hardware support */
c178d3da	100	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
d4ca31c4 WD	101
	102	#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
	103	#define CFG_I2C_SLAVE 0xFE
	104
	105	#ifdef CONFIG_SOFT_I2C
	106	/*
	107	* Software (bit-bang) I2C driver configuration
	108	*/
	109	#define PB_SCL 0x00000020 /* PB 26 */
	110	#define PB_SDA 0x00000010 /* PB 27 */
	111
	112	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	113	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	114	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	115	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	116	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
c178d3da	117	else immr->im_cpm.cp_pbdat &= ~PB_SDA
d4ca31c4	118	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
c178d3da	119	else immr->im_cpm.cp_pbdat &= ~PB_SCL
d4ca31c4 WD	120	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
	121	#endif /* CONFIG_SOFT_I2C */
	122
	123	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
c178d3da	124	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
d4ca31c4 WD	125	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	126	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	127
37d4bb70 JL	128	/*
	129	* BOOTP options
	130	*/
	131	#define CONFIG_BOOTP_SUBNETMASK
	132	#define CONFIG_BOOTP_GATEWAY
	133	#define CONFIG_BOOTP_HOSTNAME
	134	#define CONFIG_BOOTP_BOOTPATH
	135	#define CONFIG_BOOTP_BOOTFILESIZE
	136
d4ca31c4 WD	137
	138	#define CONFIG_MAC_PARTITION
	139	#define CONFIG_DOS_PARTITION
	140
a6cccaea WD	141	#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
	142
	143	#define CONFIG_TIMESTAMP /* but print image timestmps */
d4ca31c4	144
d4ca31c4	145
2694690e JL	146	/*
	147	* Command line configuration.
	148	*/
	149	#include <config_cmd_default.h>
	150
	151	#define CONFIG_CMD_ASKENV
	152	#define CONFIG_CMD_DHCP
	153	#define CONFIG_CMD_EEPROM
	154	#define CONFIG_CMD_I2C
	155	#define CONFIG_CMD_IDE
	156	#define CONFIG_CMD_NFS
	157
d4ca31c4 WD	158
	159	/*
	160	* Miscellaneous configurable options
	161	*/
c178d3da WD	162	#define CFG_LONGHELP /* undef to save memory */
c178d3da WD	163	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
d4ca31c4	164
2751a95a WD	165	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
2751a95a WD	166	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
d4ca31c4	167	#ifdef CFG_HUSH_PARSER
2751a95a	168	#define CFG_PROMPT_HUSH_PS2 "> "
d4ca31c4 WD	169	#endif
d4ca31c4 WD	170
2694690e	171	#if defined(CONFIG_CMD_KGDB)
c178d3da	172	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
d4ca31c4	173	#else
c178d3da	174	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
d4ca31c4	175	#endif
c178d3da WD	176	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
c178d3da WD	177	#define CFG_MAXARGS 16 /* max number of command args */
d4ca31c4 WD	178	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	179
	180	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	181	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	182
c178d3da	183	#define CFG_LOAD_ADDR 0x100000 /* default load address */
d4ca31c4	184
c178d3da	185	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
d4ca31c4 WD	186
	187	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	188
	189	/*
	190	* Low Level Configuration Settings
	191	* (address mappings, register initial values, etc.)
	192	* You should know what you are doing if you make changes here.
	193	*/
	194	/*-----------------------------------------------------------------------
	195	* Internal Memory Mapped Register
	196	*/
	197	#define CFG_IMMR 0xFFF00000
	198
	199	/*-----------------------------------------------------------------------
	200	* Definitions for initial stack pointer and data area (in DPRAM)
	201	*/
	202	#define CFG_INIT_RAM_ADDR CFG_IMMR
c178d3da WD	203	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
c178d3da WD	204	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
d4ca31c4	205	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c178d3da	206	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
d4ca31c4 WD	207
	208	/*-----------------------------------------------------------------------
	209	* Start addresses for the final memory configuration
	210	* (Set up by the startup code)
	211	* Please note that CFG_SDRAM_BASE _must_ start at 0
	212	*/
c178d3da	213	#define CFG_SDRAM_BASE 0x00000000
d4ca31c4	214	#define CFG_FLASH_BASE 0x40000000
c178d3da	215	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
d4ca31c4	216	#define CFG_MONITOR_BASE CFG_FLASH_BASE
c178d3da	217	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
d4ca31c4 WD	218
	219	/*
	220	* For booting Linux, the board info and command line data
	221	* have to be in the first 8 MB of memory, since this is
	222	* the maximum mapped by the Linux kernel during initialization.
	223	*/
c178d3da	224	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
d4ca31c4 WD	225
	226	/*-----------------------------------------------------------------------
	227	* FLASH organization
	228	*/
	229	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	230	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	231
	232	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	233	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	234
c178d3da WD	235	#define CFG_ENV_IS_IN_FLASH 1
	236	#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	237	#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
	238	#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
d4ca31c4 WD	239
	240	/* Address and size of Redundant Environment Sector */
	241	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
	242	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	243
	244	/*-----------------------------------------------------------------------
	245	* Hardware Information Block
	246	*/
	247	#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
c178d3da	248	#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
d4ca31c4 WD	249	#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
	250
	251	/*-----------------------------------------------------------------------
	252	* Cache Configuration
	253	*/
	254	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
2694690e	255	#if defined(CONFIG_CMD_KGDB)
d4ca31c4 WD	256	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	257	#endif
	258
	259	/*-----------------------------------------------------------------------
	260	* SYPCR - System Protection Control 11-9
	261	* SYPCR can only be written once after reset!
	262	*-----------------------------------------------------------------------
	263	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	264	*/
	265	#if defined(CONFIG_WATCHDOG)
	266	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	267	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	268	#else
	269	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	270	#endif
	271
	272	/*-----------------------------------------------------------------------
	273	* SIUMCR - SIU Module Configuration 11-6
	274	*-----------------------------------------------------------------------
	275	* PCMCIA config., multi-function pin tri-state
	276	*/
c178d3da	277	#ifndef CONFIG_CAN_DRIVER
d4ca31c4 WD	278	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	279	#else /* we must activate GPL5 in the SIUMCR for CAN */
	280	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	281	#endif /* CONFIG_CAN_DRIVER */
	282
	283	/*-----------------------------------------------------------------------
	284	* TBSCR - Time Base Status and Control 11-26
	285	*-----------------------------------------------------------------------
	286	* Clear Reference Interrupt Status, Timebase freezing enabled
	287	*/
	288	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	289
d4ca31c4 WD	290	/*-----------------------------------------------------------------------
	291	* PISCR - Periodic Interrupt Status and Control 11-31
	292	*-----------------------------------------------------------------------
	293	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	294	*/
	295	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	296
d4ca31c4 WD	297	/*-----------------------------------------------------------------------
	298	* SCCR - System Clock and reset Control Register 15-27
	299	*-----------------------------------------------------------------------
	300	* Set clock output, timebase and RTC source and divider,
	301	* power management and some other internal clocks
	302	*/
	303	#define SCCR_MASK SCCR_EBDF11
c178d3da	304	#define CFG_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
d4ca31c4 WD	305	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
d4ca31c4 WD	306	SCCR_DFALCD00)
d4ca31c4 WD	307
	308	/*-----------------------------------------------------------------------
	309	* PCMCIA stuff
	310	*-----------------------------------------------------------------------
	311	*
	312	*/
	313	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	314	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	315	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	316	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	317	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	318	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	319	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
	320	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
	321
	322	/*-----------------------------------------------------------------------
	323	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	324	*-----------------------------------------------------------------------
	325	*/
	326
c178d3da	327	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
d4ca31c4	328
c178d3da WD	329	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
c178d3da WD	330	#undef CONFIG_IDE_LED /* LED for ide not supported */
d4ca31c4 WD	331	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	332
	333	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	334	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	335
	336	#define CFG_ATA_IDE0_OFFSET 0x0000
	337
	338	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	339
	340	/* Offset for data I/O */
	341	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
	342
	343	/* Offset for normal register accesses */
	344	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
	345
	346	/* Offset for alternate registers */
	347	#define CFG_ATA_ALT_OFFSET 0x0100
	348
	349	/*-----------------------------------------------------------------------
	350	*
	351	*-----------------------------------------------------------------------
	352	*
	353	*/
c178d3da	354	#define CFG_DER 0
d4ca31c4 WD	355
	356	/*
	357	* Init Memory Controller:
	358	*
	359	* BR0/1 and OR0/1 (FLASH)
	360	*/
	361
	362	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	363	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	364
	365	/* used to re-map FLASH both when starting from SRAM or FLASH:
	366	* restrict access enough to keep SRAM working (if any)
	367	* but not too much to meddle with FLASH accesses
	368	*/
	369	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	370	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	371
	372	/*
c178d3da	373	* FLASH timing: Default value of OR0 after reset
d4ca31c4	374	*/
c178d3da WD	375	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_MSK \| OR_BI \| \
c178d3da WD	376	OR_SCY_15_CLK \| OR_TRLX)
d4ca31c4 WD	377
	378	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	379	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	380	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
	381
	382	#define CFG_OR1_REMAP CFG_OR0_REMAP
	383	#define CFG_OR1_PRELIM CFG_OR0_PRELIM
	384	#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
	385
	386	/*
	387	* BR2/3 and OR2/3 (SDRAM)
	388	*
	389	*/
	390	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	391	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
c178d3da	392	#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
d4ca31c4 WD	393
	394	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	395	#define CFG_OR_TIMING_SDRAM 0x00000A00
	396
	397	#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
	398	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	399
c178d3da WD	400	#ifndef CONFIG_CAN_DRIVER
c178d3da WD	401	#define CFG_OR3_PRELIM CFG_OR2_PRELIM
d4ca31c4 WD	402	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
d4ca31c4 WD	403	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
c178d3da	404	#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
d4ca31c4 WD	405	#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	406	#define CFG_OR3_CAN (CFG_CAN_OR_AM \| OR_G5LA \| OR_BI)
	407	#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) \| \
	408	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	409	#endif /* CONFIG_CAN_DRIVER */
	410
c178d3da	411	/*
c178d3da WD	412	* 4096 Rows from SDRAM example configuration
	413	* 1000 factor s -> ms
	414	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
	415	* 4 Number of refresh cycles per period
	416	* 64 Refresh cycle in ms per number of rows
	417	*/
66ca92a5	418	#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
c178d3da	419
d4ca31c4 WD	420	/*
d4ca31c4 WD	421	* Memory Periodic Timer Prescaler
c178d3da	422	* Periodic timer for refresh, start with refresh rate for 40 MHz clock
66ca92a5	423	* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
d4ca31c4	424	*/
c178d3da	425	#define CFG_MAMR_PTA 39
d4ca31c4 WD	426
	427	/*
	428	* For 16 MBit, refresh rates could be 31.3 us
	429	* (= 64 ms / 2K = 125 / quad bursts).
	430	* For a simpler initialization, 15.6 us is used instead.
	431	*
	432	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
	433	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
	434	*/
	435	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	436	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	437
	438	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	439	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	440	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	441
	442	/*
	443	* MAMR settings for SDRAM
	444	*/
	445
	446	/* 8 column SDRAM */
	447	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	448	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	449	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	450	/* 9 column SDRAM */
	451	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	452	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	453	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
c178d3da WD	454	/* 10 column SDRAM */
	455	#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	456	MAMR_AMA_TYPE_2 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A9 \| \
	457	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
d4ca31c4 WD	458
	459	/*
	460	* Internal Definitions
	461	*
	462	* Boot Flags
	463	*/
c178d3da	464	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
d4ca31c4 WD	465	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	466
	467	#define CONFIG_SCC1_ENET
	468	#define CONFIG_FEC_ENET
	469	#define CONFIG_ETHPRIME "SCC ETHERNET"
	470
	471	#endif /* __CONFIG_H */