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9531a238 SP |
1 | /* |
2 | * (C) Copyright 2003-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2010 | |
6 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
9531a238 SP |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 | 19 | #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ |
9531a238 SP |
20 | #define CONFIG_A4M072 1 /* ... on A4M072 board */ |
21 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
746a36a1 | 22 | #define CONFIG_DISPLAY_BOARDINFO |
9531a238 | 23 | |
c8d76eaf WD |
24 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
25 | ||
9531a238 SP |
26 | #define CONFIG_MISC_INIT_R |
27 | ||
28 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
29 | ||
9531a238 SP |
30 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
31 | ||
32 | /* | |
33 | * Serial console configuration | |
34 | */ | |
35 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
36 | #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ | |
37 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
38 | /* define to enable silent console */ | |
39 | #define CONFIG_SILENT_CONSOLE | |
40 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ | |
41 | ||
42 | /* | |
43 | * PCI Mapping: | |
44 | * 0x40000000 - 0x4fffffff - PCI Memory | |
45 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
46 | */ | |
47 | #define CONFIG_PCI | |
48 | ||
49 | #if defined(CONFIG_PCI) | |
50 | #define CONFIG_PCI_PNP 1 | |
51 | #define CONFIG_PCI_SCAN_SHOW 1 | |
52 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 | |
53 | ||
54 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
55 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
56 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
57 | ||
58 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
59 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
60 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
61 | #endif | |
62 | ||
63 | #define CONFIG_SYS_XLB_PIPELINING 1 | |
64 | ||
071bc923 | 65 | #undef CONFIG_EEPRO100 |
9531a238 SP |
66 | |
67 | /* Partitions */ | |
68 | #define CONFIG_MAC_PARTITION | |
69 | #define CONFIG_DOS_PARTITION | |
70 | ||
71 | /* USB */ | |
72 | #define CONFIG_USB_OHCI_NEW | |
73 | #define CONFIG_USB_STORAGE | |
74 | #define CONFIG_SYS_OHCI_BE_CONTROLLER | |
75 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT | |
76 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
77 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
78 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
79 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
80 | ||
81 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
82 | ||
83 | /* | |
84 | * BOOTP options | |
85 | */ | |
86 | #define CONFIG_BOOTP_BOOTFILESIZE | |
87 | #define CONFIG_BOOTP_BOOTPATH | |
88 | #define CONFIG_BOOTP_GATEWAY | |
89 | #define CONFIG_BOOTP_HOSTNAME | |
90 | ||
9531a238 SP |
91 | /* |
92 | * Command line configuration. | |
93 | */ | |
9531a238 | 94 | #define CONFIG_CMD_EEPROM |
9531a238 | 95 | #define CONFIG_CMD_IDE |
cb5639cb | 96 | #define CONFIG_CMD_DISPLAY |
9531a238 SP |
97 | |
98 | #if defined(CONFIG_PCI) | |
99 | #define CONFIG_CMD_PCI | |
100 | #endif | |
101 | ||
c8d76eaf | 102 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ |
9531a238 SP |
103 | #define CONFIG_SYS_LOWBOOT 1 |
104 | #define CONFIG_SYS_LOWBOOT32 1 | |
105 | #endif | |
106 | ||
107 | /* | |
108 | * Autobooting | |
109 | */ | |
9531a238 SP |
110 | |
111 | #define CONFIG_SYS_AUTOLOAD "n" | |
112 | ||
9531a238 SP |
113 | #undef CONFIG_BOOTARGS |
114 | #define CONFIG_PREBOOT "run try_update" | |
115 | ||
116 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
7ae54992 IY |
117 | "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \ |
118 | "cf1=diskboot 200000 0:1\0" \ | |
119 | "bootcmd_cf1=run bcf1\0" \ | |
120 | "bcf=setenv bootargs root=/dev/hda3\0" \ | |
121 | "bootcmd_nfs=run bnfs\0" \ | |
122 | "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\ | |
123 | "panic=1\0" \ | |
124 | "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \ | |
125 | "run norargs addip; run bk\0" \ | |
126 | "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \ | |
127 | "run nfsargs addip ; run bk\0" \ | |
128 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
129 | "nfsroot=${serverip}:${rootpath}\0" \ | |
130 | "try_update=usb start;sleep 2;usb start;sleep 1;" \ | |
131 | "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \ | |
132 | "source 2F0000\0" \ | |
133 | "env_addr=FE060000\0" \ | |
134 | "kernel_addr=FE100000\0" \ | |
135 | "rootfs_addr=FE200000\0" \ | |
136 | "add_mtd=setenv bootargs ${bootargs} mtdparts=" \ | |
137 | "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \ | |
138 | "bcf1=run cf1; run bcf; run addip; run bk\0" \ | |
139 | "add_consolespec=setenv bootargs ${bootargs} " \ | |
140 | "console=/dev/null quiet\0" \ | |
141 | "addip=if test -n ${ethaddr};" \ | |
142 | "then if test -n ${ipaddr};" \ | |
143 | "then setenv bootargs ${bootargs} " \ | |
144 | "ip=${ipaddr}:${serverip}:${gatewayip}:"\ | |
145 | "${netmask}:${hostname}:${netdev}:off;" \ | |
146 | "fi;" \ | |
147 | "else;" \ | |
148 | "setenv bootargs ${bootargs} no_ethaddr;" \ | |
149 | "fi\0" \ | |
150 | "hostname=CPUP0\0" \ | |
7ae54992 IY |
151 | "netdev=eth0\0" \ |
152 | "bootcmd=run bootcmd_nor\0" \ | |
9531a238 SP |
153 | "" |
154 | /* | |
155 | * IPB Bus clocking configuration. | |
156 | */ | |
157 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ | |
158 | ||
159 | /* | |
160 | * I2C configuration | |
161 | */ | |
162 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
163 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ | |
164 | ||
165 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
166 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
167 | ||
168 | /* | |
169 | * EEPROM configuration | |
170 | */ | |
171 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */ | |
172 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
173 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
174 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
175 | #define CONFIG_SYS_EEPROM_WREN 1 | |
176 | #define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4 | |
177 | ||
178 | /* | |
179 | * Flash configuration | |
180 | */ | |
181 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 | |
182 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
183 | #if !defined(CONFIG_SYS_LOWBOOT) | |
184 | #error "CONFIG_SYS_LOWBOOT not defined?" | |
185 | #else /* CONFIG_SYS_LOWBOOT */ | |
186 | #if defined(CONFIG_SYS_LOWBOOT32) | |
187 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) | |
188 | #endif | |
189 | #endif /* CONFIG_SYS_LOWBOOT */ | |
190 | ||
191 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
192 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
193 | #define CONFIG_FLASH_CFI_DRIVER | |
194 | #define CONFIG_SYS_FLASH_CFI | |
195 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
196 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START} | |
e36aff68 | 197 | #define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE} |
9531a238 SP |
198 | |
199 | /* | |
200 | * Environment settings | |
201 | */ | |
202 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
203 | #define CONFIG_ENV_SIZE 0x10000 | |
204 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
205 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
206 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
207 | ||
208 | #define CONFIG_ENV_OVERWRITE 1 | |
209 | ||
210 | /* | |
211 | * Memory map | |
212 | */ | |
213 | #define CONFIG_SYS_MBAR 0xF0000000 | |
214 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
215 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
216 | ||
217 | /* Use SRAM until RAM will be available */ | |
218 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
553f0982 | 219 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
9531a238 | 220 | |
25ddd1fb | 221 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
9531a238 SP |
222 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
223 | ||
c8d76eaf | 224 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
9531a238 SP |
225 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
226 | # define CONFIG_SYS_RAMBOOT 1 | |
227 | #endif | |
228 | ||
229 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ | |
230 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
231 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
232 | ||
233 | /* | |
234 | * Ethernet configuration | |
235 | */ | |
236 | #define CONFIG_MPC5xxx_FEC 1 | |
237 | #define CONFIG_MPC5xxx_FEC_MII100 | |
238 | /* | |
239 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb | |
240 | */ | |
241 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ | |
242 | #define CONFIG_PHY_ADDR 0x1f | |
243 | #define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */ | |
244 | ||
245 | /* | |
246 | * GPIO configuration | |
247 | */ | |
cb5639cb | 248 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004 |
9531a238 SP |
249 | |
250 | /* | |
251 | * Miscellaneous configurable options | |
252 | */ | |
9531a238 | 253 | #define CONFIG_CMDLINE_EDITING 1 |
9531a238 | 254 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
9531a238 SP |
255 | #if defined(CONFIG_CMD_KGDB) |
256 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
257 | #else | |
258 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
259 | #endif | |
260 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
261 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
262 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
263 | ||
264 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ | |
265 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
266 | ||
267 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
268 | ||
9531a238 SP |
269 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
270 | #if defined(CONFIG_CMD_KGDB) | |
271 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
272 | #endif | |
273 | ||
9531a238 SP |
274 | /* |
275 | * Various low-level settings | |
276 | */ | |
277 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI | |
278 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
279 | /* Flash at CSBoot, CS0 */ | |
280 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
281 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
282 | #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 | |
283 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
284 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
285 | /* External SRAM at CS1 */ | |
286 | #define CONFIG_SYS_CS1_START 0x62000000 | |
287 | #define CONFIG_SYS_CS1_SIZE 0x00400000 | |
288 | #define CONFIG_SYS_CS1_CFG 0x00009930 | |
289 | #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START | |
290 | #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE | |
cb5639cb IY |
291 | /* LED display at CS7 */ |
292 | #define CONFIG_SYS_CS7_START 0x6a000000 | |
293 | #define CONFIG_SYS_CS7_SIZE (64*1024) | |
294 | #define CONFIG_SYS_CS7_CFG 0x0000bf30 | |
9531a238 SP |
295 | |
296 | #define CONFIG_SYS_CS_BURST 0x00000000 | |
297 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333003 | |
298 | ||
299 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
300 | ||
301 | /*----------------------------------------------------------------------- | |
302 | * USB stuff | |
303 | *----------------------------------------------------------------------- | |
304 | */ | |
305 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
306 | #define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */ | |
307 | ||
308 | /*----------------------------------------------------------------------- | |
309 | * IDE/ATA stuff Supports IDE harddisk | |
310 | *----------------------------------------------------------------------- | |
311 | */ | |
312 | ||
313 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
314 | ||
315 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
316 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
317 | ||
318 | #define CONFIG_IDE_PREINIT | |
319 | ||
320 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
321 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ | |
322 | ||
323 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
324 | ||
325 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
326 | ||
327 | /* Offset for data I/O */ | |
328 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) | |
329 | ||
330 | /* Offset for normal register accesses */ | |
331 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
332 | ||
333 | /* Offset for alternate registers */ | |
334 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) | |
335 | ||
336 | /* Interval between registers */ | |
337 | #define CONFIG_SYS_ATA_STRIDE 4 | |
338 | ||
339 | #define CONFIG_ATAPI 1 | |
340 | ||
341 | /*----------------------------------------------------------------------- | |
342 | * Open firmware flat tree support | |
343 | *----------------------------------------------------------------------- | |
344 | */ | |
9531a238 SP |
345 | #define OF_CPU "PowerPC,5200@0" |
346 | #define OF_SOC "soc5200@f0000000" | |
347 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
348 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
349 | ||
cb5639cb IY |
350 | /* Support for the 7-segment display */ |
351 | #define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START | |
352 | #define CONFIG_SHOW_ACTIVITY /* used for display realization */ | |
353 | ||
92d1a400 IY |
354 | #define CONFIG_SHOW_BOOT_PROGRESS |
355 | ||
9531a238 | 356 | #endif /* __CONFIG_H */ |