[people/ms/u-boot.git] / include / configs / a4m072.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2010
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
#define CONFIG_A4M072		1	/* ... on A4M072 board */
#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */

#define CONFIG_SYS_TEXT_BASE	0xFE000000

#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
/* define to enable silent console */
#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */

#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#undef CONFIG_EEPRO100

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DISPLAY

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif

#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
#define CONFIG_SYS_LOWBOOT		1
#define CONFIG_SYS_LOWBOOT32		1
#endif

/*
 * Autobooting
 */

#define CONFIG_SYS_AUTOLOAD	"n"

#undef	CONFIG_BOOTARGS
#define CONFIG_PREBOOT				"run try_update"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"		\
	"cf1=diskboot 200000 0:1\0"					\
	"bootcmd_cf1=run bcf1\0"					\
	"bcf=setenv bootargs root=/dev/hda3\0"				\
	"bootcmd_nfs=run bnfs\0"					\
	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
		"panic=1\0"						\
	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"		\
			"run norargs addip; run bk\0"			\
	"bnfs=nfs 200000 ${rootpath}/boot/uImage;"			\
			"run nfsargs addip ; run bk\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
				"nfsroot=${serverip}:${rootpath}\0"	\
	"try_update=usb start;sleep 2;usb start;sleep 1;"		\
			"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"	\
			"source 2F0000\0"				\
	"env_addr=FE060000\0"						\
	"kernel_addr=FE100000\0"					\
	"rootfs_addr=FE200000\0"					\
	"add_mtd=setenv bootargs ${bootargs} mtdparts="			\
		"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
	"bcf1=run cf1; run bcf; run addip; run bk\0"			\
	"add_consolespec=setenv bootargs ${bootargs} "			\
				"console=/dev/null quiet\0"		\
	"addip=if test -n ${ethaddr};"					\
		"then if test -n ${ipaddr};"				\
			"then setenv bootargs ${bootargs} "		\
				"ip=${ipaddr}:${serverip}:${gatewayip}:"\
				"${netmask}:${hostname}:${netdev}:off;"	\
			"fi;"						\
		"else;"							\
			"setenv bootargs ${bootargs} no_ethaddr;"	\
		"fi\0"							\
	"hostname=CPUP0\0"						\
	"netdev=eth0\0"							\
	"bootcmd=run bootcmd_nor\0" 					\
	""
/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C			1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1010010x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
#define CONFIG_SYS_EEPROM_WREN			1
#define CONFIG_SYS_EEPROM_WP			GPIO_PSC2_4

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#if !defined(CONFIG_SYS_LOWBOOT)
#error "CONFIG_SYS_LOWBOOT not defined?"
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT32)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
#endif
#endif	/* CONFIG_SYS_LOWBOOT */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS0_START}
#define CONFIG_SYS_FLASH_BANKS_SIZES	{CONFIG_SYS_CS0_SIZE}

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE	0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x1f
#define CONFIG_PHY_TYPE		0x79c874		/* AMD Phy Controller */

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x18000004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE
/* Flash at CSBoot, CS0 */
#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
/* External SRAM at CS1 */
#define CONFIG_SYS_CS1_START		0x62000000
#define CONFIG_SYS_CS1_SIZE		0x00400000
#define CONFIG_SYS_CS1_CFG		0x00009930
#define CONFIG_SYS_SRAM_BASE		CONFIG_SYS_CS1_START
#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE
/* LED display at CS7 */
#define CONFIG_SYS_CS7_START		0x6a000000
#define CONFIG_SYS_CS7_SIZE		(64*1024)
#define CONFIG_SYS_CS7_CFG		0x0000bf30

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE		0x33333003

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000 /* 0x4000 for SE mode */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#define CONFIG_ATAPI                   1

/*-----------------------------------------------------------------------
 * Open firmware flat tree support
 *-----------------------------------------------------------------------
 */
#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

/* Support for the 7-segment display */
#define CONFIG_SYS_DISP_CHR_RAM	     CONFIG_SYS_CS7_START
#define CONFIG_SHOW_ACTIVITY		/* used for display realization */

#define CONFIG_SHOW_BOOT_PROGRESS

#endif /* __CONFIG_H */
Commit	Line	Data
9531a238 SP	1	/*
	2	* (C) Copyright 2003-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2010
	6	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
9531a238 SP	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	* (easy to change)
	17	*/
	18
b2a6dfe4	19	#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
9531a238 SP	20	#define CONFIG_A4M072 1 /* ... on A4M072 board */
	21	#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	22
c8d76eaf WD	23	#define CONFIG_SYS_TEXT_BASE 0xFE000000
c8d76eaf WD	24
9531a238 SP	25	#define CONFIG_MISC_INIT_R
	26
	27	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	28
9531a238 SP	29	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	30
	31	/*
	32	* Serial console configuration
	33	*/
	34	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	35	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
	36	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	37	/* define to enable silent console */
9531a238 SP	38	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
	39
	40	/*
	41	* PCI Mapping:
	42	* 0x40000000 - 0x4fffffff - PCI Memory
	43	* 0x50000000 - 0x50ffffff - PCI IO Space
	44	*/
9531a238 SP	45
9531a238 SP	46	#if defined(CONFIG_PCI)
9531a238 SP	47	#define CONFIG_PCI_SCAN_SHOW 1
	48	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
	49
	50	#define CONFIG_PCI_MEM_BUS 0x40000000
	51	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	52	#define CONFIG_PCI_MEM_SIZE 0x10000000
	53
	54	#define CONFIG_PCI_IO_BUS 0x50000000
	55	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	56	#define CONFIG_PCI_IO_SIZE 0x01000000
	57	#endif
	58
	59	#define CONFIG_SYS_XLB_PIPELINING 1
	60
071bc923	61	#undef CONFIG_EEPRO100
9531a238 SP	62
	63	/* Partitions */
	64	#define CONFIG_MAC_PARTITION
	65	#define CONFIG_DOS_PARTITION
	66
	67	/* USB */
	68	#define CONFIG_USB_OHCI_NEW
9531a238 SP	69	#define CONFIG_SYS_OHCI_BE_CONTROLLER
	70	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	71	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	72	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
	73	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
	74	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	75
	76	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	77
	78	/*
	79	* BOOTP options
	80	*/
	81	#define CONFIG_BOOTP_BOOTFILESIZE
	82	#define CONFIG_BOOTP_BOOTPATH
	83	#define CONFIG_BOOTP_GATEWAY
	84	#define CONFIG_BOOTP_HOSTNAME
	85
9531a238 SP	86	/*
	87	* Command line configuration.
	88	*/
9531a238	89	#define CONFIG_CMD_EEPROM
9531a238	90	#define CONFIG_CMD_IDE
cb5639cb	91	#define CONFIG_CMD_DISPLAY
9531a238 SP	92
	93	#if defined(CONFIG_PCI)
	94	#define CONFIG_CMD_PCI
	95	#endif
	96
c8d76eaf	97	#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
9531a238 SP	98	#define CONFIG_SYS_LOWBOOT 1
	99	#define CONFIG_SYS_LOWBOOT32 1
	100	#endif
	101
	102	/*
	103	* Autobooting
	104	*/
9531a238 SP	105
	106	#define CONFIG_SYS_AUTOLOAD "n"
	107
9531a238 SP	108	#undef CONFIG_BOOTARGS
	109	#define CONFIG_PREBOOT "run try_update"
	110
	111	#define CONFIG_EXTRA_ENV_SETTINGS \
7ae54992 IY	112	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
	113	"cf1=diskboot 200000 0:1\0" \
	114	"bootcmd_cf1=run bcf1\0" \
	115	"bcf=setenv bootargs root=/dev/hda3\0" \
	116	"bootcmd_nfs=run bnfs\0" \
	117	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
	118	"panic=1\0" \
	119	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \
	120	"run norargs addip; run bk\0" \
	121	"bnfs=nfs 200000 ${rootpath}/boot/uImage;" \
	122	"run nfsargs addip ; run bk\0" \
	123	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	124	"nfsroot=${serverip}:${rootpath}\0" \
	125	"try_update=usb start;sleep 2;usb start;sleep 1;" \
	126	"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \
	127	"source 2F0000\0" \
	128	"env_addr=FE060000\0" \
	129	"kernel_addr=FE100000\0" \
	130	"rootfs_addr=FE200000\0" \
	131	"add_mtd=setenv bootargs ${bootargs} mtdparts=" \
	132	"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
	133	"bcf1=run cf1; run bcf; run addip; run bk\0" \
	134	"add_consolespec=setenv bootargs ${bootargs} " \
	135	"console=/dev/null quiet\0" \
	136	"addip=if test -n ${ethaddr};" \
	137	"then if test -n ${ipaddr};" \
	138	"then setenv bootargs ${bootargs} " \
	139	"ip=${ipaddr}:${serverip}:${gatewayip}:"\
	140	"${netmask}:${hostname}:${netdev}:off;" \
	141	"fi;" \
	142	"else;" \
	143	"setenv bootargs ${bootargs} no_ethaddr;" \
	144	"fi\0" \
	145	"hostname=CPUP0\0" \
7ae54992 IY	146	"netdev=eth0\0" \
7ae54992 IY	147	"bootcmd=run bootcmd_nor\0" \
9531a238 SP	148	""
	149	/*
	150	* IPB Bus clocking configuration.
	151	*/
	152	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
	153
	154	/*
	155	* I2C configuration
	156	*/
	157	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	158	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	159
	160	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	161	#define CONFIG_SYS_I2C_SLAVE 0x7F
	162
	163	/*
	164	* EEPROM configuration
	165	*/
	166	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
	167	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	168	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	169	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	170	#define CONFIG_SYS_EEPROM_WREN 1
	171	#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
	172
	173	/*
	174	* Flash configuration
	175	*/
	176	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	177	#define CONFIG_SYS_FLASH_SIZE 0x02000000
	178	#if !defined(CONFIG_SYS_LOWBOOT)
	179	#error "CONFIG_SYS_LOWBOOT not defined?"
	180	#else /* CONFIG_SYS_LOWBOOT */
	181	#if defined(CONFIG_SYS_LOWBOOT32)
	182	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
	183	#endif
	184	#endif /* CONFIG_SYS_LOWBOOT */
	185
	186	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	187	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	188	#define CONFIG_FLASH_CFI_DRIVER
	189	#define CONFIG_SYS_FLASH_CFI
	190	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	191	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
e36aff68	192	#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE}
9531a238 SP	193
	194	/*
	195	* Environment settings
	196	*/
	197	#define CONFIG_ENV_IS_IN_FLASH 1
	198	#define CONFIG_ENV_SIZE 0x10000
	199	#define CONFIG_ENV_SECT_SIZE 0x20000
	200	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	201	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	202
	203	#define CONFIG_ENV_OVERWRITE 1
	204
	205	/*
	206	* Memory map
	207	*/
	208	#define CONFIG_SYS_MBAR 0xF0000000
	209	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	210	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	211
	212	/* Use SRAM until RAM will be available */
	213	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	214	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
9531a238	215
25ddd1fb	216	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
9531a238 SP	217	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9531a238 SP	218
c8d76eaf	219	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
9531a238 SP	220	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	221	# define CONFIG_SYS_RAMBOOT 1
	222	#endif
	223
	224	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	225	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	226	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	227
	228	/*
	229	* Ethernet configuration
	230	*/
	231	#define CONFIG_MPC5xxx_FEC 1
	232	#define CONFIG_MPC5xxx_FEC_MII100
	233	/*
	234	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
	235	*/
	236	/* #define CONFIG_MPC5xxx_FEC_MII10 */
	237	#define CONFIG_PHY_ADDR 0x1f
	238	#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
	239
	240	/*
	241	* GPIO configuration
	242	*/
cb5639cb	243	#define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004
9531a238 SP	244
	245	/*
	246	* Miscellaneous configurable options
	247	*/
9531a238	248	#define CONFIG_CMDLINE_EDITING 1
9531a238	249	#define CONFIG_SYS_LONGHELP /* undef to save memory */
9531a238 SP	250	#if defined(CONFIG_CMD_KGDB)
	251	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	252	#else
	253	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	254	#endif
	255	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	256	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	257	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	258
	259	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	260	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	261
	262	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
	263
9531a238 SP	264	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	265	#if defined(CONFIG_CMD_KGDB)
	266	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	267	#endif
	268
9531a238 SP	269	/*
	270	* Various low-level settings
	271	*/
	272	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	273	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	274	/* Flash at CSBoot, CS0 */
	275	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	276	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	277	#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
	278	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	279	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	280	/* External SRAM at CS1 */
	281	#define CONFIG_SYS_CS1_START 0x62000000
	282	#define CONFIG_SYS_CS1_SIZE 0x00400000
	283	#define CONFIG_SYS_CS1_CFG 0x00009930
	284	#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
	285	#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
cb5639cb IY	286	/* LED display at CS7 */
	287	#define CONFIG_SYS_CS7_START 0x6a000000
	288	#define CONFIG_SYS_CS7_SIZE (64*1024)
	289	#define CONFIG_SYS_CS7_CFG 0x0000bf30
9531a238 SP	290
	291	#define CONFIG_SYS_CS_BURST 0x00000000
	292	#define CONFIG_SYS_CS_DEADCYCLE 0x33333003
	293
	294	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
	295
	296	/*-----------------------------------------------------------------------
	297	* USB stuff
	298	*-----------------------------------------------------------------------
	299	*/
	300	#define CONFIG_USB_CLOCK 0x0001BBBB
	301	#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
	302
	303	/*-----------------------------------------------------------------------
	304	* IDE/ATA stuff Supports IDE harddisk
	305	*-----------------------------------------------------------------------
	306	*/
	307
	308	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	309
	310	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	311	#undef CONFIG_IDE_LED /* LED for ide not supported */
	312
	313	#define CONFIG_IDE_PREINIT
	314
	315	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	316	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
	317
	318	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	319
	320	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	321
	322	/* Offset for data I/O */
	323	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
	324
	325	/* Offset for normal register accesses */
	326	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
	327
	328	/* Offset for alternate registers */
	329	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
	330
	331	/* Interval between registers */
	332	#define CONFIG_SYS_ATA_STRIDE 4
	333
	334	#define CONFIG_ATAPI 1
	335
	336	/*-----------------------------------------------------------------------
	337	* Open firmware flat tree support
	338	*-----------------------------------------------------------------------
	339	*/
9531a238 SP	340	#define OF_CPU "PowerPC,5200@0"
	341	#define OF_SOC "soc5200@f0000000"
	342	#define OF_TBCLK (bd->bi_busfreq / 4)
	343	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	344
cb5639cb IY	345	/* Support for the 7-segment display */
	346	#define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START
	347	#define CONFIG_SHOW_ACTIVITY /* used for display realization */
	348
92d1a400 IY	349	#define CONFIG_SHOW_BOOT_PROGRESS
92d1a400 IY	350
9531a238	351	#endif /* __CONFIG_H */