[people/ms/u-boot.git] / include / configs / ads5121.h

/*
 * (C) Copyright 2007 DENX Software Engineering
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * ADS5121 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Memory map for the ADS5121 board:
 *
 * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
 * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
 * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
 * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
 * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
 * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
 * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
 * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
 */

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC512X		1	/* MPC512X family */

/* CONFIG_PCI is defined at config time */

#define CFG_MPC512X_CLKIN	66000000	/* in Hz */

#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */

#define CFG_IMMR		0x80000000

#define CFG_MEMTEST_START	0x00200000      /* memtest region */
#define CFG_MEMTEST_END		0x00400000

/*
 * DDR Setup - manually set all parameters as there's no SPD etc.
 */
#define CFG_DDR_SIZE		256		/* MB */
#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_BASE

/* DDR Controller Configuration
 *
 * SYS_CFG:
 *	[31:31]	MDDRC Soft Reset:	Diabled
 *	[30:30]	DRAM CKE pin:		Enabled
 *	[29:29]	DRAM CLK:		Enabled
 *	[28:28]	Command Mode:		Enabled (For initialization only)
 *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
 *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
 *	[20:19]	Read Test:		DON'T USE
 *	[18:18]	Self Refresh:		Enabled
 *	[17:17]	16bit Mode:		Disabled
 *	[16:13] Ready Delay:		2
 *	[12:12]	Half DQS Delay:		Disabled
 *	[11:11]	Quarter DQS Delay:	Disabled
 *	[10:08]	Write Delay:		2
 *	[07:07]	Early ODT:		Disabled
 *	[06:06]	On DIE Termination:	Disabled
 *	[05:05]	FIFO Overflow Clear:	DON'T USE here
 *	[04:04]	FIFO Underflow Clear:	DON'T USE here
 *	[03:03]	FIFO Overflow Pending:	DON'T USE here
 *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
 *	[01:01]	FIFO Overlfow Enabled:	Enabled
 *	[00:00]	FIFO Underflow Enabled:	Enabled
 * TIME_CFG0
 *	[31:16]	DRAM Refresh Time:	0 CSB clocks
 *	[15:8]	DRAM Command Time:	0 CSB clocks
 *	[07:00]	DRAM Precharge Time:	0 CSB clocks
 * TIME_CFG1
 *	[31:26]	DRAM tRFC:
 *	[25:21]	DRAM tWR1:
 *	[20:17]	DRAM tWRT1:
 *	[16:11]	DRAM tDRR:
 *	[10:05]	DRAM tRC:
 *	[04:00]	DRAM tRAS:
 * TIME_CFG2
 *	[31:28]	DRAM tRCD:
 *	[27:23]	DRAM tFAW:
 *	[22:19]	DRAM tRTW1:
 *	[18:15]	DRAM tCCD:
 *	[14:10] DRAM tRTP:
 *	[09:05]	DRAM tRP:
 *	[04:00] DRAM tRPA
 */

#define CFG_MDDRC_SYS_CFG	0xF8604A00
#define CFG_MDDRC_SYS_CFG_RUN	0xE8604A00
#define CFG_MDDRC_SYS_CFG_EN	0xF0000000
#define CFG_MDDRC_TIME_CFG0	0x00003D2E
#define CFG_MDDRC_TIME_CFG0_RUN	0x06183D2E
#define CFG_MDDRC_TIME_CFG1	0x54EC1168
#define CFG_MDDRC_TIME_CFG2	0x35210864

#define CFG_MICRON_NOP		0x01380000
#define CFG_MICRON_PCHG_ALL	0x01100400
#define CFG_MICRON_EM2		0x01020000
#define CFG_MICRON_EM3		0x01030000
#define CFG_MICRON_EN_DLL	0x01010000
#define CFG_MICRON_RFSH		0x01080000
#define CFG_MICRON_INIT_DEV_OP	0x01000432
#define CFG_MICRON_OCD_DEFAULT	0x01010780

/* DDR Priority Manager Configuration */
#define CFG_MDDRCGRP_PM_CFG1	0x000777AA
#define CFG_MDDRCGRP_PM_CFG2	0x00000055
#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000000
#define CFG_MDDRCGRP_LUT0_MU    0x11111117
#define CFG_MDDRCGRP_LUT0_ML	0x7777777A
#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
#define CFG_MDDRCGRP_LUT1_ML	0xEEEEEEEE
#define CFG_MDDRCGRP_LUT2_MU    0x44444444
#define CFG_MDDRCGRP_LUT2_ML	0x44444444
#define CFG_MDDRCGRP_LUT3_MU    0x55555555
#define CFG_MDDRCGRP_LUT3_ML	0x55555558
#define CFG_MDDRCGRP_LUT4_MU    0x11111111
#define CFG_MDDRCGRP_LUT4_ML	0x1111117C
#define CFG_MDDRCGRP_LUT0_AU    0x33333377
#define CFG_MDDRCGRP_LUT0_AL	0x7777EEEE
#define CFG_MDDRCGRP_LUT1_AU    0x11111111
#define CFG_MDDRCGRP_LUT1_AL	0x11111111
#define CFG_MDDRCGRP_LUT2_AU    0x11111111
#define CFG_MDDRCGRP_LUT2_AL	0x11111111
#define CFG_MDDRCGRP_LUT3_AU    0x11111111
#define CFG_MDDRCGRP_LUT3_AL	0x11111111
#define CFG_MDDRCGRP_LUT4_AU    0x11111111
#define CFG_MDDRCGRP_LUT4_AL	0x11111111

/*
 * NOR FLASH on the Local Bus
 */
#define CFG_FLASH_CFI				/* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
#define CFG_FLASH_BASE		0xFC000000	/* start of FLASH   */
#define CFG_FLASH_SIZE		0x04000000	/* max flash size in bytes */
#define CFG_FLASH_USE_BUFFER_WRITE

#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE}
#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */

#undef CFG_FLASH_CHECKSUM

/*
 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 * window is 64KB
 */
#define CFG_CPLD_BASE		0x82000000
#define CFG_CPLD_SIZE		0x00010000	/* 64 KB */

#define CFG_SRAM_BASE		0x30000000
#define CFG_SRAM_SIZE		0x00020000	/* 128 KB */

#define CFG_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
#define CFG_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */

/* Use SRAM for initial stack */
#define CFG_INIT_RAM_ADDR	CFG_SRAM_BASE		/* Initial RAM address */
#define CFG_INIT_RAM_END	CFG_SRAM_SIZE		/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(512 * 1024)		/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX     1
#undef CONFIG_SERIAL_SOFTWARE_FIFO

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/*
 * PCI
 */
#ifdef CONFIG_PCI

/*
 * General PCI
 */
#define CFG_PCI_MEM_BASE	0xA0000000
#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
#define CFG_PCI_MMIO_BASE	(CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
#define CFG_PCI_IO_BASE		0x00000000
#define CFG_PCI_IO_PHYS		0x84000000
#define CFG_PCI_IO_SIZE		0x01000000	/* 16M */


#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif

/* I2C */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#if 0
#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
#endif

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
#define CFG_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC512x_FEC	1
#define CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR		0x1
#define CONFIG_MII		1	/* MII PHY management		*/

#if 0
/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1374			/* use ds1374 rtc via i2c	*/
#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
#endif

/*
 * Environment
 */
#define CFG_ENV_IS_IN_FLASH	1
/* This has to be a multiple of the Flash sector size */
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE		0x2000
#define CFG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_EEPROM

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif

/*
 * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
 * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 * to chapter 36 of the MPC5121e Reference Manual.
 */
/* #define CONFIG_WATCHDOG */		/* enable watchdog */
#define CFG_WATCHDOG_VALUE 0xFFFF

 /*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory */
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */

#ifdef CONFIG_CMD_KGDB
	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
#endif


#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

#define CFG_HID0_INIT	0x000000000
#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2	HID2_HBE

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot */

#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_TIMESTAMP

#define CONFIG_HOSTNAME		ads5121
#define CONFIG_BOOTFILE		ads5121/uImage
#define CONFIG_ROOTPATH		/opt/eldk/pcc_6xx

#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */

#define CONFIG_BAUDRATE		115200

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"u-boot_addr_r=200000\0"					\
	"kernel_addr_r=300000\0"					\
	"fdt_addr_r=400000\0"						\
	"ramdisk_addr_r=500000\0"					\
	"u-boot_addr=FFF00000\0"					\
	"kernel_addr=FC040000\0"					\
	"fdt_addr=FC2C0000\0"						\
	"ramdisk_addr=FC300000\0"					\
	"ramdiskfile=ads5121/uRamdisk\0"				\
	"fdtfile=ads5121/ads5121.dtb\0"					\
	"u-boot=ads5121/u-boot.bin\0"					\
	"netdev=eth0\0"							\
	"consdev=ttyPSC0\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consdev},${baudrate}\0"			\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"		\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
		"tftp ${fdt_addr_r} ${fdtfile};"				\
		"run ramargs addip addtty;"				\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
	"load=tftp ${u-boot_addr_r} ${u-boot}\0"				\
	"update=protect off ${u-boot_addr} +${filesize};"		\
		"era ${u-boot_addr} +${filesize};"			\
		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
	"upd=run load update\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5121@0"
#define OF_SOC			"soc@80000000"
#define OF_SOC_OLD		"soc5121@80000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"

#endif	/* __CONFIG_H */
Commit	Line	Data
8993e54b RJ	1	/*
	2	* (C) Copyright 2007 DENX Software Engineering
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/*
	24	* ADS5121 board configuration file
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
8993e54b RJ	30	/*
	31	* Memory map for the ADS5121 board:
	32	*
	33	* 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
	34	* 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
	35	* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
	36	* 0x8200_0000 - 0x8200_001F CPLD (32 B)
5f91db7f JR	37	* 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
	38	* 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
	39	* 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
8993e54b RJ	40	* 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
	41	*/
	42
	43	/*
	44	* High Level Configuration Options
	45	*/
	46	#define CONFIG_E300 1 /* E300 Family */
	47	#define CONFIG_MPC512X 1 /* MPC512X family */
	48
5f91db7f	49	/* CONFIG_PCI is defined at config time */
8993e54b RJ	50
	51	#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
	52
	53	#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
	54
	55	#define CFG_IMMR 0x80000000
	56
	57	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
	58	#define CFG_MEMTEST_END 0x00400000
	59
	60	/*
	61	* DDR Setup - manually set all parameters as there's no SPD etc.
	62	*/
	63	#define CFG_DDR_SIZE 256 /* MB */
	64	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
	65	#define CFG_SDRAM_BASE CFG_DDR_BASE
	66
	67	/* DDR Controller Configuration
b1b54e35 WD	68	*
	69	* SYS_CFG:
	70	* [31:31] MDDRC Soft Reset: Diabled
	71	* [30:30] DRAM CKE pin: Enabled
	72	* [29:29] DRAM CLK: Enabled
	73	* [28:28] Command Mode: Enabled (For initialization only)
	74	* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
	75	* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
	76	* [20:19] Read Test: DON'T USE
	77	* [18:18] Self Refresh: Enabled
	78	* [17:17] 16bit Mode: Disabled
	79	* [16:13] Ready Delay: 2
	80	* [12:12] Half DQS Delay: Disabled
	81	* [11:11] Quarter DQS Delay: Disabled
	82	* [10:08] Write Delay: 2
	83	* [07:07] Early ODT: Disabled
	84	* [06:06] On DIE Termination: Disabled
	85	* [05:05] FIFO Overflow Clear: DON'T USE here
	86	* [04:04] FIFO Underflow Clear: DON'T USE here
	87	* [03:03] FIFO Overflow Pending: DON'T USE here
	88	* [02:02] FIFO Underlfow Pending: DON'T USE here
	89	* [01:01] FIFO Overlfow Enabled: Enabled
	90	* [00:00] FIFO Underflow Enabled: Enabled
	91	* TIME_CFG0
	92	* [31:16] DRAM Refresh Time: 0 CSB clocks
	93	* [15:8] DRAM Command Time: 0 CSB clocks
	94	* [07:00] DRAM Precharge Time: 0 CSB clocks
	95	* TIME_CFG1
	96	* [31:26] DRAM tRFC:
	97	* [25:21] DRAM tWR1:
	98	* [20:17] DRAM tWRT1:
	99	* [16:11] DRAM tDRR:
	100	* [10:05] DRAM tRC:
	101	* [04:00] DRAM tRAS:
	102	* TIME_CFG2
	103	* [31:28] DRAM tRCD:
	104	* [27:23] DRAM tFAW:
	105	* [22:19] DRAM tRTW1:
	106	* [18:15] DRAM tCCD:
	107	* [14:10] DRAM tRTP:
	108	* [09:05] DRAM tRP:
	109	* [04:00] DRAM tRPA
	110	*/
8993e54b	111
37e3c62f GB	112	#define CFG_MDDRC_SYS_CFG 0xF8604A00
	113	#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
	114	#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
	115	#define CFG_MDDRC_TIME_CFG0 0x00003D2E
	116	#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
8993e54b RJ	117	#define CFG_MDDRC_TIME_CFG1 0x54EC1168
	118	#define CFG_MDDRC_TIME_CFG2 0x35210864
	119
	120	#define CFG_MICRON_NOP 0x01380000
	121	#define CFG_MICRON_PCHG_ALL 0x01100400
8993e54b RJ	122	#define CFG_MICRON_EM2 0x01020000
	123	#define CFG_MICRON_EM3 0x01030000
	124	#define CFG_MICRON_EN_DLL 0x01010000
8993e54b	125	#define CFG_MICRON_RFSH 0x01080000
37e3c62f	126	#define CFG_MICRON_INIT_DEV_OP 0x01000432
8993e54b	127	#define CFG_MICRON_OCD_DEFAULT 0x01010780
8993e54b RJ	128
	129	/* DDR Priority Manager Configuration */
	130	#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
	131	#define CFG_MDDRCGRP_PM_CFG2 0x00000055
	132	#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
	133	#define CFG_MDDRCGRP_LUT0_MU 0x11111117
	134	#define CFG_MDDRCGRP_LUT0_ML 0x7777777A
	135	#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
	136	#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
	137	#define CFG_MDDRCGRP_LUT2_MU 0x44444444
	138	#define CFG_MDDRCGRP_LUT2_ML 0x44444444
	139	#define CFG_MDDRCGRP_LUT3_MU 0x55555555
	140	#define CFG_MDDRCGRP_LUT3_ML 0x55555558
	141	#define CFG_MDDRCGRP_LUT4_MU 0x11111111
	142	#define CFG_MDDRCGRP_LUT4_ML 0x1111117C
	143	#define CFG_MDDRCGRP_LUT0_AU 0x33333377
	144	#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
	145	#define CFG_MDDRCGRP_LUT1_AU 0x11111111
	146	#define CFG_MDDRCGRP_LUT1_AL 0x11111111
	147	#define CFG_MDDRCGRP_LUT2_AU 0x11111111
	148	#define CFG_MDDRCGRP_LUT2_AL 0x11111111
	149	#define CFG_MDDRCGRP_LUT3_AU 0x11111111
	150	#define CFG_MDDRCGRP_LUT3_AL 0x11111111
	151	#define CFG_MDDRCGRP_LUT4_AU 0x11111111
	152	#define CFG_MDDRCGRP_LUT4_AL 0x11111111
	153
	154	/*
	155	* NOR FLASH on the Local Bus
	156	*/
	157	#define CFG_FLASH_CFI /* use the Common Flash Interface */
	158	#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
	159	#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
	160	#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
	161	#define CFG_FLASH_USE_BUFFER_WRITE
	162
	163	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	164	#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
	165	#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
	166
	167	#undef CFG_FLASH_CHECKSUM
	168
	169	/*
	170	* CPLD registers area is really only 32 bytes in size, but the smallest possible LP
	171	* window is 64KB
	172	*/
	173	#define CFG_CPLD_BASE 0x82000000
	174	#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
	175
	176	#define CFG_SRAM_BASE 0x30000000
	177	#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
	178
	179	#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
	180	#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
	181
	182	/* Use SRAM for initial stack */
	183	#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
	184	#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
	185
	186	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	187	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	188	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	189
	190	#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
	191	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
192	#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
193
194	/*
195	* Serial Port
196	*/
197	#define CONFIG_CONS_INDEX 1
198	#undef CONFIG_SERIAL_SOFTWARE_FIFO
199
200	/*
201	* Serial console configuration
202	*/
203	#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
204	#if CONFIG_PSC_CONSOLE != 3
205	#error CONFIG_PSC_CONSOLE must be 3
206	#endif
207	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
208	#define CFG_BAUDRATE_TABLE \
209	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
210
211	#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
212	#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
213	#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
214	#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
215
216	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
217	/* Use the HUSH parser */
218	#define CFG_HUSH_PARSER
219	#ifdef CFG_HUSH_PARSER
220	#define CFG_PROMPT_HUSH_PS2 "> "
221	#endif
222
5f91db7f JR	223	/*
	224	* PCI
	225	*/
	226	#ifdef CONFIG_PCI
	227
	228	/*
	229	* General PCI
	230	*/
	231	#define CFG_PCI_MEM_BASE 0xA0000000
	232	#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
	233	#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
	234	#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
	235	#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
	236	#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
	237	#define CFG_PCI_IO_BASE 0x00000000
	238	#define CFG_PCI_IO_PHYS 0x84000000
	239	#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */
	240
	241
	242	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	243
	244	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	245
	246	#endif
	247
8993e54b RJ	248	/* I2C */
	249	#define CONFIG_HARD_I2C /* I2C with hardware support */
	250	#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
	251	#define CONFIG_I2C_MULTI_BUS
	252	#define CONFIG_I2C_CMD_TREE
	253	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
	254	#define CFG_I2C_SLAVE 0x7F
	255	#if 0
cf5933ba	256	#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
8993e54b RJ	257	#endif
8993e54b RJ	258
80020120 GB	259	/*
	260	* EEPROM configuration
	261	*/
	262	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
	263	#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
de74b9ee	264	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
80020120 GB	265	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
80020120 GB	266
8993e54b RJ	267	/*
	268	* Ethernet configuration
	269	*/
	270	#define CONFIG_MPC512x_FEC 1
	271	#define CONFIG_NET_MULTI
	272	#define CONFIG_PHY_ADDR 0x1
	273	#define CONFIG_MII 1 /* MII PHY management */
8993e54b RJ	274
	275	#if 0
	276	/*
	277	* Configure on-board RTC
	278	*/
	279	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
	280	#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	281	#endif
	282
	283	/*
	284	* Environment
	285	*/
	286	#define CFG_ENV_IS_IN_FLASH 1
	287	/* This has to be a multiple of the Flash sector size */
	288	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	289	#define CFG_ENV_SIZE 0x2000
	290	#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
	291
	292	/* Address and size of Redundant Environment Sector */
	293	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
	294	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	295
	296	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	297	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	298
e27f3a6e WD	299	#include <config_cmd_default.h>
	300
	301	#define CONFIG_CMD_ASKENV
	302	#define CONFIG_CMD_DHCP
	303	#define CONFIG_CMD_I2C
	304	#define CONFIG_CMD_MII
	305	#define CONFIG_CMD_NFS
	306	#define CONFIG_CMD_PING
	307	#define CONFIG_CMD_REGINFO
80020120	308	#define CONFIG_CMD_EEPROM
e27f3a6e	309
8993e54b	310	#if defined(CONFIG_PCI)
e27f3a6e	311	#define CONFIG_CMD_PCI
8993e54b RJ	312	#endif
8993e54b RJ	313
8993e54b RJ	314	/*
	315	* Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
	316	* For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
	317	* to 0xFFFF, watchdog timeouts after about 64s. For details refer
	318	* to chapter 36 of the MPC5121e Reference Manual.
	319	*/
66ffb188	320	/* #define CONFIG_WATCHDOG / / enable watchdog */
8993e54b RJ	321	#define CFG_WATCHDOG_VALUE 0xFFFF
	322
	323	/*
	324	* Miscellaneous configurable options
	325	*/
	326	#define CFG_LONGHELP /* undef to save memory */
	327	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	328	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	329
e27f3a6e	330	#ifdef CONFIG_CMD_KGDB
66ffb188	331	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
8993e54b	332	#else
66ffb188	333	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
8993e54b RJ	334	#endif
	335
	336
	337	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
	338	#define CFG_MAXARGS 16 /* max number of command args */
	339	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	340	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	341
	342	/*
	343	* For booting Linux, the board info and command line data
	344	* have to be in the first 8 MB of memory, since this is
	345	* the maximum mapped by the Linux kernel during initialization.
	346	*/
	347	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
	348
	349	/* Cache Configuration */
	350	#define CFG_DCACHE_SIZE 32768
	351	#define CFG_CACHELINE_SIZE 32
e27f3a6e	352	#ifdef CONFIG_CMD_KGDB
8993e54b RJ	353	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
	354	#endif
	355
	356	#define CFG_HID0_INIT 0x000000000
	357	#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
	358	#define CFG_HID2 HID2_HBE
	359
	360	/*
	361	* Internal Definitions
	362	*
	363	* Boot Flags
	364	*/
66ffb188 WD	365	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
66ffb188 WD	366	#define BOOTFLAG_WARM 0x02 /* Software reboot */
8993e54b	367
e27f3a6e	368	#ifdef CONFIG_CMD_KGDB
8993e54b RJ	369	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
	370	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	371	#endif
	372
	373	/*
	374	* Environment Configuration
	375	*/
66ffb188	376	#define CONFIG_TIMESTAMP
8993e54b RJ	377
8993e54b RJ	378	#define CONFIG_HOSTNAME ads5121
8d103071	379	#define CONFIG_BOOTFILE ads5121/uImage
5b0b2b6f	380	#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
8993e54b	381
8d103071	382	#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
8993e54b	383
e27f3a6e	384	#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
8993e54b RJ	385	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	386
	387	#define CONFIG_BAUDRATE 115200
	388
	389	#define CONFIG_PREBOOT "echo;" \
5b0b2b6f	390	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
8993e54b RJ	391	"echo"
	392
	393	#define CONFIG_EXTRA_ENV_SETTINGS \
8d103071	394	"u-boot_addr_r=200000\0" \
5b0b2b6f	395	"kernel_addr_r=300000\0" \
8d103071 WD	396	"fdt_addr_r=400000\0" \
	397	"ramdisk_addr_r=500000\0" \
	398	"u-boot_addr=FFF00000\0" \
5b0b2b6f	399	"kernel_addr=FC040000\0" \
8d103071 WD	400	"fdt_addr=FC2C0000\0" \
	401	"ramdisk_addr=FC300000\0" \
	402	"ramdiskfile=ads5121/uRamdisk\0" \
	403	"fdtfile=ads5121/ads5121.dtb\0" \
	404	"u-boot=ads5121/u-boot.bin\0" \
8993e54b	405	"netdev=eth0\0" \
8d103071	406	"consdev=ttyPSC0\0" \
8993e54b RJ	407	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	408	"nfsroot=${serverip}:${rootpath}\0" \
	409	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	410	"addip=setenv bootargs ${bootargs} " \
	411	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	412	":${hostname}:${netdev}:off panic=1\0" \
8d103071 WD	413	"addtty=setenv bootargs ${bootargs} " \
8d103071 WD	414	"console=${consdev},${baudrate}\0" \
8993e54b	415	"flash_nfs=run nfsargs addip addtty;" \
5b0b2b6f	416	"bootm ${kernel_addr} - ${fdt_addr}\0" \
8993e54b	417	"flash_self=run ramargs addip addtty;" \
8d103071 WD	418	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	419	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	420	"tftp ${fdt_addr_r} ${fdtfile};" \
	421	"run nfsargs addip addtty;" \
	422	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	423	"net_self=tftp ${kernel_addr_r} ${bootfile};" \
	424	"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
5b0b2b6f	425	"tftp ${fdt_addr_r} ${fdtfile};" \
8d103071	426	"run ramargs addip addtty;" \
5b0b2b6f WD	427	"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
5b0b2b6f WD	428	"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
8d103071 WD	429	"update=protect off ${u-boot_addr} +${filesize};" \
	430	"era ${u-boot_addr} +${filesize};" \
	431	"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
	432	"upd=run load update\0" \
8993e54b RJ	433	""
8993e54b RJ	434
8993e54b RJ	435	#define CONFIG_BOOTCOMMAND "run flash_self"
8993e54b RJ	436
281ff9a4 GB	437	#define CONFIG_OF_LIBFDT 1
	438	#define CONFIG_OF_BOARD_SETUP 1
	439
	440	#define OF_CPU "PowerPC,5121@0"
ac915283 JR	441	#define OF_SOC "soc@80000000"
ac915283 JR	442	#define OF_SOC_OLD "soc5121@80000000"
281ff9a4	443	#define OF_TBCLK (bd->bi_busfreq / 4)
ac915283	444	#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
281ff9a4	445
8993e54b	446	#endif /* __CONFIG_H */