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915162da S |
1 | /* |
2 | * am3517_crane.h - Default configuration for AM3517 CraneBoard. | |
3 | * | |
4 | * Author: Srinath.R <srinath@mistralsolutions.com> | |
5 | * | |
6 | * Based on include/configs/am3517evm.h | |
7 | * | |
8 | * Copyright (C) 2011 Mistral Solutions pvt Ltd | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
915162da S |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
915162da S |
19 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ |
20 | ||
21 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 22 | #include <asm/arch/omap.h> |
915162da | 23 | |
915162da S |
24 | /* Clock Defines */ |
25 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
26 | #define V_SCLK (V_OSCK >> 1) | |
27 | ||
915162da S |
28 | #define CONFIG_MISC_INIT_R |
29 | ||
30 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
31 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
32 | #define CONFIG_INITRD_TAG 1 | |
33 | #define CONFIG_REVISION_TAG 1 | |
34 | ||
35 | /* | |
36 | * Size of malloc() pool | |
37 | */ | |
38 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
39 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
40 | /* initial data */ | |
41 | /* | |
42 | * DDR related | |
43 | */ | |
915162da S |
44 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) |
45 | ||
46 | /* | |
47 | * Hardware drivers | |
48 | */ | |
49 | ||
50 | /* | |
51 | * NS16550 Configuration | |
52 | */ | |
53 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
54 | ||
915162da S |
55 | #define CONFIG_SYS_NS16550_SERIAL |
56 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
57 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
58 | ||
59 | /* | |
60 | * select serial console configuration | |
61 | */ | |
62 | #define CONFIG_CONS_INDEX 3 | |
63 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
64 | #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ | |
65 | ||
66 | /* allow to overwrite serial and ethaddr */ | |
67 | #define CONFIG_ENV_OVERWRITE | |
915162da S |
68 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
69 | 115200} | |
915162da S |
70 | |
71 | /* | |
72 | * USB configuration | |
95de1e2f PK |
73 | * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard |
74 | * Enable CONFIG_USB_MUSB_UDC for Device functionalities. | |
915162da S |
75 | */ |
76 | #define CONFIG_USB_AM35X 1 | |
95de1e2f | 77 | #define CONFIG_USB_MUSB_HCD 1 |
915162da S |
78 | |
79 | #ifdef CONFIG_USB_AM35X | |
80 | ||
95de1e2f | 81 | #ifdef CONFIG_USB_MUSB_HCD |
915162da | 82 | |
915162da | 83 | #ifdef CONFIG_USB_KEYBOARD |
915162da S |
84 | #define CONFIG_PREBOOT "usb start" |
85 | #endif /* CONFIG_USB_KEYBOARD */ | |
86 | ||
95de1e2f | 87 | #endif /* CONFIG_USB_MUSB_HCD */ |
915162da | 88 | |
95de1e2f | 89 | #ifdef CONFIG_USB_MUSB_UDC |
915162da S |
90 | /* USB device configuration */ |
91 | #define CONFIG_USB_DEVICE 1 | |
92 | #define CONFIG_USB_TTY 1 | |
915162da S |
93 | /* Change these to suit your needs */ |
94 | #define CONFIG_USBD_VENDORID 0x0451 | |
95 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
96 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
97 | #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" | |
95de1e2f | 98 | #endif /* CONFIG_USB_MUSB_UDC */ |
915162da S |
99 | |
100 | #endif /* CONFIG_USB_AM35X */ | |
101 | ||
6789e84e HS |
102 | #define CONFIG_SYS_I2C |
103 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
104 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
915162da | 105 | |
915162da S |
106 | /* |
107 | * Board NAND Info. | |
108 | */ | |
109 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
110 | /* to access nand */ | |
111 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
112 | /* to access */ | |
113 | /* nand at CS0 */ | |
114 | ||
115 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
116 | /* NAND devices */ | |
915162da S |
117 | |
118 | #define CONFIG_JFFS2_NAND | |
119 | /* nand device jffs2 lives on */ | |
120 | #define CONFIG_JFFS2_DEV "nand0" | |
121 | /* start of jffs2 partition */ | |
122 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
123 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ | |
124 | ||
125 | /* Environment information */ | |
915162da | 126 | |
b3f44c21 | 127 | #define CONFIG_BOOTFILE "uImage" |
915162da S |
128 | |
129 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
130 | "loadaddr=0x82000000\0" \ | |
131 | "console=ttyS2,115200n8\0" \ | |
a5a8821c | 132 | "mmcdev=0\0" \ |
915162da S |
133 | "mmcargs=setenv bootargs console=${console} " \ |
134 | "root=/dev/mmcblk0p2 rw " \ | |
135 | "rootfstype=ext3 rootwait\0" \ | |
136 | "nandargs=setenv bootargs console=${console} " \ | |
137 | "root=/dev/mtdblock4 rw " \ | |
138 | "rootfstype=jffs2\0" \ | |
a5a8821c | 139 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
915162da S |
140 | "bootscript=echo Running bootscript from mmc ...; " \ |
141 | "source ${loadaddr}\0" \ | |
a5a8821c | 142 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
915162da S |
143 | "mmcboot=echo Booting from mmc ...; " \ |
144 | "run mmcargs; " \ | |
145 | "bootm ${loadaddr}\0" \ | |
146 | "nandboot=echo Booting from nand ...; " \ | |
147 | "run nandargs; " \ | |
148 | "nand read ${loadaddr} 280000 400000; " \ | |
149 | "bootm ${loadaddr}\0" \ | |
150 | ||
151 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 152 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
915162da S |
153 | "if run loadbootscript; then " \ |
154 | "run bootscript; " \ | |
155 | "else " \ | |
156 | "if run loaduimage; then " \ | |
157 | "run mmcboot; " \ | |
158 | "else run nandboot; " \ | |
159 | "fi; " \ | |
160 | "fi; " \ | |
161 | "else run nandboot; fi" | |
162 | ||
163 | #define CONFIG_AUTO_COMPLETE 1 | |
164 | /* | |
165 | * Miscellaneous configurable options | |
166 | */ | |
915162da | 167 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
915162da | 168 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
915162da S |
169 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ |
170 | /* args */ | |
915162da S |
171 | /* memtest works on */ |
172 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
173 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
174 | 0x01F00000) /* 31MB */ | |
175 | ||
176 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
177 | /* address */ | |
178 | ||
179 | /* | |
180 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
181 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
182 | * This rate is divided by a local divisor. | |
183 | */ | |
184 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
185 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
915162da | 186 | |
915162da S |
187 | /*----------------------------------------------------------------------- |
188 | * Physical Memory Map | |
189 | */ | |
190 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
191 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
915162da S |
192 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
193 | ||
915162da S |
194 | /*----------------------------------------------------------------------- |
195 | * FLASH and environment organization | |
196 | */ | |
197 | ||
198 | /* **** PISMO SUPPORT *** */ | |
915162da S |
199 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ |
200 | /* on one chip */ | |
201 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ | |
202 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ | |
203 | ||
222a3113 | 204 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
915162da S |
205 | |
206 | /* Monitor at start of flash */ | |
207 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
208 | ||
209 | #define CONFIG_NAND_OMAP_GPMC | |
915162da S |
210 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
211 | ||
6cbec7b3 LC |
212 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ |
213 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
214 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
915162da S |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * CFI FLASH driver setup | |
218 | */ | |
219 | /* timeout values are in ticks */ | |
220 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) | |
221 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) | |
222 | ||
223 | /* Flash banks JFFS2 should use */ | |
224 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
225 | CONFIG_SYS_MAX_NAND_DEVICE) | |
226 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
227 | /* use flash_info[2] */ | |
228 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
229 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
230 | ||
915162da S |
231 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
232 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
233 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
234 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
235 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
236 | GENERATED_GBL_DATA_SIZE) | |
d067cc46 TR |
237 | |
238 | /* Defines for SPL */ | |
47f7bcae | 239 | #define CONFIG_SPL_FRAMEWORK |
d067cc46 TR |
240 | #define CONFIG_SPL_NAND_SIMPLE |
241 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
242 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
243 | CONFIG_SPL_TEXT_BASE) | |
d067cc46 TR |
244 | |
245 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
246 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
247 | ||
e2ccdf89 | 248 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 249 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
d067cc46 | 250 | |
6f2f01b9 SW |
251 | #define CONFIG_SPL_NAND_BASE |
252 | #define CONFIG_SPL_NAND_DRIVERS | |
253 | #define CONFIG_SPL_NAND_ECC | |
d067cc46 TR |
254 | |
255 | /* NAND boot config */ | |
55f1b39f | 256 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
d067cc46 TR |
257 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
258 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
259 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
260 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
261 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
262 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
263 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
264 | 10, 11, 12, 13} | |
265 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
266 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 267 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
d067cc46 TR |
268 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
269 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
270 | ||
271 | /* | |
272 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
273 | * 64 bytes before this address should be set aside for u-boot.img's | |
274 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
275 | * other needs. | |
276 | */ | |
277 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
278 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
279 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
280 | ||
915162da | 281 | #endif /* __CONFIG_H */ |