[people/ms/u-boot.git] / include / configs / am3517_crane.h

/*
 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
 *
 * Author: Srinath.R <srinath@mistralsolutions.com>
 *
 * Based on include/configs/am3517evm.h
 *
 * Copyright (C) 2011 Mistral Solutions pvt Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517CRANE	1	/* working with CRANEBOARD */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
						/* initial data */
/*
 * DDR related
 */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on CRANEBOARD */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/*
 * USB configuration
 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
 * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
 */
#define CONFIG_USB_AM35X		1
#define CONFIG_USB_MUSB_HCD			1

#ifdef CONFIG_USB_AM35X

#ifdef CONFIG_USB_MUSB_HCD

#define CONGIG_CMD_STORAGE

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_USB_MUSB_HCD */

#ifdef CONFIG_USB_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
#endif /* CONFIG_USB_MUSB_UDC */

#endif /* CONFIG_USB_AM35X */

/* commands to include */
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_NAND		/* NAND support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */

#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS2,115200n8\0" \
	"mmcdev=0\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		NAND_BASE

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#endif /* __CONFIG_H */
Commit	Line	Data
915162da S	1	/*
	2	* am3517_crane.h - Default configuration for AM3517 CraneBoard.
	3	*
	4	* Author: Srinath.R <srinath@mistralsolutions.com>
	5	*
	6	* Based on include/configs/am3517evm.h
	7	*
	8	* Copyright (C) 2011 Mistral Solutions pvt Ltd
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
915162da S	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
915162da	19	#define CONFIG_OMAP 1 /* in a TI OMAP core */
915162da	20	#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
806d2792	21	#define CONFIG_OMAP_COMMON
c6f90e14 NM	22	/* Common ARM Erratas */
	23	#define CONFIG_ARM_ERRATA_454179
	24	#define CONFIG_ARM_ERRATA_430973
	25	#define CONFIG_ARM_ERRATA_621766
915162da S	26
	27	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	28
	29	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	30	#include <asm/arch/omap.h>
915162da	31
915162da S	32	/* Clock Defines */
	33	#define V_OSCK 26000000 /* Clock output from T2 */
	34	#define V_SCLK (V_OSCK >> 1)
	35
915162da S	36	#define CONFIG_MISC_INIT_R
	37
	38	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	39	#define CONFIG_SETUP_MEMORY_TAGS 1
	40	#define CONFIG_INITRD_TAG 1
	41	#define CONFIG_REVISION_TAG 1
	42
	43	/*
	44	* Size of malloc() pool
	45	*/
	46	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	47	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	48	/* initial data */
	49	/*
	50	* DDR related
	51	*/
915162da S	52	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	53
	54	/*
	55	* Hardware drivers
	56	*/
	57
	58	/*
	59	* NS16550 Configuration
	60	*/
	61	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	62
915162da S	63	#define CONFIG_SYS_NS16550_SERIAL
	64	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	65	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	66
	67	/*
	68	* select serial console configuration
	69	*/
	70	#define CONFIG_CONS_INDEX 3
	71	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	72	#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
	73
	74	/* allow to overwrite serial and ethaddr */
	75	#define CONFIG_ENV_OVERWRITE
	76	#define CONFIG_BAUDRATE 115200
	77	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	78	115200}
a5a8821c	79	#define CONFIG_GENERIC_MMC 1
915162da	80	#define CONFIG_MMC 1
a5a8821c	81	#define CONFIG_OMAP_HSMMC 1
915162da S	82	#define CONFIG_DOS_PARTITION 1
	83
	84	/*
	85	* USB configuration
95de1e2f PK	86	* Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
95de1e2f PK	87	* Enable CONFIG_USB_MUSB_UDC for Device functionalities.
915162da S	88	*/
915162da S	89	#define CONFIG_USB_AM35X 1
95de1e2f	90	#define CONFIG_USB_MUSB_HCD 1
915162da S	91
	92	#ifdef CONFIG_USB_AM35X
	93
95de1e2f	94	#ifdef CONFIG_USB_MUSB_HCD
915162da	95
915162da	96	#define CONGIG_CMD_STORAGE
915162da S	97
	98	#ifdef CONFIG_USB_KEYBOARD
	99	#define CONFIG_SYS_USB_EVENT_POLL
	100	#define CONFIG_PREBOOT "usb start"
	101	#endif /* CONFIG_USB_KEYBOARD */
	102
95de1e2f	103	#endif /* CONFIG_USB_MUSB_HCD */
915162da	104
95de1e2f	105	#ifdef CONFIG_USB_MUSB_UDC
915162da S	106	/* USB device configuration */
	107	#define CONFIG_USB_DEVICE 1
	108	#define CONFIG_USB_TTY 1
915162da S	109	/* Change these to suit your needs */
	110	#define CONFIG_USBD_VENDORID 0x0451
	111	#define CONFIG_USBD_PRODUCTID 0x5678
	112	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	113	#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
95de1e2f	114	#endif /* CONFIG_USB_MUSB_UDC */
915162da S	115
	116	#endif /* CONFIG_USB_AM35X */
	117
	118	/* commands to include */
915162da S	119	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
915162da S	120
915162da	121	#define CONFIG_CMD_NAND /* NAND support */
915162da	122
915162da	123	#define CONFIG_SYS_NO_FLASH
6789e84e HS	124	#define CONFIG_SYS_I2C
	125	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	126	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	127	#define CONFIG_SYS_I2C_OMAP34XX
915162da	128
915162da S	129	/*
	130	* Board NAND Info.
	131	*/
	132	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	133	/* to access nand */
	134	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	135	/* to access */
	136	/* nand at CS0 */
	137
	138	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	139	/* NAND devices */
915162da S	140
	141	#define CONFIG_JFFS2_NAND
	142	/* nand device jffs2 lives on */
	143	#define CONFIG_JFFS2_DEV "nand0"
	144	/* start of jffs2 partition */
	145	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	146	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	147
	148	/* Environment information */
915162da	149
b3f44c21	150	#define CONFIG_BOOTFILE "uImage"
915162da S	151
	152	#define CONFIG_EXTRA_ENV_SETTINGS \
	153	"loadaddr=0x82000000\0" \
	154	"console=ttyS2,115200n8\0" \
a5a8821c	155	"mmcdev=0\0" \
915162da S	156	"mmcargs=setenv bootargs console=${console} " \
	157	"root=/dev/mmcblk0p2 rw " \
	158	"rootfstype=ext3 rootwait\0" \
	159	"nandargs=setenv bootargs console=${console} " \
	160	"root=/dev/mtdblock4 rw " \
	161	"rootfstype=jffs2\0" \
a5a8821c	162	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
915162da S	163	"bootscript=echo Running bootscript from mmc ...; " \
915162da S	164	"source ${loadaddr}\0" \
a5a8821c	165	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
915162da S	166	"mmcboot=echo Booting from mmc ...; " \
	167	"run mmcargs; " \
	168	"bootm ${loadaddr}\0" \
	169	"nandboot=echo Booting from nand ...; " \
	170	"run nandargs; " \
	171	"nand read ${loadaddr} 280000 400000; " \
	172	"bootm ${loadaddr}\0" \
	173
	174	#define CONFIG_BOOTCOMMAND \
66968110	175	"mmc dev ${mmcdev}; if mmc rescan; then " \
915162da S	176	"if run loadbootscript; then " \
	177	"run bootscript; " \
	178	"else " \
	179	"if run loaduimage; then " \
	180	"run mmcboot; " \
	181	"else run nandboot; " \
	182	"fi; " \
	183	"fi; " \
	184	"else run nandboot; fi"
	185
	186	#define CONFIG_AUTO_COMPLETE 1
	187	/*
	188	* Miscellaneous configurable options
	189	*/
915162da	190	#define CONFIG_SYS_LONGHELP /* undef to save memory */
915162da S	191	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	192	/* Print Buffer Size */
	193	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	194	sizeof(CONFIG_SYS_PROMPT) + 16)
	195	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	196	/* args */
	197	/* Boot Argument Buffer Size */
	198	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	199	/* memtest works on */
	200	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	201	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	202	0x01F00000) /* 31MB */
	203
	204	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	205	/* address */
	206
	207	/*
	208	* AM3517 has 12 GP timers, they can be driven by the system clock
	209	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	210	* This rate is divided by a local divisor.
	211	*/
	212	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	213	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
915162da	214
915162da S	215	/*-----------------------------------------------------------------------
	216	* Physical Memory Map
	217	*/
	218	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	219	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
915162da S	220	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
915162da S	221
915162da S	222	/*-----------------------------------------------------------------------
	223	* FLASH and environment organization
	224	*/
	225
	226	/* ** PISMO SUPPORT * */
915162da S	227	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	228	/* on one chip */
	229	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	230	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	231
222a3113	232	#define CONFIG_SYS_FLASH_BASE NAND_BASE
915162da S	233
	234	/* Monitor at start of flash */
	235	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	236
	237	#define CONFIG_NAND_OMAP_GPMC
915162da S	238	#define CONFIG_ENV_IS_IN_NAND 1
	239	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	240
6cbec7b3 LC	241	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
	242	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	243	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
915162da S	244
	245	/*-----------------------------------------------------------------------
	246	* CFI FLASH driver setup
	247	*/
	248	/* timeout values are in ticks */
	249	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	250	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	251
	252	/* Flash banks JFFS2 should use */
	253	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	254	CONFIG_SYS_MAX_NAND_DEVICE)
	255	#define CONFIG_SYS_JFFS2_MEM_NAND
	256	/* use flash_info[2] */
	257	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	258	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	259
915162da S	260	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	261	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	262	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	263	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	264	CONFIG_SYS_INIT_RAM_SIZE - \
	265	GENERATED_GBL_DATA_SIZE)
d067cc46 TR	266
d067cc46 TR	267	/* Defines for SPL */
47f7bcae	268	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	269	#define CONFIG_SPL_BOARD_INIT
d067cc46 TR	270	#define CONFIG_SPL_NAND_SIMPLE
d067cc46 TR	271	#define CONFIG_SPL_TEXT_BASE 0x40200800
fa2f81b0 TR	272	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	273	CONFIG_SPL_TEXT_BASE)
d067cc46 TR	274
	275	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	276	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	277
	278	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	279	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
e2ccdf89	280	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	281	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
d067cc46	282
6f2f01b9 SW	283	#define CONFIG_SPL_NAND_BASE
	284	#define CONFIG_SPL_NAND_DRIVERS
	285	#define CONFIG_SPL_NAND_ECC
d067cc46 TR	286	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	287
	288	/* NAND boot config */
55f1b39f	289	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
d067cc46 TR	290	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	291	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	292	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	293	#define CONFIG_SYS_NAND_OOBSIZE 64
	294	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	295	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	296	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	297	10, 11, 12, 13}
	298	#define CONFIG_SYS_NAND_ECCSIZE 512
	299	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	300	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
d067cc46 TR	301	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	302	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	303
	304	/*
	305	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	306	* 64 bytes before this address should be set aside for u-boot.img's
	307	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	308	* other needs.
	309	*/
	310	#define CONFIG_SYS_TEXT_BASE 0x80100000
	311	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	312	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	313
915162da	314	#endif /* __CONFIG_H */