[people/ms/u-boot.git] / include / configs / am3517_evm.h

/*
 * am3517_evm.h - Default configuration for AM3517 EVM board.
 *
 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
 *
 * Based on omap3_evm_config.h
 *
 * Copyright (C) 2010 Texas Instruments Incorporated
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */

#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON

#define CONFIG_SYS_NO_FLASH

#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */

/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Display CPU and Board information */
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(16 << 20)

/* Hardware drivers */

/* OMAP GPIO configuration */
#define CONFIG_OMAP_GPIO

/* NS16550 Configuration */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/* select serial console configuration */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/*
 * USB configuration
 * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
 * Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
 */
#define CONFIG_USB_MUSB_AM35X
#define CONFIG_USB_MUSB_PIO_ONLY

#ifdef CONFIG_USB_MUSB_AM35X

#ifdef CONFIG_USB_MUSB_HOST

#define CONGIG_CMD_STORAGE

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_USB_MUSB_HOST */

#ifdef CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#endif /* CONFIG_USB_MUSB_GADGET */

#endif /* CONFIG_USB_MUSB_AM35X */

/* commands to include */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PART
#define CONFIG_CMD_MTDPARTS

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/* Ethernet */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT		10

/* Board NAND Info. */
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_BCH
#define CONFIG_CMD_UBIFS		/* Read-only UBI volume operations */
#define CONFIG_RBTREE			/* required by CONFIG_CMD_UBI */
#define CONFIG_LZO			/* required by CONFIG_CMD_UBIFS */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
					 11, 12, 13, 14, 16, 17, 18, 19, 20, \
					 21, 22, 23, 24, 25, 26, 27, 28, 30, \
					 31, 32, 33, 34, 35, 36, 37, 38, 39, \
					 40, 41, 42, 44, 45, 46, 47, 48, 49, \
					 50, 51, 52, 53, 54, 55, 56 }

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	13
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_MAX_ECCPOS	56
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_MTD_PARTITIONS		/* required for UBI partition support */
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
/* NAND block size is 128 KiB.  Synchronize these values with
 * corresponding Device Tree entries in Linux:
 *  MLO(SPL)             4 * NAND_BLOCK_SIZE = 512 KiB  @ 0x000000
 *  U-Boot              15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000
 *  U-Boot environment   2 * NAND_BLOCK_SIZE = 256 KiB  @ 0x260000
 *  Kernel              64 * NAND_BLOCK_SIZE = 8 MiB    @ 0x2A0000
 *  DTB                  4 * NAND_BLOCK_SIZE = 512 KiB  @ 0xAA0000
 *  RootFS              Remaining Flash Space           @ 0xB20000
 */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:"	\
	"512k(MLO),"					\
	"1920k(u-boot),"				\
	"256k(u-boot-env),"				\
	"8m(kernel),"					\
	"512k(dtb),"					\
	"-(rootfs)"
#else
#define MTDIDS_DEFAULT
#define MTDPARTS_DEFAULT
#endif /* CONFIG_NAND */

/* Environment information */

#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"fdtfile=am3517-evm.dtb\0" \
	"fdtaddr=0x82C00000\0" \
	"vram=16M\0" \
	"bootenv=uEnv.txt\0" \
	"cmdline=\0" \
	"optargs=\0" \
	"mtdids=" MTDIDS_DEFAULT "\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"mmcdev=0\0" \
	"mmcpart=1\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext4 rootwait fixrtc\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"${mtdparts} " \
		"${optargs} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype} " \
		"${cmdline}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${mtdparts} " \
		"${optargs} " \
		"root=ubi0:rootfs rw ubi.mtd=rootfs " \
		"rootfstype=ubifs rootwait " \
		"${cmdline}\0" \
	"loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t ${loadaddr} ${filesize}\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootz ${loadaddr} - ${fdtaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 800000; " \
		"nand read ${fdtaddr} aa0000 80000; " \
		"bootm ${loadaddr} - ${fdtaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"echo SD/MMC found on device $mmcdev; " \
		"if run loadbootenv; then " \
			"run importbootenv; " \
		"fi; " \
		"echo Checking if uenvcmd is set ...; " \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...; " \
			"run uenvcmd; " \
		"fi; " \
		"echo Running default loadimage ...; " \
		"setenv bootfile zImage; " \
		"if run loadimage; then " \
			"run loadfdt; " \
			"run mmcboot; " \
		"fi; " \
	"else run nandboot; fi"

/* Miscellaneous configurable options */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_PARTITION_UUIDS

/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS		64

/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE		512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
					+ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/* Physical Memory Map */
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* FLASH and environment organization */

/* **** PISMO SUPPORT *** */
#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_SIZE			CONFIG_SYS_ENV_SECT_SIZE
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_IS_IN_NAND

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200000
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#endif /* __CONFIG_H */
Commit	Line	Data
ed01e45c VH	1	/*
	2	* am3517_evm.h - Default configuration for AM3517 EVM board.
	3	*
	4	* Author: Vaibhav Hiremath <hvaibhav@ti.com>
	5	*
	6	* Based on omap3_evm_config.h
	7	*
	8	* Copyright (C) 2010 Texas Instruments Incorporated
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
ed01e45c VH	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
3f53e619	16	/* High Level Configuration Options */
3709844f	17
3f53e619	18	#define CONFIG_OMAP
806d2792	19	#define CONFIG_OMAP_COMMON
3f53e619	20
3f53e619 DW	21	#define CONFIG_SYS_NO_FLASH
	22
	23	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	24
c6f90e14 NM	25	/* Common ARM Erratas */
	26	#define CONFIG_ARM_ERRATA_454179
	27	#define CONFIG_ARM_ERRATA_430973
	28	#define CONFIG_ARM_ERRATA_621766
ed01e45c	29
1a5038ca	30	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
ed01e45c	31
3f53e619 DW	32	/*
	33	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	34	* 64 bytes before this address should be set aside for u-boot.img's
	35	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	36	* other needs.
	37	*/
	38	#define CONFIG_SYS_TEXT_BASE 0x80100000
	39	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	40	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	41
ed01e45c	42	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	43	#include <asm/arch/omap.h>
ed01e45c	44
3f53e619	45	/* Display CPU and Board information */
3f53e619	46	#define CONFIG_DISPLAY_BOARDINFO
3f53e619 DW	47	#define CONFIG_MISC_INIT_R
	48	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	49	#define CONFIG_SETUP_MEMORY_TAGS
	50	#define CONFIG_INITRD_TAG
	51	#define CONFIG_REVISION_TAG
ed01e45c VH	52
	53	/* Clock Defines */
	54	#define V_OSCK 26000000 /* Clock output from T2 */
	55	#define V_SCLK (V_OSCK >> 1)
	56
3f53e619 DW	57	/* Size of malloc() pool */
3f53e619 DW	58	#define CONFIG_SYS_MALLOC_LEN (16 << 20)
ed01e45c	59
3f53e619	60	/* Hardware drivers */
ed01e45c	61
3f53e619	62	/* OMAP GPIO configuration */
6a1df373 YY	63	#define CONFIG_OMAP_GPIO
6a1df373 YY	64
3f53e619	65	/* NS16550 Configuration */
ed01e45c	66	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
ed01e45c VH	67	#define CONFIG_SYS_NS16550_SERIAL
	68	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	69	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	70
3f53e619	71	/* select serial console configuration */
ed01e45c VH	72	#define CONFIG_CONS_INDEX 3
	73	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	74	#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
	75
	76	/* allow to overwrite serial and ethaddr */
	77	#define CONFIG_ENV_OVERWRITE
	78	#define CONFIG_BAUDRATE 115200
	79	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	80	115200}
3f53e619 DW	81
	82	/* SD/MMC */
	83	#define CONFIG_MMC
	84	#define CONFIG_GENERIC_MMC
	85	#define CONFIG_OMAP_HSMMC
	86	#define CONFIG_DOS_PARTITION
ed01e45c	87
7dc27b05 AKG	88	/*
7dc27b05 AKG	89	* USB configuration
95de1e2f PK	90	* Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
95de1e2f PK	91	* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
7dc27b05	92	*/
88919ff7	93	#define CONFIG_USB_MUSB_AM35X
95de1e2f	94	#define CONFIG_USB_MUSB_PIO_ONLY
7dc27b05	95
88919ff7	96	#ifdef CONFIG_USB_MUSB_AM35X
7dc27b05	97
95de1e2f	98	#ifdef CONFIG_USB_MUSB_HOST
7dc27b05	99
7dc27b05	100	#define CONGIG_CMD_STORAGE
7dc27b05 AKG	101
	102	#ifdef CONFIG_USB_KEYBOARD
	103	#define CONFIG_SYS_USB_EVENT_POLL
	104	#define CONFIG_PREBOOT "usb start"
	105	#endif /* CONFIG_USB_KEYBOARD */
	106
95de1e2f	107	#endif /* CONFIG_USB_MUSB_HOST */
88919ff7	108
95de1e2f	109	#ifdef CONFIG_USB_MUSB_GADGET
88919ff7 IY	110	#define CONFIG_USB_ETHER
88919ff7 IY	111	#define CONFIG_USB_ETH_RNDIS
95de1e2f	112	#endif /* CONFIG_USB_MUSB_GADGET */
88919ff7 IY	113
88919ff7 IY	114	#endif /* CONFIG_USB_MUSB_AM35X */
7dc27b05	115
ed01e45c	116	/* commands to include */
3f53e619	117	#define CONFIG_CMD_NAND
3f53e619	118	#define CONFIG_CMD_PART
3f53e619	119	#define CONFIG_CMD_MTDPARTS
ed01e45c	120
3f53e619	121	/* I2C */
6789e84e HS	122	#define CONFIG_SYS_I2C
	123	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	124	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	125	#define CONFIG_SYS_I2C_OMAP34XX
ed01e45c	126
3f53e619	127	/* Ethernet */
18a02e80 TR	128	#define CONFIG_DRIVER_TI_EMAC
	129	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	130	#define CONFIG_MII
	131	#define CONFIG_BOOTP_DEFAULT
	132	#define CONFIG_BOOTP_DNS
	133	#define CONFIG_BOOTP_DNS2
	134	#define CONFIG_BOOTP_SEND_HOSTNAME
	135	#define CONFIG_NET_RETRY_COUNT 10
	136
3f53e619 DW	137	/* Board NAND Info. */
	138	#ifdef CONFIG_NAND
	139	#define CONFIG_NAND_OMAP_GPMC
	140	#define CONFIG_NAND_OMAP_GPMC_PREFETCH
	141	#define CONFIG_BCH
3f53e619 DW	142	#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
	143	#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
	144	#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
ed01e45c VH	145	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	146	/* to access nand */
	147	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	148	/* to access */
	149	/* nand at CS0 */
ed01e45c VH	150	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
ed01e45c VH	151	/* NAND devices */
3f53e619 DW	152	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
	153	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	154	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	155	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	156	#define CONFIG_SYS_NAND_OOBSIZE 64
	157	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	158	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	159	#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
	160	11, 12, 13, 14, 16, 17, 18, 19, 20, \
	161	21, 22, 23, 24, 25, 26, 27, 28, 30, \
	162	31, 32, 33, 34, 35, 36, 37, 38, 39, \
	163	40, 41, 42, 44, 45, 46, 47, 48, 49, \
	164	50, 51, 52, 53, 54, 55, 56 }
	165
	166	#define CONFIG_SYS_NAND_ECCSIZE 512
	167	#define CONFIG_SYS_NAND_ECCBYTES 13
	168	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	169	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	170	#define CONFIG_SYS_NAND_MAX_ECCPOS 56
	171	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	172	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	173	#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
	174	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	175	/* NAND block size is 128 KiB. Synchronize these values with
	176	* corresponding Device Tree entries in Linux:
	177	* MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000
	178	* U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000
	179	* U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000
	180	* Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000
	181	* DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000
	182	* RootFS Remaining Flash Space @ 0xB20000
	183	*/
	184	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	185	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
	186	"512k(MLO)," \
	187	"1920k(u-boot)," \
	188	"256k(u-boot-env)," \
	189	"8m(kernel)," \
	190	"512k(dtb)," \
	191	"-(rootfs)"
	192	#else
	193	#define MTDIDS_DEFAULT
	194	#define MTDPARTS_DEFAULT
	195	#endif /* CONFIG_NAND */
ed01e45c VH	196
ed01e45c VH	197	/* Environment information */
ed01e45c	198
b3f44c21	199	#define CONFIG_BOOTFILE "uImage"
ed01e45c VH	200
	201	#define CONFIG_EXTRA_ENV_SETTINGS \
	202	"loadaddr=0x82000000\0" \
49473ada	203	"console=ttyO2,115200n8\0" \
45776e36 DW	204	"fdtfile=am3517-evm.dtb\0" \
	205	"fdtaddr=0x82C00000\0" \
	206	"vram=16M\0" \
	207	"bootenv=uEnv.txt\0" \
	208	"cmdline=\0" \
	209	"optargs=\0" \
3f53e619 DW	210	"mtdids=" MTDIDS_DEFAULT "\0" \
3f53e619 DW	211	"mtdparts=" MTDPARTS_DEFAULT "\0" \
122e6e0a	212	"mmcdev=0\0" \
45776e36 DW	213	"mmcpart=1\0" \
	214	"mmcroot=/dev/mmcblk0p2 rw\0" \
	215	"mmcrootfstype=ext4 rootwait fixrtc\0" \
ed01e45c	216	"mmcargs=setenv bootargs console=${console} " \
3f53e619	217	"${mtdparts} " \
45776e36 DW	218	"${optargs} " \
	219	"root=${mmcroot} " \
	220	"rootfstype=${mmcrootfstype} " \
	221	"${cmdline}\0" \
ed01e45c	222	"nandargs=setenv bootargs console=${console} " \
3f53e619 DW	223	"${mtdparts} " \
	224	"${optargs} " \
	225	"root=ubi0:rootfs rw ubi.mtd=rootfs " \
	226	"rootfstype=ubifs rootwait " \
	227	"${cmdline}\0" \
45776e36 DW	228	"loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\
	229	"importbootenv=echo Importing environment from mmc ...; " \
	230	"env import -t ${loadaddr} ${filesize}\0" \
ed01e45c VH	231	"bootscript=echo Running bootscript from mmc ...; " \
ed01e45c VH	232	"source ${loadaddr}\0" \
45776e36 DW	233	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \
45776e36 DW	234	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \
ed01e45c VH	235	"mmcboot=echo Booting from mmc ...; " \
ed01e45c VH	236	"run mmcargs; " \
45776e36	237	"bootz ${loadaddr} - ${fdtaddr}\0" \
ed01e45c VH	238	"nandboot=echo Booting from nand ...; " \
ed01e45c VH	239	"run nandargs; " \
3f53e619 DW	240	"nand read ${loadaddr} 2a0000 800000; " \
	241	"nand read ${fdtaddr} aa0000 80000; " \
	242	"bootm ${loadaddr} - ${fdtaddr}\0" \
ed01e45c VH	243
ed01e45c VH	244	#define CONFIG_BOOTCOMMAND \
66968110	245	"mmc dev ${mmcdev}; if mmc rescan; then " \
45776e36 DW	246	"echo SD/MMC found on device $mmcdev; " \
	247	"if run loadbootenv; then " \
	248	"run importbootenv; " \
	249	"fi; " \
	250	"echo Checking if uenvcmd is set ...; " \
	251	"if test -n $uenvcmd; then " \
	252	"echo Running uenvcmd ...; " \
	253	"run uenvcmd; " \
	254	"fi; " \
	255	"echo Running default loadimage ...; " \
	256	"setenv bootfile zImage; " \
	257	"if run loadimage; then " \
	258	"run loadfdt; " \
	259	"run mmcboot; " \
ed01e45c VH	260	"fi; " \
	261	"else run nandboot; fi"
	262
3f53e619 DW	263	/* Miscellaneous configurable options */
	264	#define CONFIG_AUTO_COMPLETE
	265	#define CONFIG_CMDLINE_EDITING
3f53e619	266	#define CONFIG_SYS_LONGHELP
3f53e619 DW	267	#define CONFIG_PARTITION_UUIDS
	268
	269	/* We set the max number of command args high to avoid HUSH bugs. */
	270	#define CONFIG_SYS_MAXARGS 64
	271
	272	/* Console I/O Buffer Size */
	273	#define CONFIG_SYS_CBSIZE 512
ed01e45c	274	/* Print Buffer Size */
3f53e619 DW	275	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
3f53e619 DW	276	+ sizeof(CONFIG_SYS_PROMPT) + 16)
ed01e45c	277	/* Boot Argument Buffer Size */
3f53e619 DW	278	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
3f53e619 DW	279
ed01e45c VH	280	/* memtest works on */
	281	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	282	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	283	0x01F00000) /* 31MB */
	284
	285	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	286	/* address */
	287
	288	/*
	289	* AM3517 has 12 GP timers, they can be driven by the system clock
	290	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	291	* This rate is divided by a local divisor.
	292	*/
	293	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	294	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
ed01e45c	295
3f53e619 DW	296	/* Physical Memory Map */
	297	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	298	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	299	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	300	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	301	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	302	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	303	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	304	CONFIG_SYS_INIT_RAM_SIZE - \
	305	GENERATED_GBL_DATA_SIZE)
ed01e45c	306
3f53e619	307	/* FLASH and environment organization */
ed01e45c VH	308
ed01e45c VH	309	/* ** PISMO SUPPORT * */
ed01e45c VH	310	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	311	/* on one chip */
	312	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	313	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	314
3f53e619	315	#if defined(CONFIG_NAND)
222a3113	316	#define CONFIG_SYS_FLASH_BASE NAND_BASE
6cbec7b3	317	#endif
ed01e45c VH	318
	319	/* Monitor at start of flash */
	320	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	321
6cbec7b3	322	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
3f53e619 DW	323	#define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE
3f53e619 DW	324	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
6cbec7b3 LC	325	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
6cbec7b3 LC	326	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
3f53e619	327	#define CONFIG_ENV_IS_IN_NAND
5059a2a4 TR	328
5059a2a4 TR	329	/* Defines for SPL */
47f7bcae	330	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	331	#define CONFIG_SPL_BOARD_INIT
5059a2a4	332	#define CONFIG_SPL_NAND_SIMPLE
138daa7b	333	#define CONFIG_SPL_TEXT_BASE 0x40200000
fa2f81b0 TR	334	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	335	CONFIG_SPL_TEXT_BASE)
5059a2a4 TR	336
	337	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	338	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	339
	340	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	341	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
e2ccdf89	342	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
3f53e619	343	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
5059a2a4	344
6f2f01b9 SW	345	#define CONFIG_SPL_NAND_BASE
	346	#define CONFIG_SPL_NAND_DRIVERS
	347	#define CONFIG_SPL_NAND_ECC
5059a2a4 TR	348	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
5059a2a4 TR	349
ed01e45c	350	#endif /* __CONFIG_H */