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7254d92e HS |
1 | /* |
2 | * (C) Copyright 2015 | |
3 | * (C) Copyright 2014 | |
4 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
5 | * | |
6 | * Based on: | |
7 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
8 | * | |
9 | * Configuration settings for the Freescale i.MX6Q SabreSD board. | |
10 | * | |
11 | * SPDX-License-Identifier: GPL-2.0+ | |
12 | */ | |
13 | #ifndef __ARISTAINETOS_COMMON_CONFIG_H | |
14 | #define __ARISTAINETOS_COMMON_CONFIG_H | |
15 | ||
7254d92e | 16 | #include "mx6_common.h" |
7254d92e | 17 | |
7254d92e HS |
18 | #define CONFIG_MACH_TYPE 4501 |
19 | #define CONFIG_MMCROOT "/dev/mmcblk0p1" | |
7254d92e | 20 | |
7254d92e HS |
21 | /* Size of malloc() pool */ |
22 | #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) | |
23 | ||
7254d92e HS |
24 | #define CONFIG_MXC_UART |
25 | ||
7254d92e | 26 | /* MMC Configs */ |
7254d92e HS |
27 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
28 | ||
7254d92e HS |
29 | #define CONFIG_FEC_MXC |
30 | #define CONFIG_MII | |
31 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
32 | #define CONFIG_ETHPRIME "FEC" | |
33 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
34 | ||
7254d92e HS |
35 | #define CONFIG_PHY_MICREL |
36 | ||
7254d92e | 37 | #define CONFIG_SPI_FLASH_MTD |
7254d92e | 38 | #define CONFIG_MXC_SPI |
7254d92e HS |
39 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
40 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
41 | #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN | |
42 | ||
7254d92e HS |
43 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
44 | "script=u-boot.scr\0" \ | |
45 | "fit_file=/boot/system.itb\0" \ | |
46 | "loadaddr=0x12000000\0" \ | |
47 | "fit_addr_r=0x14000000\0" \ | |
48 | "uboot=/boot/u-boot.imx\0" \ | |
49 | "uboot_sz=d0000\0" \ | |
50 | "rescue_sys_addr=f0000\0" \ | |
51 | "rescue_sys_length=f10000\0" \ | |
52 | "panel=lb07wv8\0" \ | |
53 | "splashpos=m,m\0" \ | |
12ca05a3 | 54 | "console=" CONSOLE_DEV "\0" \ |
7254d92e HS |
55 | "fdt_high=0xffffffff\0" \ |
56 | "initrd_high=0xffffffff\0" \ | |
57 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
58 | "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ | |
59 | "default ${board_type}\0" \ | |
60 | "get_env=mw ${loadaddr} 0 0x20000;" \ | |
61 | "mmc rescan;" \ | |
62 | "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ | |
63 | "env import -t ${loadaddr}\0" \ | |
64 | "default_env=mw ${loadaddr} 0 0x20000;" \ | |
65 | "env export -t ${loadaddr} serial# ethaddr eth1addr " \ | |
66 | "board_type panel;" \ | |
67 | "env default -a;" \ | |
68 | "env import -t ${loadaddr}\0" \ | |
69 | "loadbootscript=" \ | |
70 | "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
71 | "bootscript=echo Running bootscript from mmc ...; " \ | |
72 | "source\0" \ | |
73 | "mmcpart=1\0" \ | |
74 | "mmcdev=0\0" \ | |
75 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | |
76 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
77 | "root=${mmcroot}\0" \ | |
78 | "mmcboot=echo Booting from mmc ...; " \ | |
79 | "run mmcargs addmtd addmisc set_fit_default;" \ | |
80 | "bootm ${fit_addr_r}\0" \ | |
81 | "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ | |
82 | "${fit_file}\0" \ | |
83 | "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ | |
84 | "${uboot}\0" \ | |
85 | "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ | |
86 | "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ | |
87 | "setexpr uboot_maxsize ${uboot_sz} - 400;" \ | |
88 | "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ | |
89 | "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ | |
90 | "sf write ${loadaddr} 400 ${filesize};" \ | |
91 | "sf read ${cmp_buf} 400 ${uboot_sz};" \ | |
92 | "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ | |
93 | "ubiboot=echo Booting from ubi ...; " \ | |
94 | "run ubiargs addmtd addmisc set_fit_default;" \ | |
95 | "bootm ${fit_addr_r}\0" \ | |
7254d92e HS |
96 | "rescueargs=setenv bootargs console=${console},${baudrate} " \ |
97 | "root=/dev/ram rw\0 " \ | |
98 | "rescueboot=echo Booting rescue system from NOR ...; " \ | |
99 | "run rescueargs addmtd addmisc set_fit_default;" \ | |
100 | "bootm ${fit_addr_r}\0" \ | |
101 | "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ | |
102 | "${rescue_sys_length}; imi ${fit_addr_r}\0" \ | |
103 | CONFIG_EXTRA_ENV_BOARD_SETTINGS | |
104 | ||
105 | #define CONFIG_BOOTCOMMAND \ | |
106 | "mmc dev ${mmcdev};" \ | |
107 | "if mmc rescan; then " \ | |
108 | "if run loadbootscript; then " \ | |
109 | "run bootscript; " \ | |
110 | "else " \ | |
111 | "if run mmc_load_fit; then " \ | |
112 | "run mmcboot; " \ | |
113 | "else " \ | |
114 | "if run ubifs_load_fit; then " \ | |
115 | "run ubiboot; " \ | |
116 | "else " \ | |
117 | "if run rescue_load_fit; then " \ | |
118 | "run rescueboot; " \ | |
119 | "else " \ | |
120 | "echo RESCUE SYSTEM BOOT " \ | |
121 | "FAILURE;" \ | |
122 | "fi; " \ | |
123 | "fi; " \ | |
124 | "fi; " \ | |
125 | "fi; " \ | |
126 | "else " \ | |
127 | "if run ubifs_load_fit; then " \ | |
128 | "run ubiboot; " \ | |
129 | "else " \ | |
130 | "if run rescue_load_fit; then " \ | |
131 | "run rescueboot; " \ | |
132 | "else " \ | |
133 | "echo RESCUE SYSTEM BOOT FAILURE;" \ | |
134 | "fi; " \ | |
135 | "fi; " \ | |
136 | "fi" | |
137 | ||
138 | #define CONFIG_ARP_TIMEOUT 200UL | |
139 | ||
7254d92e HS |
140 | /* Print Buffer Size */ |
141 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
7254d92e HS |
142 | |
143 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
144 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) | |
145 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
146 | ||
7254d92e HS |
147 | /* Physical Memory Map */ |
148 | #define CONFIG_NR_DRAM_BANKS 1 | |
149 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
150 | ||
151 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
152 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
153 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
154 | ||
155 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
156 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
157 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
158 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
159 | ||
056845c2 | 160 | /* Environment organization */ |
7254d92e | 161 | #define CONFIG_ENV_SIZE (12 * 1024) |
7254d92e HS |
162 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
163 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
164 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
165 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
166 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
167 | #define CONFIG_ENV_SECT_SIZE (0x010000) | |
168 | #define CONFIG_ENV_OFFSET (0x0d0000) | |
169 | #define CONFIG_ENV_OFFSET_REDUND (0x0e0000) | |
170 | ||
7254d92e HS |
171 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
172 | ||
173 | /* I2C */ | |
7254d92e HS |
174 | #define CONFIG_SYS_I2C |
175 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
176 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
177 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
7254d92e HS |
178 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
179 | #define CONFIG_SYS_I2C_SPEED 100000 | |
180 | #define CONFIG_SYS_I2C_SLAVE 0x7f | |
181 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } | |
182 | ||
7254d92e | 183 | /* NAND stuff */ |
7254d92e HS |
184 | #define CONFIG_NAND_MXS |
185 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
186 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
187 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
188 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
189 | ||
190 | /* DMA stuff, needed for GPMI/MXS NAND support */ | |
191 | #define CONFIG_APBH_DMA | |
192 | #define CONFIG_APBH_DMA_BURST | |
193 | #define CONFIG_APBH_DMA_BURST8 | |
194 | ||
195 | /* RTC */ | |
196 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
197 | #define CONFIG_SYS_RTC_BUS_NUM 2 | |
198 | #define CONFIG_RTC_M41T11 | |
7254d92e HS |
199 | |
200 | /* USB Configs */ | |
7254d92e HS |
201 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
202 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
203 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
204 | #define CONFIG_MXC_USB_FLAGS 0 | |
205 | ||
206 | /* UBI support */ | |
7254d92e HS |
207 | #define CONFIG_MTD_PARTITIONS |
208 | #define CONFIG_MTD_DEVICE | |
7254d92e | 209 | |
7254d92e HS |
210 | #define CONFIG_HW_WATCHDOG |
211 | #define CONFIG_IMX_WATCHDOG | |
212 | ||
7254d92e | 213 | /* Framebuffer */ |
7254d92e HS |
214 | #define CONFIG_VIDEO_IPUV3 |
215 | /* check this console not needed, after test remove it */ | |
7254d92e HS |
216 | #define CONFIG_VIDEO_BMP_RLE8 |
217 | #define CONFIG_SPLASH_SCREEN | |
218 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
219 | #define CONFIG_BMP_16BPP | |
220 | #define CONFIG_VIDEO_LOGO | |
221 | #define CONFIG_VIDEO_BMP_LOGO | |
222 | #define CONFIG_IPUV3_CLK 198000000 | |
223 | #define CONFIG_IMX_VIDEO_SKIP | |
224 | ||
7254d92e HS |
225 | #define CONFIG_PWM_IMX |
226 | #define CONFIG_IMX6_PWM_PER_CLK 66000000 | |
227 | ||
228 | #endif /* __ARISTAINETOS_COMMON_CONFIG_H */ |