[people/ms/u-boot.git] / include / configs / at91sam9261ek.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9261EK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */

#ifdef CONFIG_AT91SAM9G10
#define CONFIG_AT91SAM9G10EK		/* It's an Atmel AT91SAM9G10 EK*/
#else
#define CONFIG_AT91SAM9261EK		/* It's an Atmel AT91SAM9261 EK*/
#endif

#include <asm/hardware.h>

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_DISPLAY_CPUINFO

#define CONFIG_ATMEL_LEGACY
#define CONFIG_SYS_TEXT_BASE		0x21f00000

/*
 * Hardware drivers
 */

/* gpio */
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP		1

/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define CONFIG_USART_ID			ATMEL_ID_SYS
#define CONFIG_BAUDRATE			115200

/* LCD */
#define CONFIG_LCD
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_LCD
#ifdef CONFIG_AT91SAM9261EK
#define CONFIG_ATMEL_LCD_BGR555
#endif

#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* LED */
#define CONFIG_AT91_LED
#define	CONFIG_RED_LED		AT91_PIN_PA23	/* this is the power led */
#define	CONFIG_GREEN_LED	AT91_PIN_PA13	/* this is the user1 led */
#define	CONFIG_YELLOW_LED	AT91_PIN_PA14	/* this is the user2 led */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_NAND

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000
#define CONFIG_SYS_INIT_SP_ADDR \
	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)

/* DataFlash */
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
#define AT91_SPI_CLK				15000000
#define DATAFLASH_TCSS				(0x1a << 16)
#define DATAFLASH_TCHS				(0x1 << 24)

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15

#endif

/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH

/* Ethernet */
#define CONFIG_DRIVER_DM9000
#define CONFIG_DM9000_BASE		0x30000000
#define DM9000_IO			CONFIG_DM9000_BASE
#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT
#define CONFIG_DM9000_NO_SROM
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
#ifdef CONFIG_AT91SAM9G10EK
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g10"
#else
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#ifdef CONFIG_SYS_USE_DATAFLASH_CS0

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_IS_IN_DATAFLASH
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock0 "			\
				"mtdparts=atmel_nand:-(root) "		\
				"rw rootfstype=jffs2"

#elif CONFIG_SYS_USE_DATAFLASH_CS3

/* bootstrap + u-boot + env + linux in dataflash on CS3 */
#define CONFIG_ENV_IS_IN_DATAFLASH
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xD0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock0 "			\
				"mtdparts=atmel_nand:-(root) "		\
				"rw rootfstype=jffs2"

#else /* CONFIG_SYS_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0xc0000
#define CONFIG_ENV_OFFSET_REDUND	0x100000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
#define CONFIG_BOOTARGS							\
	"console=ttyS0,115200 earlyprintk "				\
	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
	"256k(env),256k(env_redundant),256k(spare),"			\
	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
	"root=/dev/mtdblock7 rw rootfstype=jffs2"
#endif

#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)

#endif
Commit	Line	Data
d99a8ff6 SP	1	/*
d99a8ff6 SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
d99a8ff6 SP	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Configuation settings for the AT91SAM9261EK board.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
d99a8ff6 SP	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/* ARM asynchronous clock */
f7aea46d	15	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
7c966a8b	16	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
d99a8ff6	17
f7aea46d XH	18	#ifdef CONFIG_AT91SAM9G10
f7aea46d XH	19	#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
5ccc2d99	20	#else
f7aea46d	21	#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
5ccc2d99	22	#endif
f7aea46d XH	23
	24	#include <asm/hardware.h>
	25
f7aea46d XH	26	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	27	#define CONFIG_SETUP_MEMORY_TAGS
	28	#define CONFIG_INITRD_TAG
d99a8ff6 SP	29
d99a8ff6 SP	30	#define CONFIG_SKIP_LOWLEVEL_INIT
d99a8ff6	31
f7aea46d XH	32	#define CONFIG_DISPLAY_CPUINFO
	33
	34	#define CONFIG_ATMEL_LEGACY
	35	#define CONFIG_SYS_TEXT_BASE 0x21f00000
	36
d99a8ff6 SP	37	/*
	38	* Hardware drivers
	39	*/
f7aea46d XH	40
	41	/* gpio */
	42	#define CONFIG_AT91_GPIO
	43	#define CONFIG_AT91_GPIO_PULLUP 1
	44
	45	/* serial console */
	46	#define CONFIG_ATMEL_USART
	47	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	48	#define CONFIG_USART_ID ATMEL_ID_SYS
	49	#define CONFIG_BAUDRATE 115200
d99a8ff6	50
820f2a95	51	/* LCD */
f7aea46d	52	#define CONFIG_LCD
820f2a95	53	#define LCD_BPP LCD_COLOR8
f7aea46d	54	#define CONFIG_LCD_LOGO
820f2a95	55	#undef LCD_TEST_PATTERN
f7aea46d XH	56	#define CONFIG_LCD_INFO
	57	#define CONFIG_LCD_INFO_BELOW_LOGO
	58	#define CONFIG_SYS_WHITE_ON_BLACK
	59	#define CONFIG_ATMEL_LCD
5ccc2d99	60	#ifdef CONFIG_AT91SAM9261EK
f7aea46d	61	#define CONFIG_ATMEL_LCD_BGR555
5ccc2d99	62	#endif
f7aea46d XH	63
f7aea46d XH	64	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
820f2a95	65
a484b00b JCPV	66	/* LED */
	67	#define CONFIG_AT91_LED
	68	#define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */
	69	#define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */
	70	#define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */
	71
d99a8ff6	72
d99a8ff6 SP	73	/*
	74	* BOOTP options
	75	*/
f7aea46d XH	76	#define CONFIG_BOOTP_BOOTFILESIZE
	77	#define CONFIG_BOOTP_BOOTPATH
	78	#define CONFIG_BOOTP_GATEWAY
	79	#define CONFIG_BOOTP_HOSTNAME
d99a8ff6 SP	80
	81	/*
	82	* Command line configuration.
	83	*/
f7aea46d	84	#define CONFIG_CMD_NAND
d99a8ff6 SP	85
	86	/* SDRAM */
	87	#define CONFIG_NR_DRAM_BANKS 1
f7aea46d XH	88	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	89	#define CONFIG_SYS_SDRAM_SIZE 0x04000000
	90	#define CONFIG_SYS_INIT_SP_ADDR \
	91	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
d99a8ff6 SP	92
d99a8ff6 SP	93	/* DataFlash */
4758ebdd	94	#define CONFIG_ATMEL_DATAFLASH_SPI
f7aea46d	95	#define CONFIG_HAS_DATAFLASH
6d0f6bcf JCPV	96	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
	97	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
	98	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
f7aea46d XH	99	#define AT91_SPI_CLK 15000000
	100	#define DATAFLASH_TCSS (0x1a << 16)
	101	#define DATAFLASH_TCHS (0x1 << 24)
d99a8ff6 SP	102
d99a8ff6 SP	103	/* NAND flash */
74c076d6 JCPV	104	#ifdef CONFIG_CMD_NAND
74c076d6 JCPV	105	#define CONFIG_NAND_ATMEL
6d0f6bcf JCPV	106	#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf JCPV	107	#define CONFIG_SYS_NAND_BASE 0x40000000
f7aea46d	108	#define CONFIG_SYS_NAND_DBW_8
74c076d6 JCPV	109	/* our ALE is AD22 */
	110	#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
	111	/* our CLE is AD21 */
	112	#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
	113	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	114	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
2eb99ca8	115
74c076d6	116	#endif
d99a8ff6 SP	117
d99a8ff6 SP	118	/* NOR flash - no real flash on this board */
f7aea46d	119	#define CONFIG_SYS_NO_FLASH
d99a8ff6 SP	120
d99a8ff6 SP	121	/* Ethernet */
f7aea46d	122	#define CONFIG_DRIVER_DM9000
d99a8ff6 SP	123	#define CONFIG_DM9000_BASE 0x30000000
	124	#define DM9000_IO CONFIG_DM9000_BASE
	125	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
f7aea46d XH	126	#define CONFIG_DM9000_USE_16BIT
f7aea46d XH	127	#define CONFIG_DM9000_NO_SROM
d99a8ff6	128	#define CONFIG_NET_RETRY_COUNT 20
f7aea46d	129	#define CONFIG_RESET_PHY_R
d99a8ff6 SP	130
d99a8ff6 SP	131	/* USB */
2b7178af	132	#define CONFIG_USB_ATMEL
dcd2f1a0	133	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
f7aea46d XH	134	#define CONFIG_USB_OHCI_NEW
	135	#define CONFIG_DOS_PARTITION
	136	#define CONFIG_SYS_USB_OHCI_CPU_INIT
6d0f6bcf	137	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
5ccc2d99 SG	138	#ifdef CONFIG_AT91SAM9G10EK
	139	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
	140	#else
6d0f6bcf	141	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
5ccc2d99	142	#endif
6d0f6bcf	143	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
f7aea46d	144	#define CONFIG_USB_STORAGE
d99a8ff6	145
6d0f6bcf	146	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
d99a8ff6	147
f7aea46d	148	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
6d0f6bcf	149	#define CONFIG_SYS_MEMTEST_END 0x23e00000
d99a8ff6	150
6d0f6bcf	151	#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
d99a8ff6 SP	152
d99a8ff6 SP	153	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
f7aea46d	154	#define CONFIG_ENV_IS_IN_DATAFLASH
6d0f6bcf	155	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
89a7a87f	156	#define CONFIG_ENV_OFFSET 0x4200
6d0f6bcf	157	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
0e8d1586	158	#define CONFIG_ENV_SIZE 0x4200
e139cb31	159	#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
d99a8ff6 SP	160	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
d99a8ff6 SP	161	"root=/dev/mtdblock0 " \
918319c7	162	"mtdparts=atmel_nand:-(root) " \
d99a8ff6 SP	163	"rw rootfstype=jffs2"
d99a8ff6 SP	164
89a7a87f NF	165	#elif CONFIG_SYS_USE_DATAFLASH_CS3
	166
	167	/* bootstrap + u-boot + env + linux in dataflash on CS3 */
f7aea46d	168	#define CONFIG_ENV_IS_IN_DATAFLASH
89a7a87f NF	169	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
	170	#define CONFIG_ENV_OFFSET 0x4200
	171	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
	172	#define CONFIG_ENV_SIZE 0x4200
e139cb31	173	#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
89a7a87f NF	174	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
89a7a87f NF	175	"root=/dev/mtdblock0 " \
918319c7	176	"mtdparts=atmel_nand:-(root) " \
89a7a87f NF	177	"rw rootfstype=jffs2"
89a7a87f NF	178
6d0f6bcf	179	#else /* CONFIG_SYS_USE_NANDFLASH */
d99a8ff6 SP	180
d99a8ff6 SP	181	/* bootstrap + u-boot + env + linux in nandflash */
f7aea46d	182	#define CONFIG_ENV_IS_IN_NAND
0c58cfa9 BS	183	#define CONFIG_ENV_OFFSET 0xc0000
0c58cfa9 BS	184	#define CONFIG_ENV_OFFSET_REDUND 0x100000
0e8d1586	185	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
0c58cfa9 BS	186	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
	187	#define CONFIG_BOOTARGS \
	188	"console=ttyS0,115200 earlyprintk " \
	189	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
	190	"256k(env),256k(env_redundant),256k(spare)," \
	191	"512k(dtb),6M(kernel)ro,-(rootfs) " \
	192	"root=/dev/mtdblock7 rw rootfstype=jffs2"
d99a8ff6 SP	193	#endif
d99a8ff6 SP	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_CBSIZE 256
6d0f6bcf JCPV	196	#define CONFIG_SYS_MAXARGS 16
f7aea46d XH	197	#define CONFIG_SYS_LONGHELP
f7aea46d XH	198	#define CONFIG_CMDLINE_EDITING
e139cb31	199	#define CONFIG_AUTO_COMPLETE
d99a8ff6	200
d99a8ff6 SP	201	/*
	202	* Size of malloc() pool
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
d99a8ff6	205
d99a8ff6	206	#endif