projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d99a8ff6 SP |
1 | /* |
| 2 | * (C) Copyright 2007-2008 | |
| c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
| d99a8ff6 SP |
4 | * Lead Tech Design <www.leadtechdesign.com> |
| 5 | * | |
| 6 | * Configuation settings for the AT91SAM9261EK board. | |
| 7 | * | |
| 1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| d99a8ff6 SP |
9 | */ |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 14 | /* ARM asynchronous clock */ | |
| f7aea46d | 15 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 7c966a8b | 16 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ |
| d99a8ff6 | 17 | |
| f7aea46d XH |
18 | #ifdef CONFIG_AT91SAM9G10 |
| 19 | #define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ | |
| 5ccc2d99 | 20 | #else |
| f7aea46d | 21 | #define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ |
| 5ccc2d99 | 22 | #endif |
| f7aea46d XH |
23 | |
| 24 | #include <asm/hardware.h> | |
| 25 | ||
| f7aea46d XH |
26 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 27 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 28 | #define CONFIG_INITRD_TAG | |
| d99a8ff6 SP |
29 | |
| 30 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| d99a8ff6 | 31 | |
| f7aea46d XH |
32 | #define CONFIG_DISPLAY_CPUINFO |
| 33 | ||
| dc3e30ba BS |
34 | #define CONFIG_OF_LIBFDT |
| 35 | ||
| f7aea46d XH |
36 | #define CONFIG_ATMEL_LEGACY |
| 37 | #define CONFIG_SYS_TEXT_BASE 0x21f00000 | |
| 38 | ||
| d99a8ff6 SP |
39 | /* |
| 40 | * Hardware drivers | |
| 41 | */ | |
| f7aea46d XH |
42 | |
| 43 | /* gpio */ | |
| 44 | #define CONFIG_AT91_GPIO | |
| 45 | #define CONFIG_AT91_GPIO_PULLUP 1 | |
| 46 | ||
| 47 | /* serial console */ | |
| 48 | #define CONFIG_ATMEL_USART | |
| 49 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
| 50 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
| 51 | #define CONFIG_BAUDRATE 115200 | |
| d99a8ff6 | 52 | |
| 820f2a95 | 53 | /* LCD */ |
| f7aea46d | 54 | #define CONFIG_LCD |
| 820f2a95 | 55 | #define LCD_BPP LCD_COLOR8 |
| f7aea46d | 56 | #define CONFIG_LCD_LOGO |
| 820f2a95 | 57 | #undef LCD_TEST_PATTERN |
| f7aea46d XH |
58 | #define CONFIG_LCD_INFO |
| 59 | #define CONFIG_LCD_INFO_BELOW_LOGO | |
| 60 | #define CONFIG_SYS_WHITE_ON_BLACK | |
| 61 | #define CONFIG_ATMEL_LCD | |
| 5ccc2d99 | 62 | #ifdef CONFIG_AT91SAM9261EK |
| f7aea46d | 63 | #define CONFIG_ATMEL_LCD_BGR555 |
| 5ccc2d99 | 64 | #endif |
| f7aea46d XH |
65 | |
| 66 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 820f2a95 | 67 | |
| a484b00b JCPV |
68 | /* LED */ |
| 69 | #define CONFIG_AT91_LED | |
| 70 | #define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */ | |
| 71 | #define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */ | |
| 72 | #define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */ | |
| 73 | ||
| d99a8ff6 SP |
74 | #define CONFIG_BOOTDELAY 3 |
| 75 | ||
| d99a8ff6 SP |
76 | /* |
| 77 | * BOOTP options | |
| 78 | */ | |
| f7aea46d XH |
79 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 80 | #define CONFIG_BOOTP_BOOTPATH | |
| 81 | #define CONFIG_BOOTP_GATEWAY | |
| 82 | #define CONFIG_BOOTP_HOSTNAME | |
| d99a8ff6 SP |
83 | |
| 84 | /* | |
| 85 | * Command line configuration. | |
| 86 | */ | |
| 87 | #include <config_cmd_default.h> | |
| 88 | #undef CONFIG_CMD_BDI | |
| d99a8ff6 | 89 | #undef CONFIG_CMD_FPGA |
| 74de7aef | 90 | #undef CONFIG_CMD_IMI |
| d99a8ff6 | 91 | #undef CONFIG_CMD_IMLS |
| 74de7aef WD |
92 | #undef CONFIG_CMD_LOADS |
| 93 | #undef CONFIG_CMD_SOURCE | |
| d99a8ff6 | 94 | |
| f7aea46d XH |
95 | #define CONFIG_CMD_PING |
| 96 | #define CONFIG_CMD_DHCP | |
| 97 | #define CONFIG_CMD_NAND | |
| 98 | #define CONFIG_CMD_USB | |
| d99a8ff6 SP |
99 | |
| 100 | /* SDRAM */ | |
| 101 | #define CONFIG_NR_DRAM_BANKS 1 | |
| f7aea46d XH |
102 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 103 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
| 104 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
| 105 | (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
| d99a8ff6 SP |
106 | |
| 107 | /* DataFlash */ | |
| 4758ebdd | 108 | #define CONFIG_ATMEL_DATAFLASH_SPI |
| f7aea46d | 109 | #define CONFIG_HAS_DATAFLASH |
| 6d0f6bcf JCPV |
110 | #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) |
| 111 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 | |
| 112 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
| 113 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ | |
| f7aea46d XH |
114 | #define AT91_SPI_CLK 15000000 |
| 115 | #define DATAFLASH_TCSS (0x1a << 16) | |
| 116 | #define DATAFLASH_TCHS (0x1 << 24) | |
| d99a8ff6 SP |
117 | |
| 118 | /* NAND flash */ | |
| 74c076d6 JCPV |
119 | #ifdef CONFIG_CMD_NAND |
| 120 | #define CONFIG_NAND_ATMEL | |
| 6d0f6bcf JCPV |
121 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 122 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
| f7aea46d | 123 | #define CONFIG_SYS_NAND_DBW_8 |
| 74c076d6 JCPV |
124 | /* our ALE is AD22 */ |
| 125 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) | |
| 126 | /* our CLE is AD21 */ | |
| 127 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) | |
| 128 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
| 129 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 | |
| 2eb99ca8 | 130 | |
| 74c076d6 | 131 | #endif |
| d99a8ff6 SP |
132 | |
| 133 | /* NOR flash - no real flash on this board */ | |
| f7aea46d | 134 | #define CONFIG_SYS_NO_FLASH |
| d99a8ff6 SP |
135 | |
| 136 | /* Ethernet */ | |
| f7aea46d | 137 | #define CONFIG_DRIVER_DM9000 |
| d99a8ff6 SP |
138 | #define CONFIG_DM9000_BASE 0x30000000 |
| 139 | #define DM9000_IO CONFIG_DM9000_BASE | |
| 140 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
| f7aea46d XH |
141 | #define CONFIG_DM9000_USE_16BIT |
| 142 | #define CONFIG_DM9000_NO_SROM | |
| d99a8ff6 | 143 | #define CONFIG_NET_RETRY_COUNT 20 |
| f7aea46d | 144 | #define CONFIG_RESET_PHY_R |
| d99a8ff6 SP |
145 | |
| 146 | /* USB */ | |
| 2b7178af | 147 | #define CONFIG_USB_ATMEL |
| f7aea46d XH |
148 | #define CONFIG_USB_OHCI_NEW |
| 149 | #define CONFIG_DOS_PARTITION | |
| 150 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
| 6d0f6bcf | 151 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ |
| 5ccc2d99 SG |
152 | #ifdef CONFIG_AT91SAM9G10EK |
| 153 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" | |
| 154 | #else | |
| 6d0f6bcf | 155 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" |
| 5ccc2d99 | 156 | #endif |
| 6d0f6bcf | 157 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
| f7aea46d XH |
158 | #define CONFIG_USB_STORAGE |
| 159 | #define CONFIG_CMD_FAT | |
| d99a8ff6 | 160 | |
| 6d0f6bcf | 161 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| d99a8ff6 | 162 | |
| f7aea46d | 163 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 6d0f6bcf | 164 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
| d99a8ff6 | 165 | |
| 6d0f6bcf | 166 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 |
| d99a8ff6 SP |
167 | |
| 168 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
| f7aea46d | 169 | #define CONFIG_ENV_IS_IN_DATAFLASH |
| 6d0f6bcf | 170 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
| 89a7a87f | 171 | #define CONFIG_ENV_OFFSET 0x4200 |
| 6d0f6bcf | 172 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
| 0e8d1586 | 173 | #define CONFIG_ENV_SIZE 0x4200 |
| e139cb31 | 174 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" |
| d99a8ff6 SP |
175 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
| 176 | "root=/dev/mtdblock0 " \ | |
| 918319c7 | 177 | "mtdparts=atmel_nand:-(root) " \ |
| d99a8ff6 SP |
178 | "rw rootfstype=jffs2" |
| 179 | ||
| 89a7a87f NF |
180 | #elif CONFIG_SYS_USE_DATAFLASH_CS3 |
| 181 | ||
| 182 | /* bootstrap + u-boot + env + linux in dataflash on CS3 */ | |
| f7aea46d | 183 | #define CONFIG_ENV_IS_IN_DATAFLASH |
| 89a7a87f NF |
184 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400) |
| 185 | #define CONFIG_ENV_OFFSET 0x4200 | |
| 186 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET) | |
| 187 | #define CONFIG_ENV_SIZE 0x4200 | |
| e139cb31 | 188 | #define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm" |
| 89a7a87f NF |
189 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
| 190 | "root=/dev/mtdblock0 " \ | |
| 918319c7 | 191 | "mtdparts=atmel_nand:-(root) " \ |
| 89a7a87f NF |
192 | "rw rootfstype=jffs2" |
| 193 | ||
| 6d0f6bcf | 194 | #else /* CONFIG_SYS_USE_NANDFLASH */ |
| d99a8ff6 SP |
195 | |
| 196 | /* bootstrap + u-boot + env + linux in nandflash */ | |
| f7aea46d | 197 | #define CONFIG_ENV_IS_IN_NAND |
| 0c58cfa9 BS |
198 | #define CONFIG_ENV_OFFSET 0xc0000 |
| 199 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 | |
| 0e8d1586 | 200 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
| 0c58cfa9 BS |
201 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
| 202 | #define CONFIG_BOOTARGS \ | |
| 203 | "console=ttyS0,115200 earlyprintk " \ | |
| 204 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ | |
| 205 | "256k(env),256k(env_redundant),256k(spare)," \ | |
| 206 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ | |
| 207 | "root=/dev/mtdblock7 rw rootfstype=jffs2" | |
| d99a8ff6 SP |
208 | #endif |
| 209 | ||
| 6d0f6bcf JCPV |
210 | #define CONFIG_SYS_PROMPT "U-Boot> " |
| 211 | #define CONFIG_SYS_CBSIZE 256 | |
| 212 | #define CONFIG_SYS_MAXARGS 16 | |
| 213 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| f7aea46d XH |
214 | #define CONFIG_SYS_LONGHELP |
| 215 | #define CONFIG_CMDLINE_EDITING | |
| e139cb31 | 216 | #define CONFIG_AUTO_COMPLETE |
| d99a8ff6 | 217 | |
| d99a8ff6 SP |
218 | /* |
| 219 | * Size of malloc() pool | |
| 220 | */ | |
| 6d0f6bcf | 221 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
| d99a8ff6 | 222 | |
| d99a8ff6 | 223 | #endif |