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Commit | Line | Data |
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7aa78614 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
7aa78614 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
21 | #define CONFIG_ATC 1 /* ...on a ATC board */ | |
9c4c5ae3 | 22 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
7aa78614 | 23 | |
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 |
25 | ||
7aa78614 WD |
26 | /* |
27 | * select serial console configuration | |
28 | * | |
29 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
30 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
31 | * for SCC). | |
32 | * | |
33 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
34 | * defined elsewhere (for example, on the cogent platform, there are serial | |
35 | * ports on the motherboard which are used for the serial console - see | |
36 | * cogent/cma101/serial.[ch]). | |
37 | */ | |
38 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
39 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
40 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
41 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
42 | ||
43 | #define CONFIG_BAUDRATE 115200 | |
44 | ||
45 | /* | |
46 | * select ethernet configuration | |
47 | * | |
48 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
49 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
50 | * for FCC) | |
51 | * | |
52 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 53 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
7aa78614 WD |
54 | */ |
55 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
56 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
57 | #define CONFIG_ETHER_ON_FCC | |
58 | ||
7aa78614 WD |
59 | #define CONFIG_ETHER_ON_FCC2 |
60 | ||
61 | /* | |
62 | * - Rx-CLK is CLK13 | |
63 | * - Tx-CLK is CLK14 | |
64 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
65 | * - Enable Full Duplex in FSMR | |
66 | */ | |
6d0f6bcf JCPV |
67 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
68 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
69 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
70 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
7aa78614 WD |
71 | |
72 | #define CONFIG_ETHER_ON_FCC3 | |
73 | ||
74 | /* | |
75 | * - Rx-CLK is CLK15 | |
76 | * - Tx-CLK is CLK16 | |
77 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
78 | * - Enable Half Duplex in FSMR | |
79 | */ | |
6d0f6bcf JCPV |
80 | # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) |
81 | # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
7aa78614 WD |
82 | |
83 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
84 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ | |
85 | ||
86 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
87 | ||
88 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ | |
89 | ||
90 | #define CONFIG_PREBOOT \ | |
91 | "echo;" \ | |
32bf3d14 | 92 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\ |
7aa78614 WD |
93 | "echo" |
94 | ||
95 | #undef CONFIG_BOOTARGS | |
96 | #define CONFIG_BOOTCOMMAND \ | |
97 | "bootp;" \ | |
98 | "setenv bootargs root=/dev/nfs rw " \ | |
53677ef1 | 99 | "nfsroot=${serverip}:${rootpath} " \ |
fe126d8b | 100 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ |
7aa78614 WD |
101 | "bootm" |
102 | ||
103 | /*----------------------------------------------------------------------- | |
104 | * Miscellaneous configuration options | |
105 | */ | |
106 | ||
107 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 108 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
7aa78614 | 109 | |
2fd90ce5 JL |
110 | |
111 | /* | |
112 | * BOOTP options | |
113 | */ | |
114 | #define CONFIG_BOOTP_SUBNETMASK | |
115 | #define CONFIG_BOOTP_GATEWAY | |
116 | #define CONFIG_BOOTP_HOSTNAME | |
117 | #define CONFIG_BOOTP_BOOTPATH | |
118 | #define CONFIG_BOOTP_BOOTFILESIZE | |
7aa78614 | 119 | |
15ef8a5d | 120 | |
0b361c91 JL |
121 | /* |
122 | * Command line configuration. | |
123 | */ | |
124 | #include <config_cmd_default.h> | |
15ef8a5d | 125 | |
0b361c91 JL |
126 | #define CONFIG_CMD_EEPROM |
127 | #define CONFIG_CMD_PCI | |
128 | #define CONFIG_CMD_PCMCIA | |
129 | #define CONFIG_CMD_DATE | |
130 | #define CONFIG_CMD_IDE | |
7aa78614 | 131 | |
0b361c91 JL |
132 | |
133 | #define CONFIG_DOS_PARTITION | |
7aa78614 WD |
134 | |
135 | /* | |
136 | * Miscellaneous configurable options | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
0b361c91 | 139 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 140 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7aa78614 | 141 | #else |
6d0f6bcf | 142 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7aa78614 | 143 | #endif |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
145 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
146 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7aa78614 | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
149 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
7aa78614 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
7aa78614 | 152 | |
6d0f6bcf | 153 | #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
66fd3d1c | 154 | |
6d0f6bcf | 155 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */ |
7aa78614 | 156 | |
6d0f6bcf | 157 | #define CONFIG_SYS_ALLOC_DPRAM |
7aa78614 WD |
158 | |
159 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
160 | ||
161 | #define CONFIG_SPI | |
162 | ||
15ef8a5d WD |
163 | #define CONFIG_RTC_DS12887 |
164 | ||
53677ef1 WD |
165 | #define RTC_BASE_ADDR 0xF5000000 |
166 | #define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 | |
167 | #define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 | |
15ef8a5d WD |
168 | |
169 | #define CONFIG_MISC_INIT_R | |
170 | ||
7aa78614 WD |
171 | /* |
172 | * For booting Linux, the board info and command line data | |
173 | * have to be in the first 8 MB of memory, since this is | |
174 | * the maximum mapped by the Linux kernel during initialization. | |
175 | */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7aa78614 WD |
177 | |
178 | /*----------------------------------------------------------------------- | |
179 | * Flash configuration | |
180 | */ | |
181 | ||
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
183 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 | |
7aa78614 WD |
184 | |
185 | /*----------------------------------------------------------------------- | |
186 | * FLASH organization | |
187 | */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
189 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
7aa78614 | 190 | |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
192 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
7aa78614 WD |
193 | |
194 | #define CONFIG_FLASH_16BIT | |
195 | ||
196 | /*----------------------------------------------------------------------- | |
197 | * Hard Reset Configuration Words | |
198 | * | |
6d0f6bcf | 199 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
7aa78614 | 200 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 201 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
7aa78614 | 202 | */ |
6d0f6bcf | 203 | #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ |
9a0e21a3 | 204 | HRCW_BPS10 |\ |
7aa78614 WD |
205 | HRCW_APPC10) |
206 | ||
207 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
209 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
210 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
211 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
212 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
213 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
214 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
7aa78614 WD |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * Internal Memory Mapped Register | |
218 | */ | |
6d0f6bcf | 219 | #define CONFIG_SYS_IMMR 0xF0000000 |
7aa78614 WD |
220 | |
221 | /*----------------------------------------------------------------------- | |
222 | * Definitions for initial stack pointer and data area (in DPRAM) | |
223 | */ | |
6d0f6bcf | 224 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 225 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 226 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 227 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7aa78614 WD |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * Start addresses for the final memory configuration | |
231 | * (Set up by the startup code) | |
6d0f6bcf | 232 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7aa78614 | 233 | * |
6d0f6bcf | 234 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE. |
7aa78614 | 235 | */ |
6d0f6bcf JCPV |
236 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
237 | #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
14d0a02a | 238 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
240 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
7aa78614 | 241 | |
6d0f6bcf JCPV |
242 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
243 | # define CONFIG_SYS_RAMBOOT | |
7aa78614 WD |
244 | #endif |
245 | ||
66fd3d1c | 246 | #define CONFIG_PCI |
842033e6 | 247 | #define CONFIG_PCI_INDIRECT_BRIDGE |
66fd3d1c | 248 | #define CONFIG_PCI_PNP |
6d0f6bcf | 249 | #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ |
66fd3d1c | 250 | |
7aa78614 WD |
251 | #if 1 |
252 | /* environment is in Flash */ | |
5a1aceb0 | 253 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 254 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000) |
0e8d1586 JCPV |
255 | # define CONFIG_ENV_SIZE 0x10000 |
256 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
7aa78614 | 257 | #else |
bb1f8b4f | 258 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
0e8d1586 JCPV |
259 | #define CONFIG_ENV_OFFSET 0 |
260 | #define CONFIG_ENV_SIZE 2048 | |
6d0f6bcf | 261 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ |
7aa78614 | 262 | #endif |
7aa78614 WD |
263 | |
264 | /*----------------------------------------------------------------------- | |
265 | * Cache Configuration | |
266 | */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
0b361c91 | 268 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 269 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
7aa78614 WD |
270 | #endif |
271 | ||
272 | /*----------------------------------------------------------------------- | |
273 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
274 | *----------------------------------------------------------------------- | |
275 | * HID0 also contains cache control - initially enable both caches and | |
276 | * invalidate contents, then the final state leaves only the instruction | |
277 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
278 | * but Soft reset does not. | |
279 | * | |
280 | * HID1 has only read-only information - nothing to set. | |
281 | */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ |
8bde7f77 | 283 | HID0_DCI|HID0_IFEM|HID0_ABE) |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
285 | #define CONFIG_SYS_HID2 0 | |
7aa78614 WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * RMR - Reset Mode Register 5-5 | |
289 | *----------------------------------------------------------------------- | |
290 | * turn on Checkstop Reset Enable | |
291 | */ | |
6d0f6bcf | 292 | #define CONFIG_SYS_RMR RMR_CSRE |
7aa78614 WD |
293 | |
294 | /*----------------------------------------------------------------------- | |
295 | * BCR - Bus Configuration 4-25 | |
296 | *----------------------------------------------------------------------- | |
297 | */ | |
298 | #define BCR_APD01 0x10000000 | |
6d0f6bcf | 299 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
7aa78614 WD |
300 | |
301 | /*----------------------------------------------------------------------- | |
302 | * SIUMCR - SIU Module Configuration 4-31 | |
303 | *----------------------------------------------------------------------- | |
304 | */ | |
6d0f6bcf | 305 | #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\ |
7aa78614 WD |
306 | SIUMCR_CS10PC00|SIUMCR_BCTLC10) |
307 | ||
308 | /*----------------------------------------------------------------------- | |
309 | * SYPCR - System Protection Control 4-35 | |
310 | * SYPCR can only be written once after reset! | |
311 | *----------------------------------------------------------------------- | |
312 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
313 | */ | |
314 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 315 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 316 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
7aa78614 | 317 | #else |
6d0f6bcf | 318 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 319 | SYPCR_SWRI|SYPCR_SWP) |
7aa78614 WD |
320 | #endif /* CONFIG_WATCHDOG */ |
321 | ||
322 | /*----------------------------------------------------------------------- | |
323 | * TMCNTSC - Time Counter Status and Control 4-40 | |
324 | *----------------------------------------------------------------------- | |
325 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
326 | * and enable Time Counter | |
327 | */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
7aa78614 WD |
329 | |
330 | /*----------------------------------------------------------------------- | |
331 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
332 | *----------------------------------------------------------------------- | |
333 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
334 | * Periodic timer | |
335 | */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
7aa78614 WD |
337 | |
338 | /*----------------------------------------------------------------------- | |
339 | * SCCR - System Clock Control 9-8 | |
340 | *----------------------------------------------------------------------- | |
341 | * Ensure DFBRG is Divide by 16 | |
342 | */ | |
6d0f6bcf | 343 | #define CONFIG_SYS_SCCR SCCR_DFBRG01 |
7aa78614 WD |
344 | |
345 | /*----------------------------------------------------------------------- | |
346 | * RCCR - RISC Controller Configuration 13-7 | |
347 | *----------------------------------------------------------------------- | |
348 | */ | |
6d0f6bcf | 349 | #define CONFIG_SYS_RCCR 0 |
7aa78614 | 350 | |
6d0f6bcf | 351 | #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 |
7aa78614 WD |
352 | /*----------------------------------------------------------------------- |
353 | * MPTPR - Memory Refresh Timer Prescaler Register 10-18 | |
354 | *----------------------------------------------------------------------- | |
355 | */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_MPTPR 0x1F00 |
7aa78614 WD |
357 | |
358 | /*----------------------------------------------------------------------- | |
359 | * PSRT - Refresh Timer Register 10-16 | |
360 | *----------------------------------------------------------------------- | |
361 | */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_PSRT 0x0f |
7aa78614 WD |
363 | |
364 | /*----------------------------------------------------------------------- | |
365 | * PSRT - SDRAM Mode Register 10-10 | |
366 | *----------------------------------------------------------------------- | |
367 | */ | |
368 | ||
369 | /* SDRAM initialization values for 8-column chips | |
370 | */ | |
6d0f6bcf | 371 | #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ |
7aa78614 | 372 | ORxS_BPD_4 |\ |
f7de16ae WD |
373 | ORxS_ROWST_PBI1_A7 |\ |
374 | ORxS_NUMR_12) | |
7aa78614 | 375 | |
6d0f6bcf | 376 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ |
f7de16ae WD |
377 | PSDMR_SDAM_A15_IS_A5 |\ |
378 | PSDMR_BSMA_A15_A17 |\ | |
379 | PSDMR_SDA10_PBI1_A7 |\ | |
7aa78614 | 380 | PSDMR_RFRC_7_CLK |\ |
f7de16ae WD |
381 | PSDMR_PRETOACT_3W |\ |
382 | PSDMR_ACTTORW_2W |\ | |
7aa78614 WD |
383 | PSDMR_LDOTOPRE_1C |\ |
384 | PSDMR_WRC_1C |\ | |
385 | PSDMR_CL_2) | |
386 | ||
387 | /* SDRAM initialization values for 9-column chips | |
388 | */ | |
6d0f6bcf | 389 | #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ |
7aa78614 | 390 | ORxS_BPD_4 |\ |
f7de16ae WD |
391 | ORxS_ROWST_PBI1_A6 |\ |
392 | ORxS_NUMR_12) | |
7aa78614 | 393 | |
6d0f6bcf | 394 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ |
f7de16ae WD |
395 | PSDMR_SDAM_A16_IS_A5 |\ |
396 | PSDMR_BSMA_A15_A17 |\ | |
397 | PSDMR_SDA10_PBI1_A6 |\ | |
7aa78614 | 398 | PSDMR_RFRC_7_CLK |\ |
f7de16ae WD |
399 | PSDMR_PRETOACT_3W |\ |
400 | PSDMR_ACTTORW_2W |\ | |
7aa78614 WD |
401 | PSDMR_LDOTOPRE_1C |\ |
402 | PSDMR_WRC_1C |\ | |
403 | PSDMR_CL_2) | |
404 | ||
405 | /* | |
406 | * Init Memory Controller: | |
407 | * | |
408 | * Bank Bus Machine PortSz Device | |
409 | * ---- --- ------- ------ ------ | |
410 | * 0 60x GPCM 8 bit Boot ROM | |
411 | * 1 60x GPCM 64 bit FLASH | |
412 | * 2 60x SDRAM 64 bit SDRAM | |
413 | * | |
414 | */ | |
415 | ||
6d0f6bcf | 416 | #define CONFIG_SYS_MRS_OFFS 0x00000000 |
7aa78614 WD |
417 | |
418 | /* Bank 0 - FLASH | |
419 | */ | |
6d0f6bcf | 420 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
421 | BRx_PS_16 |\ |
422 | BRx_MS_GPCM_P |\ | |
423 | BRx_V) | |
7aa78614 | 424 | |
6d0f6bcf | 425 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
8bde7f77 WD |
426 | ORxG_CSNT |\ |
427 | ORxG_ACS_DIV1 |\ | |
428 | ORxG_SCY_3_CLK |\ | |
429 | ORxU_EHTR_8IDLE) | |
7aa78614 WD |
430 | |
431 | ||
432 | /* Bank 2 - 60x bus SDRAM | |
433 | */ | |
6d0f6bcf JCPV |
434 | #ifndef CONFIG_SYS_RAMBOOT |
435 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
8bde7f77 WD |
436 | BRx_PS_64 |\ |
437 | BRx_MS_SDRAM_P |\ | |
438 | BRx_V) | |
7aa78614 | 439 | |
6d0f6bcf | 440 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL |
7aa78614 | 441 | |
6d0f6bcf JCPV |
442 | #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL |
443 | #endif /* CONFIG_SYS_RAMBOOT */ | |
7aa78614 | 444 | |
6d0f6bcf | 445 | #define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\ |
8bde7f77 WD |
446 | BRx_PS_8 |\ |
447 | BRx_MS_UPMA |\ | |
448 | BRx_V) | |
15ef8a5d | 449 | |
6d0f6bcf | 450 | #define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI) |
8bde7f77 | 451 | |
66fd3d1c WD |
452 | /*----------------------------------------------------------------------- |
453 | * PCMCIA stuff | |
454 | *----------------------------------------------------------------------- | |
455 | * | |
456 | */ | |
457 | #define CONFIG_I82365 | |
458 | ||
6d0f6bcf JCPV |
459 | #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000 |
460 | #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 | |
66fd3d1c WD |
461 | |
462 | /*----------------------------------------------------------------------- | |
463 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
464 | *----------------------------------------------------------------------- | |
465 | */ | |
466 | ||
8d1165e1 | 467 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
66fd3d1c WD |
468 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
469 | ||
470 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
471 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
472 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
473 | ||
6d0f6bcf JCPV |
474 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
475 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
66fd3d1c | 476 | |
6d0f6bcf | 477 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
66fd3d1c | 478 | |
6d0f6bcf | 479 | #define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000 |
66fd3d1c WD |
480 | |
481 | /* Offset for data I/O */ | |
6d0f6bcf | 482 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x100 |
66fd3d1c WD |
483 | |
484 | /* Offset for normal register accesses */ | |
6d0f6bcf | 485 | #define CONFIG_SYS_ATA_REG_OFFSET 0x100 |
66fd3d1c WD |
486 | |
487 | /* Offset for alternate registers */ | |
6d0f6bcf | 488 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x108 |
66fd3d1c | 489 | |
7aa78614 | 490 | #endif /* __CONFIG_H */ |