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1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1003 CPU daughterboard
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
5d73bc7a 11#include <asm/arch/hardware.h>
a23e277c 12
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13#define CONFIG_AVR32
14#define CONFIG_AT32AP
15#define CONFIG_AT32AP7002
16#define CONFIG_ATSTK1004
17#define CONFIG_ATSTK1000
64ff2357 18
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19/*
20 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
21 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
22 * PLL frequency.
6d0f6bcf 23 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
64ff2357 24 */
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25#define CONFIG_PLL
26#define CONFIG_SYS_POWER_MANAGER
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27#define CONFIG_SYS_OSC0_HZ 20000000
28#define CONFIG_SYS_PLL0_DIV 1
29#define CONFIG_SYS_PLL0_MUL 7
30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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31/*
32 * Set the CPU running at:
6d0f6bcf 33 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
64ff2357 34 */
6d0f6bcf 35#define CONFIG_SYS_CLKDIV_CPU 0
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36/*
37 * Set the HSB running at:
6d0f6bcf 38 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
64ff2357 39 */
6d0f6bcf 40#define CONFIG_SYS_CLKDIV_HSB 1
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41/*
42 * Set the PBA running at:
6d0f6bcf 43 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
64ff2357 44 */
6d0f6bcf 45#define CONFIG_SYS_CLKDIV_PBA 2
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46/*
47 * Set the PBB running at:
6d0f6bcf 48 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
64ff2357 49 */
6d0f6bcf 50#define CONFIG_SYS_CLKDIV_PBB 1
64ff2357 51
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52/* Reserve VM regions for SDRAM and NOR flash */
53#define CONFIG_SYS_NR_VM_REGIONS 2
54
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55/*
56 * The PLLOPT register controls the PLL like this:
57 * icp = PLLOPT<2>
58 * ivco = PLLOPT<1:0>
59 *
60 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
61 */
6d0f6bcf 62#define CONFIG_SYS_PLL0_OPT 0x04
64ff2357 63
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64#define CONFIG_USART_BASE ATMEL_BASE_USART1
65#define CONFIG_USART_ID 1
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66
67/* User serviceable stuff */
4de58bcb 68#define CONFIG_DOS_PARTITION
64ff2357 69
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70#define CONFIG_CMDLINE_TAG
71#define CONFIG_SETUP_MEMORY_TAGS
72#define CONFIG_INITRD_TAG
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73
74#define CONFIG_STACKSIZE (2048)
75
76#define CONFIG_BAUDRATE 115200
77#define CONFIG_BOOTARGS \
78 "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
79
80#define CONFIG_BOOTCOMMAND \
72fa4679 81 "mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
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82
83/*
84 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
85 * data on the serial line may interrupt the boot sequence.
86 */
87#define CONFIG_BOOTDELAY 1
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88#define CONFIG_AUTOBOOT
89#define CONFIG_AUTOBOOT_KEYED
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90#define CONFIG_AUTOBOOT_PROMPT \
91 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
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92#define CONFIG_AUTOBOOT_DELAY_STR "d"
93#define CONFIG_AUTOBOOT_STOP_STR " "
94
95/*
96 * Command line configuration.
97 */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_ASKENV
101#define CONFIG_CMD_EXT2
102#define CONFIG_CMD_FAT
103#define CONFIG_CMD_JFFS2
104#define CONFIG_CMD_MMC
105
106#undef CONFIG_CMD_FPGA
107#undef CONFIG_CMD_NET
108#undef CONFIG_CMD_NFS
109#undef CONFIG_CMD_SETGETDCR
110#undef CONFIG_CMD_XIMG
111
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112#define CONFIG_ATMEL_USART
113#define CONFIG_PORTMUX_PIO
114#define CONFIG_SYS_HSDRAMC
115#define CONFIG_MMC
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116#define CONFIG_GENERIC_ATMEL_MCI
117#define CONFIG_GENERIC_MMC
64ff2357 118
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119#define CONFIG_SYS_DCACHE_LINESZ 32
120#define CONFIG_SYS_ICACHE_LINESZ 32
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121
122#define CONFIG_NR_DRAM_BANKS 1
123
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124#define CONFIG_SYS_FLASH_CFI
125#define CONFIG_FLASH_CFI_DRIVER
64ff2357 126
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127#define CONFIG_SYS_FLASH_BASE 0x00000000
128#define CONFIG_SYS_FLASH_SIZE 0x800000
129#define CONFIG_SYS_MAX_FLASH_BANKS 1
130#define CONFIG_SYS_MAX_FLASH_SECT 135
64ff2357 131
6d0f6bcf 132#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
47293c18 133#define CONFIG_SYS_TEXT_BASE 0x00000000
64ff2357 134
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135#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
136#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
137#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
64ff2357 138
4de58bcb 139#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 140#define CONFIG_ENV_SIZE 65536
6d0f6bcf 141#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
64ff2357 142
6d0f6bcf 143#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
64ff2357 144
6d0f6bcf 145#define CONFIG_SYS_MALLOC_LEN (256*1024)
64ff2357 146
b2e1d5b6 147/* Allow 2MB for the kernel run-time image */
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148#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
149#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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150
151/* Other configuration settings that shouldn't have to change all that often */
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152#define CONFIG_SYS_PROMPT "U-Boot> "
153#define CONFIG_SYS_CBSIZE 256
154#define CONFIG_SYS_MAXARGS 16
155#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
4de58bcb 156#define CONFIG_SYS_LONGHELP
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157
158#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
159#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
160#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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161
162#endif /* __CONFIG_H */