[people/ms/u-boot.git] / include / configs / axs101.h

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_AXS101_H_
#define _CONFIG_AXS101_H_

/*
 *  CPU configuration
 */
#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ

#define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
#define ARC_APB_PERIPHERAL_BASE		0xF0000000
#define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
#define ARC_DWGMAC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x18000)

/*
 * Memory configuration
 */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE		0x20000000	/* 512 Mb */

#define CONFIG_SYS_INIT_SP_ADDR		\
	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
#define CONFIG_SYS_LOAD_ADDR		0x82000000

/*
 * NAND Flash configuration
 */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_NAND_BASE		(ARC_FPGA_PERIPHERAL_BASE + 0x16000)
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/*
 * UART configuration
 *
 * CONFIG_CONS_INDEX = 1 - Debug UART
 * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
 */
#define CONFIG_CONS_INDEX		4
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#if (CONFIG_CONS_INDEX == 1)
	/* Debug UART */
#	define CONFIG_SYS_NS16550_CLK		33333000
#else
	/* FPGA UARTs use different clock */
#	define CONFIG_SYS_NS16550_CLK		33333333
#endif
#define CONFIG_SYS_NS16550_COM1		(ARC_APB_PERIPHERAL_BASE + 0x5000)
#define CONFIG_SYS_NS16550_COM2		(ARC_FPGA_PERIPHERAL_BASE + 0x20000)
#define CONFIG_SYS_NS16550_COM3		(ARC_FPGA_PERIPHERAL_BASE + 0x21000)
#define CONFIG_SYS_NS16550_COM4		(ARC_FPGA_PERIPHERAL_BASE + 0x22000)
#define CONFIG_SYS_NS16550_MEM32

#define CONFIG_BAUDRATE			115200
/*
 * I2C configuration
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DW
#define CONFIG_I2C_ENV_EEPROM_BUS	2
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SLAVE		0
#define CONFIG_SYS_I2C_SLAVE1		0
#define CONFIG_SYS_I2C_SLAVE2		0
#define CONFIG_SYS_I2C_BASE		0xE001D000
#define CONFIG_SYS_I2C_BASE1		0xE001E000
#define CONFIG_SYS_I2C_BASE2		0xE001F000
#define CONFIG_SYS_I2C_BUS_MAX		3
#define IC_CLK				50

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xA8 >> 1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	64

/*
 * SD/MMC configuration
 */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_DOS_PARTITION

/*
 * Ethernet PHY configuration
 */
#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE

/*
 * Ethernet configuration
 */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_AUTONEG
#define CONFIG_NET_MULTI

/*
 * Command line configuration
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_RARP

#define CONFIG_OF_LIBFDT

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		16

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
#define CONFIG_ENV_OFFSET		0

/*
 * Environment configuration
 */
#define CONFIG_BOOTDELAY		3
#define CONFIG_BOOTFILE			"uImage"
#define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR

/*
 * Console configuration
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"AXS# "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)

/*
 * Misc utility configuration
 */
#define CONFIG_BOUNCE_BUFFER

#endif /* _CONFIG_AXS101_H_ */
Commit	Line	Data
a7069ddf AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_AXS101_H_
	8	#define _CONFIG_AXS101_H_
	9
	10	/*
	11	* CPU configuration
	12	*/
a7069ddf AB	13	#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
a7069ddf AB	14
a7069ddf AB	15	#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
	16	#define ARC_APB_PERIPHERAL_BASE 0xF0000000
	17	#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
	18	#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
	19
	20	/*
	21	* Memory configuration
	22	*/
a7069ddf AB	23	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	24
	25	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	26	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
0cdd7620	27	#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */
a7069ddf AB	28
	29	#define CONFIG_SYS_INIT_SP_ADDR \
	30	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
	31
	32	#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
	33	#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
	34	#define CONFIG_SYS_LOAD_ADDR 0x82000000
	35
	36	/*
	37	* NAND Flash configuration
	38	*/
	39	#define CONFIG_SYS_NO_FLASH
	40	#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
	41	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	42
	43	/*
	44	* UART configuration
	45	*
	46	* CONFIG_CONS_INDEX = 1 - Debug UART
	47	* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
	48	*/
	49	#define CONFIG_CONS_INDEX 4
	50	#define CONFIG_SYS_NS16550
	51	#define CONFIG_SYS_NS16550_SERIAL
	52	#define CONFIG_SYS_NS16550_REG_SIZE -4
	53	#if (CONFIG_CONS_INDEX == 1)
	54	/* Debug UART */
	55	# define CONFIG_SYS_NS16550_CLK 33333000
	56	#else
	57	/* FPGA UARTs use different clock */
	58	# define CONFIG_SYS_NS16550_CLK 33333333
	59	#endif
	60	#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
	61	#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
	62	#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
	63	#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
	64	#define CONFIG_SYS_NS16550_MEM32
	65
	66	#define CONFIG_BAUDRATE 115200
	67	/*
	68	* I2C configuration
	69	*/
678398b1 SR	70	#define CONFIG_SYS_I2C
678398b1 SR	71	#define CONFIG_SYS_I2C_DW
a7069ddf AB	72	#define CONFIG_I2C_ENV_EEPROM_BUS 2
a7069ddf AB	73	#define CONFIG_SYS_I2C_SPEED 100000
678398b1 SR	74	#define CONFIG_SYS_I2C_SPEED1 100000
678398b1 SR	75	#define CONFIG_SYS_I2C_SPEED2 100000
a7069ddf	76	#define CONFIG_SYS_I2C_SLAVE 0
678398b1 SR	77	#define CONFIG_SYS_I2C_SLAVE1 0
678398b1 SR	78	#define CONFIG_SYS_I2C_SLAVE2 0
a7069ddf AB	79	#define CONFIG_SYS_I2C_BASE 0xE001D000
	80	#define CONFIG_SYS_I2C_BASE1 0xE001E000
	81	#define CONFIG_SYS_I2C_BASE2 0xE001F000
	82	#define CONFIG_SYS_I2C_BUS_MAX 3
	83	#define IC_CLK 50
	84
	85	/*
	86	* EEPROM configuration
	87	*/
	88	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	89	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
	90	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	91	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
	92	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
6bfa4420	93	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64
a7069ddf AB	94
	95	/*
	96	* SD/MMC configuration
	97	*/
	98	#define CONFIG_MMC
	99	#define CONFIG_GENERIC_MMC
	100	#define CONFIG_DWMMC
	101	#define CONFIG_DOS_PARTITION
	102
	103	/*
	104	* Ethernet PHY configuration
	105	*/
	106	#define CONFIG_PHYLIB
	107	#define CONFIG_MII
	108	#define CONFIG_PHY_GIGE
	109
	110	/*
	111	* Ethernet configuration
	112	*/
	113	#define CONFIG_DESIGNWARE_ETH
	114	#define CONFIG_DW_AUTONEG
a7069ddf AB	115	#define CONFIG_NET_MULTI
	116
	117	/*
	118	* Command line configuration
	119	*/
	120	#include <config_cmd_default.h>
	121
	122	#define CONFIG_CMD_DHCP
	123	#define CONFIG_CMD_EEPROM
	124	#define CONFIG_CMD_ELF
	125	#define CONFIG_CMD_FAT
	126	#define CONFIG_CMD_I2C
	127	#define CONFIG_CMD_MMC
	128	#define CONFIG_CMD_NAND
	129	#define CONFIG_CMD_PING
	130	#define CONFIG_CMD_RARP
	131
	132	#define CONFIG_OF_LIBFDT
	133
	134	#define CONFIG_AUTO_COMPLETE
	135	#define CONFIG_SYS_MAXARGS 16
	136
	137	/*
	138	* Environment settings
	139	*/
	140	#define CONFIG_ENV_IS_IN_EEPROM
	141	#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
	142	#define CONFIG_ENV_OFFSET 0
	143
	144	/*
	145	* Environment configuration
	146	*/
	147	#define CONFIG_BOOTDELAY 3
	148	#define CONFIG_BOOTFILE "uImage"
	149	#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
	150	#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
	151
	152	/*
	153	* Console configuration
	154	*/
	155	#define CONFIG_SYS_LONGHELP
c42eb7f2	156	#define CONFIG_SYS_PROMPT "AXS# "
a7069ddf AB	157	#define CONFIG_SYS_CBSIZE 256
	158	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	159	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	160	sizeof(CONFIG_SYS_PROMPT) + 16)
	161
	162	/*
	163	* Misc utility configuration
	164	*/
	165	#define CONFIG_BOUNCE_BUFFER
	166
	167	#endif /* _CONFIG_AXS101_H_ */