[people/ms/u-boot.git] / include / configs / bubinga.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		bubinga
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */

#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM

/*
!-------------------------------------------------------------------------------
! Defines for entry options.
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
!       are plugged in the board will be utilized as non-ECC DIMMs.
!-------------------------------------------------------------------------------
*/
#define        AUTO_MEMORY_CONFIG
#define        DIMM_READ_ADDR 0xAB
#define        DIMM_WRITE_ADDR 0xAA

/*
!-------------------------------------------------------------------------------
! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
! assuming a 33MHz input clock to the 405EP from the C9531.
!-------------------------------------------------------------------------------
*/
#define PLLMR0_DEFAULT   PLLMR0_266_133_66
#define PLLMR1_DEFAULT   PLLMR1_266_133_66

#endif
/*----------------------------------------------------------------------------*/

/*
 * Define here the location of the environment variables (FLASH or NVRAM).
 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 *       supported for backward compatibility.
 */
#if 1
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_PPC						\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fff80000\0"					\
	"ramdisk_addr=fff90000\0"					\
	""

#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/

#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP

#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */

/*
 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD       691200

/*-----------------------------------------------------------------------
 * I2C stuff
 *-----------------------------------------------------------------------
 */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/

#define CFG_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */

#if defined(CONFIG_CMD_EEPROM)
#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
#endif

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
#define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * External peripheral base address
 *-----------------------------------------------------------------------
 */
#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
#define	CFG_IR_REG_BASE_ADDR	0xF0200000
#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 */
#define CFG_SRAM_BASE		0xFFF00000
#define CFG_FLASH_BASE		0xFFF80000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_ADDR0         0x5555
#define CFG_FLASH_ADDR1         0x2aaa
#define CFG_FLASH_WORD_SIZE     unsigned char

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/

#ifdef CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash/SRAM) initialization                                    */
#define CFG_EBC_PB0AP           0x04006000
#define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
#define CFG_EBC_PB1AP           0x04041000
#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 2 (not used) initialization                                      */
#define CFG_EBC_PB2AP           0x00000000
#define CFG_EBC_PB2CR           0x00000000

/* Memory Bank 2 (not used) initialization                                      */
#define CFG_EBC_PB3AP           0x00000000
#define CFG_EBC_PB3CR           0x00000000

/* Memory Bank 4 (FPGA regs) initialization                                     */
#define CFG_EBC_PB4AP           0x01815000
#define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS      0x55

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]     - External Bus Controller BLAST output
 * GPIO0[1-9]   - Instruction trace outputs
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CFG_GPIO0_OSRH          0x55555555
#define CFG_GPIO0_OSRL          0x40000110
#define CFG_GPIO0_ISR1H         0x00000000
#define CFG_GPIO0_ISR1L         0x15555445
#define CFG_GPIO0_TSRH          0x00000000
#define CFG_GPIO0_TSRL          0x00000000
#define CFG_GPIO0_TCR           0xFFFF8014

/*-----------------------------------------------------------------------
 * Some BUBINGA stuff...
 */
#define NVRAM_BASE      0xF0000000
#define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
#define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
#define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
#define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/

#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */

#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
#define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
#define FPGA_REG1_CLOCK_BIT_SHIFT  4
#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */

#endif	/* __CONFIG_H */
Commit	Line	Data
46578cc0	1	/*
8a316c9b	2	* (C) Copyright 2000-2005
46578cc0 SR	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
46578cc0 SR	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
8a316c9b	38	#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
46578cc0	39
490f2040 SR	40	/*
	41	* Include common defines/options for all AMCC eval boards
	42	*/
	43	#define CONFIG_HOSTNAME bubinga
	44	#include "amcc-common.h"
	45
c837dcb1	46	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
46578cc0 SR	47
	48	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	49
	50	#define CONFIG_NO_SERIAL_EEPROM
	51	/#undef CONFIG_NO_SERIAL_EEPROM/
	52	/----------------------------------------------------------------------------/
46578cc0 SR	53	#ifdef CONFIG_NO_SERIAL_EEPROM
	54
	55	/*
	56	!-------------------------------------------------------------------------------
	57	! Defines for entry options.
	58	! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
	59	! are plugged in the board will be utilized as non-ECC DIMMs.
	60	!-------------------------------------------------------------------------------
	61	*/
	62	#define AUTO_MEMORY_CONFIG
	63	#define DIMM_READ_ADDR 0xAB
	64	#define DIMM_WRITE_ADDR 0xAA
	65
	66	/*
	67	!-------------------------------------------------------------------------------
	68	! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
	69	! assuming a 33MHz input clock to the 405EP from the C9531.
	70	!-------------------------------------------------------------------------------
	71	*/
	72	#define PLLMR0_DEFAULT PLLMR0_266_133_66
	73	#define PLLMR1_DEFAULT PLLMR1_266_133_66
	74
	75	#endif
	76	/----------------------------------------------------------------------------/
46578cc0	77
8a316c9b SR	78	/*
	79	* Define here the location of the environment variables (FLASH or NVRAM).
	80	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	81	* supported for backward compatibility.
	82	*/
46578cc0	83	#if 1
5a1aceb0	84	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
46578cc0	85	#else
9314cee6	86	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
46578cc0 SR	87	#endif
46578cc0 SR	88
490f2040 SR	89	/*
	90	* Default environment variables
	91	*/
8a316c9b	92	#define CONFIG_EXTRA_ENV_SETTINGS \
490f2040 SR	93	CONFIG_AMCC_DEF_ENV \
	94	CONFIG_AMCC_DEF_ENV_PPC \
	95	CONFIG_AMCC_DEF_ENV_NOR_UPD \
8a316c9b SR	96	"kernel_addr=fff80000\0" \
8a316c9b SR	97	"ramdisk_addr=fff90000\0" \
8a316c9b	98	""
8a316c9b	99
46578cc0	100	#define CONFIG_PHY_ADDR 1 /* PHY address */
a00eccfe	101	#define CONFIG_HAS_ETH0
9e00589b SR	102	#define CONFIG_HAS_ETH1
9e00589b SR	103	#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
1e25f957	104
46578cc0 SR	105	#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
46578cc0 SR	106
ba2351f9	107	/*
490f2040	108	* Commands additional to the ones defined in amcc-common.h
ba2351f9	109	*/
ba2351f9	110	#define CONFIG_CMD_DATE
ba2351f9	111	#define CONFIG_CMD_PCI
ba2351f9 JL	112	#define CONFIG_CMD_SDRAM
	113	#define CONFIG_CMD_SNTP
	114
46578cc0 SR	115	#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
46578cc0 SR	116
46578cc0 SR	117	/*
	118	* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	119	* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
	120	* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
	121	* The Linux BASE_BAUD define should match this configuration.
	122	* baseBaud = cpuClock/(uartDivisor*16)
	123	* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
	124	* set Linux BASE_BAUD to 403200.
	125	*/
8a316c9b	126	#undef CONFIG_SERIAL_SOFTWARE_FIFO
46578cc0 SR	127	#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
	128	#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	129	#define CFG_BASE_BAUD 691200
	130
8a316c9b SR	131	/*-----------------------------------------------------------------------
	132	* I2C stuff
	133	*-----------------------------------------------------------------------
	134	*/
46578cc0	135	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
46578cc0	136
b828dda6 SR	137	#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
	138	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
	139
ba2351f9	140	#if defined(CONFIG_CMD_EEPROM)
b828dda6 SR	141	#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
	142	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	143	#endif
	144
46578cc0 SR	145	/*-----------------------------------------------------------------------
	146	* PCI stuff
	147	*-----------------------------------------------------------------------
	148	*/
	149	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	150	#define PCI_HOST_FORCE 1 /* configure as pci host */
	151	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	152
	153	#define CONFIG_PCI /* include pci support */
	154	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	155	#define CONFIG_PCI_PNP /* do pci plug-and-play */
8bde7f77	156	/* resource configuration */
b828dda6	157	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
46578cc0	158
8a316c9b SR	159	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
8a316c9b SR	160	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
b828dda6	161	#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
46578cc0 SR	162	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	163	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	164	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	165	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	166	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	167	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	168
	169	/*-----------------------------------------------------------------------
	170	* External peripheral base address
	171	*-----------------------------------------------------------------------
	172	*/
46578cc0 SR	173	#define CFG_KEY_REG_BASE_ADDR 0xF0100000
	174	#define CFG_IR_REG_BASE_ADDR 0xF0200000
	175	#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
	176
	177	/*-----------------------------------------------------------------------
	178	* Start addresses for the final memory configuration
	179	* (Set up by the startup code)
46578cc0	180	*/
46578cc0 SR	181	#define CFG_SRAM_BASE 0xFFF00000
46578cc0 SR	182	#define CFG_FLASH_BASE 0xFFF80000
8a316c9b	183
46578cc0 SR	184	/*-----------------------------------------------------------------------
	185	* FLASH organization
	186	*/
	187	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	188	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	189
	190	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	191	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	192
8a316c9b SR	193	#define CFG_FLASH_ADDR0 0x5555
	194	#define CFG_FLASH_ADDR1 0x2aaa
	195	#define CFG_FLASH_WORD_SIZE unsigned char
	196
5a1aceb0	197	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	198	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	199	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
	200	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
8a316c9b SR	201
8a316c9b SR	202	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	203	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	204	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	205	#endif /* CONFIG_ENV_IS_IN_FLASH */
8a316c9b	206
46578cc0 SR	207	/*-----------------------------------------------------------------------
	208	* NVRAM organization
	209	*/
	210	#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
	211	#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
	212
9314cee6	213	#ifdef CONFIG_ENV_IS_IN_NVRAM
0e8d1586 JCPV	214	#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
	215	#define CONFIG_ENV_ADDR \
	216	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
46578cc0	217	#endif
46578cc0 SR	218
	219	/*
	220	* Init Memory Controller:
	221	*
	222	* BR0/1 and OR0/1 (FLASH)
	223	*/
	224
	225	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
	226	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	227
46578cc0 SR	228	/*-----------------------------------------------------------------------
	229	* Definitions for initial stack pointer and data area (in data cache)
	230	*/
	231	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	232	#define CFG_TEMP_STACK_OCM 1
	233
	234	/* On Chip Memory location */
	235	#define CFG_OCM_DATA_ADDR 0xF8000000
	236	#define CFG_OCM_DATA_SIZE 0x1000
	237	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	238	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	239
	240	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	241	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	242	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	243
	244	/*-----------------------------------------------------------------------
	245	* External Bus Controller (EBC) Setup
	246	*/
	247
	248	/* Memory Bank 0 (Flash/SRAM) initialization */
	249	#define CFG_EBC_PB0AP 0x04006000
	250	#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
	251
	252	/* Memory Bank 1 (NVRAM/RTC) initialization */
	253	#define CFG_EBC_PB1AP 0x04041000
	254	#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	255
	256	/* Memory Bank 2 (not used) initialization */
	257	#define CFG_EBC_PB2AP 0x00000000
	258	#define CFG_EBC_PB2CR 0x00000000
	259
	260	/* Memory Bank 2 (not used) initialization */
	261	#define CFG_EBC_PB3AP 0x00000000
	262	#define CFG_EBC_PB3CR 0x00000000
	263
	264	/* Memory Bank 4 (FPGA regs) initialization */
	265	#define CFG_EBC_PB4AP 0x01815000
	266	#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
	267
	268	/*-----------------------------------------------------------------------
	269	* Definitions for Serial Presence Detect EEPROM address
	270	* (to get SDRAM settings)
	271	*/
	272	#define SPD_EEPROM_ADDRESS 0x55
	273
	274	/*-----------------------------------------------------------------------
	275	* Definitions for GPIO setup (PPC405EP specific)
	276	*
	277	* GPIO0[0] - External Bus Controller BLAST output
	278	* GPIO0[1-9] - Instruction trace outputs
	279	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	280	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
	281	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	282	* GPIO0[24-27] - UART0 control signal inputs/outputs
	283	* GPIO0[28-29] - UART1 data signal input/output
	284	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	285	*/
	286	#define CFG_GPIO0_OSRH 0x55555555
	287	#define CFG_GPIO0_OSRL 0x40000110
	288	#define CFG_GPIO0_ISR1H 0x00000000
	289	#define CFG_GPIO0_ISR1L 0x15555445
	290	#define CFG_GPIO0_TSRH 0x00000000
	291	#define CFG_GPIO0_TSRL 0x00000000
292	#define CFG_GPIO0_TCR 0xFFFF8014
293
294	/*-----------------------------------------------------------------------
295	* Some BUBINGA stuff...
296	*/
297	#define NVRAM_BASE 0xF0000000
298	#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
299	#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
300	#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
301	#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
302
303	#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
304	#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
305	#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
306	#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
307	#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
308	#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
309
310	#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
311	#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
312	#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
313	#define FPGA_REG1_CLOCK_BIT_SHIFT 4
314	#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
315	#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
316	#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
317	#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
318
46578cc0	319	#endif /* __CONFIG_H */