[people/ms/u-boot.git] / include / configs / bubinga.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */

#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM

/*
!-------------------------------------------------------------------------------
! Defines for entry options.
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
!       are plugged in the board will be utilized as non-ECC DIMMs.
!-------------------------------------------------------------------------------
*/
#define        AUTO_MEMORY_CONFIG
#define        DIMM_READ_ADDR 0xAB
#define        DIMM_WRITE_ADDR 0xAA

/*
!-------------------------------------------------------------------------------
! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
! assuming a 33MHz input clock to the 405EP from the C9531.
!-------------------------------------------------------------------------------
*/
#define PLLMR0_DEFAULT   PLLMR0_266_133_66
#define PLLMR1_DEFAULT   PLLMR1_266_133_66

#endif
/*----------------------------------------------------------------------------*/

/*
 * Define here the location of the environment variables (FLASH or NVRAM).
 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 *       supported for backward compatibility.
 */
#if 1
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=bubinga\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/bubinga/uImage\0"				\
	"kernel_addr=fff80000\0"					\
	"ramdisk_addr=fff90000\0"					\
	"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0"		\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run net_nfs"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
#define CONFIG_NET_MULTI	1
#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/

#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_CACHE	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_ELF	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_REGINFO	| \
				CFG_CMD_SDRAM	| \
				CFG_CMD_SNTP	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

/*
 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * I2C stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */

#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
#endif

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
#define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * External peripheral base address
 *-----------------------------------------------------------------------
 */
#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
#define	CFG_IR_REG_BASE_ADDR	0xF0200000
#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_SRAM_BASE		0xFFF00000
#define CFG_FLASH_BASE		0xFFF80000
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_ADDR0         0x5555
#define CFG_FLASH_ADDR1         0x2aaa
#define CFG_FLASH_WORD_SIZE     unsigned char

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/

#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384	/* For AMCC 405EP CPU			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash/SRAM) initialization                                    */
#define CFG_EBC_PB0AP           0x04006000
#define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
#define CFG_EBC_PB1AP           0x04041000
#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 2 (not used) initialization                                      */
#define CFG_EBC_PB2AP           0x00000000
#define CFG_EBC_PB2CR           0x00000000

/* Memory Bank 2 (not used) initialization                                      */
#define CFG_EBC_PB3AP           0x00000000
#define CFG_EBC_PB3CR           0x00000000

/* Memory Bank 4 (FPGA regs) initialization                                     */
#define CFG_EBC_PB4AP           0x01815000
#define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS      0x55

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]     - External Bus Controller BLAST output
 * GPIO0[1-9]   - Instruction trace outputs
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CFG_GPIO0_OSRH          0x55555555
#define CFG_GPIO0_OSRL          0x40000110
#define CFG_GPIO0_ISR1H         0x00000000
#define CFG_GPIO0_ISR1L         0x15555445
#define CFG_GPIO0_TSRH          0x00000000
#define CFG_GPIO0_TSRL          0x00000000
#define CFG_GPIO0_TCR           0xFFFF8014

/*-----------------------------------------------------------------------
 * Some BUBINGA stuff...
 */
#define NVRAM_BASE      0xF0000000
#define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
#define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
#define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
#define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/

#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */

#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
#define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
#define FPGA_REG1_CLOCK_BIT_SHIFT  4
#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
46578cc0	1	/*
8a316c9b	2	* (C) Copyright 2000-2005
46578cc0 SR	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
46578cc0 SR	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
8a316c9b	38	#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
46578cc0	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
46578cc0 SR	41
	42	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	43
	44	#define CONFIG_NO_SERIAL_EEPROM
	45	/#undef CONFIG_NO_SERIAL_EEPROM/
	46	/----------------------------------------------------------------------------/
46578cc0 SR	47	#ifdef CONFIG_NO_SERIAL_EEPROM
	48
	49	/*
	50	!-------------------------------------------------------------------------------
	51	! Defines for entry options.
	52	! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
	53	! are plugged in the board will be utilized as non-ECC DIMMs.
	54	!-------------------------------------------------------------------------------
	55	*/
	56	#define AUTO_MEMORY_CONFIG
	57	#define DIMM_READ_ADDR 0xAB
	58	#define DIMM_WRITE_ADDR 0xAA
	59
	60	/*
	61	!-------------------------------------------------------------------------------
	62	! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
	63	! assuming a 33MHz input clock to the 405EP from the C9531.
	64	!-------------------------------------------------------------------------------
	65	*/
	66	#define PLLMR0_DEFAULT PLLMR0_266_133_66
	67	#define PLLMR1_DEFAULT PLLMR1_266_133_66
	68
	69	#endif
	70	/----------------------------------------------------------------------------/
46578cc0	71
8a316c9b SR	72	/*
	73	* Define here the location of the environment variables (FLASH or NVRAM).
	74	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	75	* supported for backward compatibility.
	76	*/
46578cc0	77	#if 1
8a316c9b	78	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
46578cc0	79	#else
8a316c9b	80	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
46578cc0 SR	81	#endif
46578cc0 SR	82
8a316c9b SR	83	#define CONFIG_PREBOOT "echo;" \
	84	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	85	"echo"
	86
	87	#undef CONFIG_BOOTARGS
	88
	89	#define CONFIG_EXTRA_ENV_SETTINGS \
	90	"netdev=eth0\0" \
	91	"hostname=bubinga\0" \
	92	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	93	"nfsroot=${serverip}:${rootpath}\0" \
8a316c9b	94	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	95	"addip=setenv bootargs ${bootargs} " \
	96	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	97	":${hostname}:${netdev}:off panic=1\0" \
	98	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
8a316c9b	99	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	100	"bootm ${kernel_addr}\0" \
8a316c9b	101	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	102	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	103	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
8a316c9b SR	104	"bootm\0" \
	105	"rootpath=/opt/eldk/ppc_4xx\0" \
	106	"bootfile=/tftpboot/bubinga/uImage\0" \
	107	"kernel_addr=fff80000\0" \
	108	"ramdisk_addr=fff90000\0" \
	109	"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
	110	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	111	"cp.b 100000 fffc0000 40000;" \
	112	"setenv filesize;saveenv\0" \
	113	"upd=run load;run update\0" \
	114	""
	115	#define CONFIG_BOOTCOMMAND "run net_nfs"
46578cc0 SR	116
46578cc0 SR	117	#if 0
8a316c9b	118	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
46578cc0	119	#else
8a316c9b	120	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
46578cc0 SR	121	#endif
46578cc0 SR	122
8a316c9b SR	123	#define CONFIG_BAUDRATE 115200
8a316c9b SR	124
46578cc0 SR	125	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	126	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	127
	128	#define CONFIG_MII 1 /* MII PHY management */
	129	#define CONFIG_PHY_ADDR 1 /* PHY address */
9e00589b SR	130	#define CONFIG_HAS_ETH1
	131	#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
	132	#define CONFIG_NET_MULTI 1
	133	#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
46578cc0	134
1e25f957 SR	135	#define CONFIG_NETCONSOLE /* include NetConsole support */
1e25f957 SR	136
46578cc0 SR	137	#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
46578cc0 SR	138
46578cc0	139	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
8a316c9b	140	CFG_CMD_ASKENV \| \
b828dda6 SR	141	CFG_CMD_CACHE \| \
	142	CFG_CMD_DATE \| \
	143	CFG_CMD_DHCP \| \
	144	CFG_CMD_EEPROM \| \
	145	CFG_CMD_ELF \| \
	146	CFG_CMD_I2C \| \
46578cc0	147	CFG_CMD_IRQ \| \
b828dda6 SR	148	CFG_CMD_MII \| \
	149	CFG_CMD_NET \| \
	150	CFG_CMD_PCI \| \
	151	CFG_CMD_PING \| \
	152	CFG_CMD_REGINFO \| \
	153	CFG_CMD_SDRAM \| \
8a316c9b	154	CFG_CMD_SNTP )
46578cc0 SR	155
	156	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	157	#include <cmd_confdefs.h>
	158
	159	#undef CONFIG_WATCHDOG /* watchdog disabled */
	160
	161	#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
	162
	163	/*
	164	* Miscellaneous configurable options
	165	*/
	166	#define CFG_LONGHELP /* undef to save memory */
	167	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	168	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	169	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	170	#else
	171	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	172	#endif
	173	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	174	#define CFG_MAXARGS 16 /* max number of command args */
	175	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	176
	177	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	178	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	179
	180	/*
	181	* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	182	* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
	183	* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
	184	* The Linux BASE_BAUD define should match this configuration.
	185	* baseBaud = cpuClock/(uartDivisor*16)
	186	* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
	187	* set Linux BASE_BAUD to 403200.
	188	*/
8a316c9b	189	#undef CONFIG_SERIAL_SOFTWARE_FIFO
46578cc0 SR	190	#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
	191	#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	192	#define CFG_BASE_BAUD 691200
	193
	194	/* The following table includes the supported baudrates */
	195	#define CFG_BAUDRATE_TABLE \
	196	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	197
	198	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	199	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	200
	201	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	202
8a316c9b SR	203	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	204	#define CONFIG_LOOPW 1 /* enable loopw command */
	205	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	206	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	207
8a316c9b SR	208	/*-----------------------------------------------------------------------
	209	* I2C stuff
	210	*-----------------------------------------------------------------------
	211	*/
46578cc0 SR	212	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	213	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	214	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	215	#define CFG_I2C_SLAVE 0x7F
	216
b828dda6 SR	217	#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
	218	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
	219
	220	#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
	221	#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
	222	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	223	#endif
	224
46578cc0 SR	225	/*-----------------------------------------------------------------------
	226	* PCI stuff
	227	*-----------------------------------------------------------------------
	228	*/
	229	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	230	#define PCI_HOST_FORCE 1 /* configure as pci host */
	231	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	232
	233	#define CONFIG_PCI /* include pci support */
	234	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	235	#define CONFIG_PCI_PNP /* do pci plug-and-play */
8bde7f77	236	/* resource configuration */
b828dda6	237	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
46578cc0	238
8a316c9b SR	239	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
8a316c9b SR	240	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
b828dda6	241	#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
46578cc0 SR	242	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	243	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	244	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	245	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	246	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	247	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	248
	249	/*-----------------------------------------------------------------------
	250	* External peripheral base address
	251	*-----------------------------------------------------------------------
	252	*/
46578cc0 SR	253	#define CFG_KEY_REG_BASE_ADDR 0xF0100000
	254	#define CFG_IR_REG_BASE_ADDR 0xF0200000
	255	#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
	256
	257	/*-----------------------------------------------------------------------
	258	* Start addresses for the final memory configuration
	259	* (Set up by the startup code)
	260	* Please note that CFG_SDRAM_BASE _must_ start at 0
	261	*/
	262	#define CFG_SDRAM_BASE 0x00000000
46578cc0 SR	263	#define CFG_SRAM_BASE 0xFFF00000
46578cc0 SR	264	#define CFG_FLASH_BASE 0xFFF80000
8a316c9b	265	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
46578cc0	266	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
8a316c9b	267	#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
46578cc0 SR	268
	269	/*
	270	* For booting Linux, the board info and command line data
	271	* have to be in the first 8 MB of memory, since this is
	272	* the maximum mapped by the Linux kernel during initialization.
	273	*/
	274	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
8a316c9b	275
46578cc0 SR	276	/*-----------------------------------------------------------------------
	277	* FLASH organization
	278	*/
	279	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	280	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	281
	282	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	283	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	284
8a316c9b SR	285	#define CFG_FLASH_ADDR0 0x5555
	286	#define CFG_FLASH_ADDR1 0x2aaa
	287	#define CFG_FLASH_WORD_SIZE unsigned char
	288
46578cc0	289	#ifdef CFG_ENV_IS_IN_FLASH
8a316c9b SR	290	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	291	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	292	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	293
	294	/* Address and size of Redundant Environment Sector */
	295	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	296	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	297	#endif /* CFG_ENV_IS_IN_FLASH */
	298
46578cc0 SR	299	/*-----------------------------------------------------------------------
	300	* NVRAM organization
	301	*/
	302	#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
	303	#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
	304
	305	#ifdef CFG_ENV_IS_IN_NVRAM
b828dda6	306	#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
46578cc0 SR	307	#define CFG_ENV_ADDR \
	308	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
	309	#endif
	310	/*-----------------------------------------------------------------------
	311	* Cache Configuration
	312	*/
0c8721a4	313	#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
46578cc0 SR	314	#define CFG_CACHELINE_SIZE 32 /* ... */
	315	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	316	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	317	#endif
	318
	319	/*
	320	* Init Memory Controller:
	321	*
	322	* BR0/1 and OR0/1 (FLASH)
	323	*/
	324
	325	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
	326	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	327
46578cc0 SR	328	/*-----------------------------------------------------------------------
	329	* Definitions for initial stack pointer and data area (in data cache)
	330	*/
	331	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	332	#define CFG_TEMP_STACK_OCM 1
	333
	334	/* On Chip Memory location */
	335	#define CFG_OCM_DATA_ADDR 0xF8000000
	336	#define CFG_OCM_DATA_SIZE 0x1000
	337	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	338	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	339
	340	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	341	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	342	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	343
	344	/*-----------------------------------------------------------------------
	345	* External Bus Controller (EBC) Setup
	346	*/
	347
	348	/* Memory Bank 0 (Flash/SRAM) initialization */
	349	#define CFG_EBC_PB0AP 0x04006000
	350	#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
	351
	352	/* Memory Bank 1 (NVRAM/RTC) initialization */
	353	#define CFG_EBC_PB1AP 0x04041000
	354	#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	355
	356	/* Memory Bank 2 (not used) initialization */
	357	#define CFG_EBC_PB2AP 0x00000000
	358	#define CFG_EBC_PB2CR 0x00000000
	359
	360	/* Memory Bank 2 (not used) initialization */
	361	#define CFG_EBC_PB3AP 0x00000000
	362	#define CFG_EBC_PB3CR 0x00000000
	363
	364	/* Memory Bank 4 (FPGA regs) initialization */
	365	#define CFG_EBC_PB4AP 0x01815000
	366	#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
	367
	368	/*-----------------------------------------------------------------------
	369	* Definitions for Serial Presence Detect EEPROM address
	370	* (to get SDRAM settings)
	371	*/
	372	#define SPD_EEPROM_ADDRESS 0x55
	373
	374	/*-----------------------------------------------------------------------
	375	* Definitions for GPIO setup (PPC405EP specific)
	376	*
	377	* GPIO0[0] - External Bus Controller BLAST output
	378	* GPIO0[1-9] - Instruction trace outputs
	379	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	380	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
	381	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	382	* GPIO0[24-27] - UART0 control signal inputs/outputs
	383	* GPIO0[28-29] - UART1 data signal input/output
	384	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	385	*/
	386	#define CFG_GPIO0_OSRH 0x55555555
	387	#define CFG_GPIO0_OSRL 0x40000110
	388	#define CFG_GPIO0_ISR1H 0x00000000
	389	#define CFG_GPIO0_ISR1L 0x15555445
	390	#define CFG_GPIO0_TSRH 0x00000000
	391	#define CFG_GPIO0_TSRL 0x00000000
392	#define CFG_GPIO0_TCR 0xFFFF8014
393
394	/*-----------------------------------------------------------------------
395	* Some BUBINGA stuff...
396	*/
397	#define NVRAM_BASE 0xF0000000
398	#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
399	#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
400	#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
401	#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
402
403	#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
404	#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
405	#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
406	#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
407	#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
408	#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
409
410	#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
411	#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
412	#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
413	#define FPGA_REG1_CLOCK_BIT_SHIFT 4
414	#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
415	#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
416	#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
417	#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
418
46578cc0 SR	419	/*
	420	* Internal Definitions
	421	*
	422	* Boot Flags
	423	*/
	424	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	425	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	426
	427	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	428	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	429	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	430	#endif
	431
	432	#endif /* __CONFIG_H */