[people/ms/u-boot.git] / include / configs / cam_enc_4xx.h

/*
 * Copyright (C) 2009 Texas Instruments Incorporated
 *
 * Copyright (C) 2011
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET

/* SoC Configuration */
#define CONFIG_ARM926EJS				/* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
#define CONFIG_SOC_DM365

#define CONFIG_MACH_TYPE	MACH_TYPE_DAVINCI_DM365_EVM

#define CONFIG_HOSTNAME			cam_enc_4xx

#define	CONFIG_BOARD_LATE_INIT
#define CONFIG_CAM_ENC_LED_MASK		0x0fc00000

/* Memory Info */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x80000000
#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* 256 MiB */
#define DDR_4BANKS				/* 4-bank DDR2 (256MB) */
#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/* Serial Driver info: UART0 for console  */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		0x01c20000
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
#define CONFIG_CONS_INDEX		1
#define CONFIG_BAUDRATE			115200

/* Network Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM	0
#define	CONFIG_SYS_EMAC_TI_CLKDIV	0xa9	/* 1MHz */
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#define CONFIG_CMD_MII
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_RESET_PHY_R

/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_I2C_SLAVE		0x10	/* SMBus host address */

/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS		2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K

#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
/* socket has two chipselects, nCE0 gated by address BIT(14) */
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/* SPI support */
#define CONFIG_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK		davinci_clk_get(SPI_PLLDIV)
#define CONFIG_SF_DEFAULT_SPEED		3000000
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_CMD_SF

/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
#define CONFIG_MMC_MBLOCK

/* U-Boot command configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_BDI
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#endif

#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#endif

#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC

/* U-Boot general configuration */
#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
#define CONFIG_SYS_PROMPT	"cam_enc_4xx> "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP

#define CONFIG_MENU
#define CONFIG_MENU_SHOW
#define CONFIG_FIT
#define CONFIG_BOARD_IMG_ADDR_R 0x80000000

#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE			(16 << 10)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x180000
#define CONFIG_ENV_RANGE		0x040000
#define CONFIG_ENV_OFFSET_REDUND	0x1c0000
#undef CONFIG_ENV_IS_IN_FLASH
#endif

#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_CMD_ENV
#define CONFIG_SYS_MMC_ENV_DEV	0
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
#define CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_IS_IN_FLASH
#endif

#define CONFIG_BOOTDELAY	3
/*
 * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
 * Timeout 1 second.
 */
#define CONFIG_AIT_TIMER_TIMEOUT	0x186a00

#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP

/* U-Boot memory configuration */
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
#define CONFIG_SYS_MEMTEST_START	0x80000000	/* physical address */
#define CONFIG_SYS_MEMTEST_END		0x81000000	/* test 16MB RAM */

/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */

#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT			\
	"mtdparts="				\
		"davinci_nand.0:"		\
			"128k(spl),"		\
			"384k(UBLheader),"	\
			"1m(u-boot),"		\
			"512k(env),"		\
			"-(ubi)"

#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POST_MEM_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(BOARDDIR)/u-boot-spl.lds"
#define CONFIG_SPL_STACK		(0x00010000 + 0x7f00)

#define CONFIG_SPL_TEXT_BASE		0x00000020 /*CONFIG_SYS_SRAM_START*/
/* Provide at least 16MB spacing between us and the Linux Kernel image */
#define CONFIG_SPL_PAD_TO		12320
#define CONFIG_SPL_MAX_FOOTPRINT	12288

#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_TEXT_BASE		0x81080000
#endif

#define CONFIG_SYS_NAND_BASE		0x02000000
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					CONFIG_SYS_NAND_PAGE_SIZE)

#define CONFIG_SYS_NAND_ECCPOS		{				\
				24, 25, 26, 27, 28,			\
				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
				59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		0x200
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

/*
 * RBL searches from Block n (n = 1..24)
 * so we can define, how many UBL Headers
 * we can write before the real spl code
 */
#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6

#define CONFIG_SYS_NAND_U_BOOT_DST	0x81080000 /* u-boot TEXT_BASE */
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST

/*
 * Post tests for memory testing
 */
#define CONFIG_POST	CONFIG_SYS_POST_MEMORY
#define _POST_WORD_ADDR	0x0

#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0xa0000
#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE	0x100000

/* for UBL header */
#define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)

#define CONFIG_SYS_DM36x_PLL1_PLLM	0x55
#define CONFIG_SYS_DM36x_PLL1_PREDIV	0x8005
#define CONFIG_SYS_DM36x_PLL2_PLLM	0x09
#define CONFIG_SYS_DM36x_PLL2_PREDIV	0x8000
#define CONFIG_SYS_DM36x_PERI_CLK_CTRL	0x243F04FC
#define CONFIG_SYS_DM36x_PLL1_PLLDIV1	0x801b
#define CONFIG_SYS_DM36x_PLL1_PLLDIV2	0x8001
/* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV3	0x8001
/*
 * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
 * interface clk)
 */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV4	0x8003
/* POST DIV 680/2 = 340Mhz  -> VPSS */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV5	0x8001
/* POST DIV 680/9 = 75.6 Mhz -> VENC */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV6	0x8008
/*
 * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
 * down to 340 Mhz)
 */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV7	0x8000
/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV8	0x8006
/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
#define CONFIG_SYS_DM36x_PLL1_PLLDIV9	0x801b

#define CONFIG_SYS_DM36x_PLL2_PLLDIV1	0x8011
/* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
#define CONFIG_SYS_DM36x_PLL2_PLLDIV2	0x8000
#define CONFIG_SYS_DM36x_PLL2_PLLDIV3	0x8001
/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
#define CONFIG_SYS_DM36x_PLL2_PLLDIV4	0x8014
/* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
#define CONFIG_SYS_DM36x_PLL2_PLLDIV5	0x800f

/*
 * READ LATENCY 7 (CL + 2)
 * CONFIG_PWRDNEN = 1
 * CONFIG_EXT_STRBEN = 1
 */
#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR	(0 \
	| DV_DDR_PHY_EXT_STRBEN \
	| DV_DDR_PHY_PWRDNEN \
	| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))

/*
 * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
 * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
 * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
 * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
 * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
 * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
 * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 */
#define CONFIG_SYS_DM36x_DDR2_SDTIMR	(0 \
	| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
	| (4  << DV_DDR_SDTMR1_RP_SHIFT) \
	| (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
	| (5  << DV_DDR_SDTMR1_WR_SHIFT) \
	| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
	| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
	| (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
	| (2  << DV_DDR_SDTMR1_WTR_SHIFT))

/*
 * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
 * T_XP  = tCKE - 1 = 3 - 2
 * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
 * T_XSRD = txsrd - 1 = 200 - 1
 * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 * T_CKE = tcke - 1     = 3 - 1
 */
#define CONFIG_SYS_DM36x_DDR2_SDTIMR2	(0 \
	| (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
	| (2  << DV_DDR_SDTMR2_XP_SHIFT) \
	| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
	| (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
	| (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
	| (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))

/* PR_OLD_COUNT = 0xfe */
#define CONFIG_SYS_DM36x_DDR2_PBBPR	0x000000FE
/* refresh rate = 0x768 */
#define CONFIG_SYS_DM36x_DDR2_SDRCR	0x00000768

#define CONFIG_SYS_DM36x_DDR2_SDBCR	(0 \
	| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
	| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
	| (5 << DV_DDR_SDCR_CL_SHIFT) \
	| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	\
	| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
	| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
	| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)	\
	| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
	| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
	| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))

#define CONFIG_SYS_DM36x_AWCCR	0xff
#define CONFIG_SYS_DM36x_AB1CR	0x40400204
#define CONFIG_SYS_DM36x_AB2CR	0x04ca2650

/* All Video Inputs */
#define CONFIG_SYS_DM36x_PINMUX0	0x00000000
/*
 * All Video Outputs,
 * GPIO 86, 87 + 90 0x0000f030
 */
#define CONFIG_SYS_DM36x_PINMUX1	0x00530002
#define CONFIG_SYS_DM36x_PINMUX2	0x00001815
/*
 * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
 * GPIO 25 0x60000000
 */
#define CONFIG_SYS_DM36x_PINMUX3	0x9b5affff
/*
 * MMC/SD0 instead of MS, SPI0
 * GPIO 34 0x0000c000
 */
#define CONFIG_SYS_DM36x_PINMUX4	0x00002655

/*
 * Default environment settings
 */

#define DVN4XX_UBOOT_ADDR_R_RAM		0x80000000
/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
#define DVN4XX_UBOOT_ADDR_R_NAND_SPL	0x80000800
/*
 * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
 * CONFIG_SYS_NAND_PAGE_SIZE))
 */
#define DVN4XX_UBOOT_ADDR_R_UBOOT	0x80003800

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0"	\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0"		\
	"load=tftp ${u_boot_addr_r} ${u-boot}\0"			\
	"pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0"		\
	"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};"		\
		"nand write ${u_boot_addr_r} 20000 ${pagesz};"		\
		"nandrbl uboot\0"					\
	"writenand_spl=nandrbl rbl;nand erase 0 3000;"			\
		"nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL)	\
		" 0 3000;nandrbl uboot\0"				\
	"writeuboot=nandrbl uboot;"					\
		"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
		 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE)		\
		";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT)	\
		" " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "	\
		__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"		\
	"update=run load writenand_spl writeuboot\0"			\
	"bootcmd=run net_nfs\0"						\
	"rootpath=/opt/eldk-arm/arm\0"					\
	"mtdids=" MTDIDS_DEFAULT "\0"					\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	"netdev=eth0\0"							\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0"	\
	"addcon=setenv bootargs ${bootargs} console=ttyS0,"		\
		"${baudrate}n8\0"					\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0"	\
	"rootpath=/opt/eldk-arm/arm\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0"		\
	"kernel_addr_r=80600000\0"					\
	"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0"		\
	"ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
		"ubifsload ${kernel_addr_r} boot/uImage\0"		\
	"fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0"		\
	"img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0"		\
	"img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0"		\
	"header_addr=20000\0"						\
	"img_writeheader=nandrbl rbl;"					\
		"nand erase ${header_addr} ${pagesz};"			\
		"nand write ${img_addr_r} ${header_addr} ${pagesz};"	\
		"nandrbl uboot\0"					\
	"img_writespl=nandrbl rbl;nand erase 0 3000;"			\
		"nand write ${img_addr_r} 0 3000;nandrbl uboot\0"	\
	"img_writeuboot=nandrbl uboot;"					\
		"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
		 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE)		\
		";nand write ${img_addr_r} "				\
		__stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "		\
		__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"		\
	"img_writedfenv=ubi part ubi 2048;"				\
		"ubi write ${img_addr_r} default ${filesize}\0"		\
	"img_volume=rootfs1\0"						\
	"img_writeramdisk=ubi part ubi 2048;"				\
		"ubi write ${img_addr_r} ${img_volume} ${filesize}\0"	\
	"load_img=tftp ${fit_addr_r} ${img_file}\0"			\
	"net_nfs=run load_kernel; "					\
		"run nfsargs addip addcon addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"ubi_ubi=run ubi_load_kernel; "					\
		"run ubiargs addip addcon addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"ubiargs=setenv bootargs ubi.mtd=4,2048"			\
		" root=ubi0:${img_volume} rw rootfstype=ubifs\0"	\
	"app_reset=no\0"						\
	"dvn_app_vers=void\0"						\
	"dvn_boot_vers=void\0"						\
	"savenewvers=run savetmpparms restoreparms; saveenv;"		\
		"run restoretmpparms\0"					\
	"savetmpparms=setenv y_ipaddr ${ipaddr};"			\
		"setenv y_netmask ${netmask};"				\
		"setenv y_serverip ${serverip};"			\
		"setenv y_gatewayip ${gatewayip}\0"			\
	"saveparms=setenv x_ipaddr ${ipaddr};"				\
		"setenv x_netmask ${netmask};"				\
		"setenv x_serverip ${serverip};"			\
		"setenv x_gatewayip ${gatewayip}\0"			\
	"restoreparms=setenv ipaddr ${x_ipaddr};"			\
		"setenv netmask ${x_netmask};"				\
		"setenv serverip ${x_serverip};"			\
		"setenv gatewayip ${x_gatewayip}\0"			\
	"restoretmpparms=setenv ipaddr ${y_ipaddr};"			\
		"setenv netmask ${y_netmask};"				\
		"setenv serverip ${y_serverip};"			\
		"setenv gatewayip ${y_gatewayip}\0"			\
	"\0"

/* USB Configuration */
#define CONFIG_USB_DAVINCI
#define CONFIG_MUSB_HCD
#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
				USBPHY_PHY24MHZ)

#define CONFIG_CMD_USB         /* include support for usb cmd */
#define CONFIG_USB_STORAGE     /* MSC class support */
#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */

#undef DAVINCI_DM365EVM
#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
#define PINMUX4_USBDRVBUS_BITSET         0x2000

#endif /* __CONFIG_H */
Commit	Line	Data
4dd83490 HS	1	/*
	2	* Copyright (C) 2009 Texas Instruments Incorporated
	3	*
	4	* Copyright (C) 2011
	5	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
4dd83490 HS	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#define CONFIG_SYS_NO_FLASH /* that is, no NOR flash */
	14	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	15
	16	/* SoC Configuration */
	17	#define CONFIG_ARM926EJS /* arm926ejs CPU */
	18	#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
	19	#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
4dd83490 HS	20	#define CONFIG_SOC_DM365
	21
	22	#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
	23
	24	#define CONFIG_HOSTNAME cam_enc_4xx
	25
8913e6b3	26	#define CONFIG_BOARD_LATE_INIT
4dd83490 HS	27	#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
	28
	29	/* Memory Info */
	30	#define CONFIG_NR_DRAM_BANKS 1
	31	#define PHYS_SDRAM_1 0x80000000
	32	#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
	33	#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
	34	#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
	35	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	36
	37	/* Serial Driver info: UART0 for console */
	38	#define CONFIG_SYS_NS16550
	39	#define CONFIG_SYS_NS16550_SERIAL
	40	#define CONFIG_SYS_NS16550_REG_SIZE -4
	41	#define CONFIG_SYS_NS16550_COM1 0x01c20000
	42	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
4dd83490 HS	43	#define CONFIG_CONS_INDEX 1
	44	#define CONFIG_BAUDRATE 115200
	45
	46	/* Network Configuration */
	47	#define CONFIG_DRIVER_TI_EMAC
	48	#define CONFIG_EMAC_MDIO_PHY_NUM 0
	49	#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
	50	#define CONFIG_MII
4dd83490 HS	51	#define CONFIG_BOOTP_DNS
	52	#define CONFIG_BOOTP_DNS2
	53	#define CONFIG_BOOTP_SEND_HOSTNAME
	54	#define CONFIG_NET_RETRY_COUNT 10
4dd83490 HS	55	#define CONFIG_CMD_MII
	56	#define CONFIG_SYS_DCACHE_OFF
	57	#define CONFIG_RESET_PHY_R
	58
	59	/* I2C */
	60	#define CONFIG_HARD_I2C
	61	#define CONFIG_DRIVER_DAVINCI_I2C
	62	#define CONFIG_SYS_I2C_SPEED 400000
	63	#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
	64
	65	/* NAND: socketed, two chipselects, normally 2 GBytes */
	66	#define CONFIG_NAND_DAVINCI
	67	#define CONFIG_SYS_NAND_CS 2
	68	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	69	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	70	#define CONFIG_SYS_NAND_PAGE_2K
	71
	72	#define CONFIG_SYS_NAND_LARGEPAGE
	73	#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
	74	/* socket has two chipselects, nCE0 gated by address BIT(14) */
	75	#define CONFIG_SYS_MAX_NAND_DEVICE 1
4dd83490 HS	76
	77	/* SPI support */
	78	#define CONFIG_SPI
	79	#define CONFIG_SPI_FLASH
	80	#define CONFIG_SPI_FLASH_STMICRO
	81	#define CONFIG_DAVINCI_SPI
	82	#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
	83	#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
	84	#define CONFIG_SF_DEFAULT_SPEED 3000000
	85	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	86	#define CONFIG_CMD_SF
	87
	88	/* SD/MMC */
	89	#define CONFIG_MMC
	90	#define CONFIG_GENERIC_MMC
	91	#define CONFIG_DAVINCI_MMC
	92	#define CONFIG_MMC_MBLOCK
	93
	94	/* U-Boot command configuration */
	95	#include <config_cmd_default.h>
	96
	97	#define CONFIG_CMD_BDI
	98	#undef CONFIG_CMD_FLASH
	99	#undef CONFIG_CMD_FPGA
	100	#undef CONFIG_CMD_SETGETDCR
	101	#define CONFIG_CMD_ASKENV
	102	#define CONFIG_CMD_CACHE
	103	#define CONFIG_CMD_DHCP
	104	#define CONFIG_CMD_I2C
	105	#define CONFIG_CMD_PING
	106	#define CONFIG_CMD_SAVES
	107
8f5d4687 HM	108	#ifdef CONFIG_CMD_BDI
	109	#define CONFIG_CLOCKS
	110	#endif
	111
4dd83490 HS	112	#ifdef CONFIG_MMC
	113	#define CONFIG_DOS_PARTITION
	114	#define CONFIG_CMD_EXT2
	115	#define CONFIG_CMD_FAT
	116	#define CONFIG_CMD_MMC
	117	#endif
	118
	119	#ifdef CONFIG_NAND_DAVINCI
	120	#define CONFIG_CMD_MTDPARTS
	121	#define CONFIG_MTD_PARTITIONS
	122	#define CONFIG_MTD_DEVICE
	123	#define CONFIG_CMD_NAND
	124	#define CONFIG_CMD_UBI
6be6db58	125	#define CONFIG_CMD_UBIFS
4dd83490	126	#define CONFIG_RBTREE
6be6db58	127	#define CONFIG_LZO
4dd83490 HS	128	#endif
	129
	130	#define CONFIG_CRC32_VERIFY
	131	#define CONFIG_MX_CYCLIC
	132
	133	/* U-Boot general configuration */
4dd83490 HS	134	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
	135	#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
	136	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	137	#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
	138	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	139	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	140	#define CONFIG_SYS_HUSH_PARSER
4dd83490 HS	141	#define CONFIG_SYS_LONGHELP
4dd83490 HS	142
6be6db58 HS	143	#define CONFIG_MENU
	144	#define CONFIG_MENU_SHOW
	145	#define CONFIG_FIT
6be6db58 HS	146	#define CONFIG_BOARD_IMG_ADDR_R 0x80000000
6be6db58 HS	147
4dd83490	148	#ifdef CONFIG_NAND_DAVINCI
6be6db58	149	#define CONFIG_ENV_SIZE (16 << 10)
4dd83490	150	#define CONFIG_ENV_IS_IN_NAND
6be6db58	151	#define CONFIG_ENV_OFFSET 0x180000
24efef90	152	#define CONFIG_ENV_RANGE 0x040000
6be6db58	153	#define CONFIG_ENV_OFFSET_REDUND 0x1c0000
4dd83490 HS	154	#undef CONFIG_ENV_IS_IN_FLASH
	155	#endif
	156
	157	#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
	158	#define CONFIG_CMD_ENV
6be6db58	159	#define CONFIG_SYS_MMC_ENV_DEV 0
4dd83490 HS	160	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
	161	#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
	162	#define CONFIG_ENV_IS_IN_MMC
	163	#undef CONFIG_ENV_IS_IN_FLASH
	164	#endif
	165
	166	#define CONFIG_BOOTDELAY 3
6be6db58 HS	167	/*
	168	* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
	169	* Timeout 1 second.
	170	*/
	171	#define CONFIG_AIT_TIMER_TIMEOUT 0x186a00
4dd83490 HS	172
	173	#define CONFIG_CMDLINE_EDITING
	174	#define CONFIG_VERSION_VARIABLE
	175	#define CONFIG_TIMESTAMP
	176
	177	/* U-Boot memory configuration */
4dd83490 HS	178	#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
	179	#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
	180	#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
	181
	182	/* Linux interfacing */
	183	#define CONFIG_CMDLINE_TAG
	184	#define CONFIG_SETUP_MEMORY_TAGS
	185	#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
	186	#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
	187
	188	#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
6be6db58 HS	189	#define MTDPARTS_DEFAULT \
	190	"mtdparts=" \
	191	"davinci_nand.0:" \
	192	"128k(spl)," \
	193	"384k(UBLheader)," \
	194	"1m(u-boot)," \
	195	"512k(env)," \
	196	"-(ubi)"
	197
	198	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	199	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
4dd83490 HS	200
	201	/* Defines for SPL */
	202	#define CONFIG_SPL
3f7f2414 TR	203	#define CONFIG_SPL_FRAMEWORK
3f7f2414 TR	204	#define CONFIG_SPL_BOARD_INIT
24efef90	205	#define CONFIG_SPL_LIBGENERIC_SUPPORT
4dd83490	206	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	207	#define CONFIG_SPL_NAND_BASE
	208	#define CONFIG_SPL_NAND_DRIVERS
	209	#define CONFIG_SPL_NAND_ECC
4dd83490	210	#define CONFIG_SPL_NAND_SIMPLE
4dd83490 HS	211	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
	212	#define CONFIG_SPL_SERIAL_SUPPORT
	213	#define CONFIG_SPL_POST_MEM_SUPPORT
	214	#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
	215	#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
	216
24efef90	217	#define CONFIG_SPL_TEXT_BASE 0x00000020 /CONFIG_SYS_SRAM_START/
1affd4d4 MY	218	/* Provide at least 16MB spacing between us and the Linux Kernel image */
1affd4d4 MY	219	#define CONFIG_SPL_PAD_TO 12320
e7497891	220	#define CONFIG_SPL_MAX_FOOTPRINT 12288
4dd83490 HS	221
	222	#ifndef CONFIG_SPL_BUILD
	223	#define CONFIG_SYS_TEXT_BASE 0x81080000
	224	#endif
	225
	226	#define CONFIG_SYS_NAND_BASE 0x02000000
	227	#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
	228	CONFIG_SYS_NAND_PAGE_SIZE)
	229
	230	#define CONFIG_SYS_NAND_ECCPOS { \
	231	24, 25, 26, 27, 28, \
	232	29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
	233	39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
	234	49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
	235	59, 60, 61, 62, 63 }
	236	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	237	#define CONFIG_SYS_NAND_ECCSIZE 0x200
	238	#define CONFIG_SYS_NAND_ECCBYTES 10
	239	#define CONFIG_SYS_NAND_OOBSIZE 64
	240	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
4dd83490 HS	241
	242	/*
	243	* RBL searches from Block n (n = 1..24)
	244	* so we can define, how many UBL Headers
	245	* we can write before the real spl code
	246	*/
4dd83490 HS	247	#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
	248
	249	#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
	250	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	251
	252	/*
	253	* Post tests for memory testing
	254	*/
	255	#define CONFIG_POST CONFIG_SYS_POST_MEMORY
	256	#define _POST_WORD_ADDR 0x0
	257
4dd83490 HS	258	#define CONFIG_DISPLAY_BOARDINFO
	259
	260	#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
	261
6be6db58 HS	262	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
6be6db58 HS	263	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
24efef90	264	#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000
4dd83490	265
4dd83490 HS	266	/* for UBL header */
	267	#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
	268
	269	#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
	270	#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
	271	#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
	272	#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
	273	#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
	274	#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
	275	#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
	276	/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
	277	#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
	278	/*
	279	* POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
	280	* interface clk)
	281	*/
	282	#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
	283	/* POST DIV 680/2 = 340Mhz -> VPSS */
	284	#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
	285	/* POST DIV 680/9 = 75.6 Mhz -> VENC */
	286	#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
	287	/*
	288	* POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
	289	* down to 340 Mhz)
	290	*/
	291	#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
	292	/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
	293	#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
	294	/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
	295	#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
	296
	297	#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
	298	/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
	299	#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
	300	#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
	301	/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
	302	#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
	303	/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
	304	#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
	305
	306	/*
	307	* READ LATENCY 7 (CL + 2)
	308	* CONFIG_PWRDNEN = 1
	309	* CONFIG_EXT_STRBEN = 1
	310	*/
	311	#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
	312	\| DV_DDR_PHY_EXT_STRBEN \
	313	\| DV_DDR_PHY_PWRDNEN \
	314	\| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	315
	316	/*
	317	* T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
	318	* T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
	319	* T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
	320	* T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
	321	* T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
	322	* T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
	323	* T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
	324	* T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
	325	*/
	326	#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
	327	\| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
	328	\| (4 << DV_DDR_SDTMR1_RP_SHIFT) \
	329	\| (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
330	\| (5 << DV_DDR_SDTMR1_WR_SHIFT) \
331	\| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
332	\| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
333	\| (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
334	\| (2 << DV_DDR_SDTMR1_WTR_SHIFT))
335
336	/*
337	* T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
338	* T_XP = tCKE - 1 = 3 - 2
339	* T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
340	* T_XSRD = txsrd - 1 = 200 - 1
341	* T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
342	* T_CKE = tcke - 1 = 3 - 1
343	*/
344	#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
345	\| (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
346	\| (2 << DV_DDR_SDTMR2_XP_SHIFT) \
347	\| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
348	\| (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
349	\| (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
350	\| (2 << DV_DDR_SDTMR2_CKE_SHIFT))
351
352	/* PR_OLD_COUNT = 0xfe */
353	#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
354	/* refresh rate = 0x768 */
355	#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
356
357	#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
358	\| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
359	\| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
360	\| (5 << DV_DDR_SDCR_CL_SHIFT) \
361	\| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
362	\| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
363	\| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
364	\| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
365	\| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
366	\| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
367	\| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
368
369	#define CONFIG_SYS_DM36x_AWCCR 0xff
370	#define CONFIG_SYS_DM36x_AB1CR 0x40400204
371	#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
372
373	/* All Video Inputs */
374	#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
375	/*
376	* All Video Outputs,
377	* GPIO 86, 87 + 90 0x0000f030
378	*/
379	#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
380	#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
381	/*
382	* SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
383	* GPIO 25 0x60000000
384	*/
385	#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
386	/*
387	* MMC/SD0 instead of MS, SPI0
388	* GPIO 34 0x0000c000
389	*/
390	#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
391
392	/*
393	* Default environment settings
394	*/
4dd83490 HS	395
	396	#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
	397	/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
	398	#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
	399	/*
	400	* (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
	401	* CONFIG_SYS_NAND_PAGE_SIZE))
	402	*/
	403	#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
	404
	405	#define CONFIG_EXTRA_ENV_SETTINGS \
93ea89f0 MV	406	"u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
93ea89f0 MV	407	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
6be6db58	408	"load=tftp ${u_boot_addr_r} ${u-boot}\0" \
93ea89f0	409	"pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
6be6db58 HS	410	"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
6be6db58 HS	411	"nand write ${u_boot_addr_r} 20000 ${pagesz};" \
4dd83490	412	"nandrbl uboot\0" \
6be6db58	413	"writenand_spl=nandrbl rbl;nand erase 0 3000;" \
93ea89f0	414	"nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
6be6db58	415	" 0 3000;nandrbl uboot\0" \
4dd83490	416	"writeuboot=nandrbl uboot;" \
93ea89f0 MV	417	"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
	418	__stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
	419	";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT) \
	420	" " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
	421	__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
4dd83490	422	"update=run load writenand_spl writeuboot\0" \
6be6db58 HS	423	"bootcmd=run net_nfs\0" \
	424	"rootpath=/opt/eldk-arm/arm\0" \
	425	"mtdids=" MTDIDS_DEFAULT "\0" \
	426	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	427	"netdev=eth0\0" \
	428	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	429	"addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \
	430	"addcon=setenv bootargs ${bootargs} console=ttyS0," \
	431	"${baudrate}n8\0" \
	432	"addip=setenv bootargs ${bootargs} " \
	433	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	434	":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \
4dd83490	435	"rootpath=/opt/eldk-arm/arm\0" \
6be6db58 HS	436	"nfsargs=setenv bootargs root=/dev/nfs rw " \
6be6db58 HS	437	"nfsroot=${serverip}:${rootpath}\0" \
93ea89f0	438	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
6be6db58 HS	439	"kernel_addr_r=80600000\0" \
6be6db58 HS	440	"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
949a7710	441	"ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
6be6db58	442	"ubifsload ${kernel_addr_r} boot/uImage\0" \
93ea89f0 MV	443	"fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
	444	"img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
	445	"img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0" \
6be6db58 HS	446	"header_addr=20000\0" \
	447	"img_writeheader=nandrbl rbl;" \
	448	"nand erase ${header_addr} ${pagesz};" \
	449	"nand write ${img_addr_r} ${header_addr} ${pagesz};" \
	450	"nandrbl uboot\0" \
	451	"img_writespl=nandrbl rbl;nand erase 0 3000;" \
	452	"nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
	453	"img_writeuboot=nandrbl uboot;" \
93ea89f0 MV	454	"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
93ea89f0 MV	455	__stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
6be6db58	456	";nand write ${img_addr_r} " \
93ea89f0 MV	457	__stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
93ea89f0 MV	458	__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
6be6db58 HS	459	"img_writedfenv=ubi part ubi 2048;" \
	460	"ubi write ${img_addr_r} default ${filesize}\0" \
	461	"img_volume=rootfs1\0" \
24efef90	462	"img_writeramdisk=ubi part ubi 2048;" \
6be6db58 HS	463	"ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
	464	"load_img=tftp ${fit_addr_r} ${img_file}\0" \
	465	"net_nfs=run load_kernel; " \
	466	"run nfsargs addip addcon addmtd addmisc;" \
	467	"bootm ${kernel_addr_r}\0" \
	468	"ubi_ubi=run ubi_load_kernel; " \
	469	"run ubiargs addip addcon addmtd addmisc;" \
	470	"bootm ${kernel_addr_r}\0" \
	471	"ubiargs=setenv bootargs ubi.mtd=4,2048" \
	472	" root=ubi0:${img_volume} rw rootfstype=ubifs\0" \
	473	"app_reset=no\0" \
	474	"dvn_app_vers=void\0" \
	475	"dvn_boot_vers=void\0" \
	476	"savenewvers=run savetmpparms restoreparms; saveenv;" \
	477	"run restoretmpparms\0" \
	478	"savetmpparms=setenv y_ipaddr ${ipaddr};" \
	479	"setenv y_netmask ${netmask};" \
	480	"setenv y_serverip ${serverip};" \
	481	"setenv y_gatewayip ${gatewayip}\0" \
	482	"saveparms=setenv x_ipaddr ${ipaddr};" \
	483	"setenv x_netmask ${netmask};" \
	484	"setenv x_serverip ${serverip};" \
	485	"setenv x_gatewayip ${gatewayip}\0" \
	486	"restoreparms=setenv ipaddr ${x_ipaddr};" \
	487	"setenv netmask ${x_netmask};" \
	488	"setenv serverip ${x_serverip};" \
	489	"setenv gatewayip ${x_gatewayip}\0" \
	490	"restoretmpparms=setenv ipaddr ${y_ipaddr};" \
	491	"setenv netmask ${y_netmask};" \
	492	"setenv serverip ${y_serverip};" \
	493	"setenv gatewayip ${y_gatewayip}\0" \
4dd83490 HS	494	"\0"
	495
	496	/* USB Configuration */
	497	#define CONFIG_USB_DAVINCI
	498	#define CONFIG_MUSB_HCD
	499	#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN \| USBPHY_VBDTCTEN \| \
	500	USBPHY_PHY24MHZ)
	501
	502	#define CONFIG_CMD_USB /* include support for usb cmd */
	503	#define CONFIG_USB_STORAGE /* MSC class support */
	504	#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
	505	#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
	506	#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
	507
	508	#undef DAVINCI_DM365EVM
	509	#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
	510	#define PINMUX4_USBDRVBUS_BITSET 0x2000
	511
	512	#endif /* __CONFIG_H */