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e32028a7 NK |
1 | /* |
2 | * Config file for Compulab CM-FX6 board | |
3 | * | |
4 | * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ | |
5 | * | |
6 | * Author: Nikita Kiryanov <nikita@compulab.co.il> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_CM_FX6_H | |
12 | #define __CONFIG_CM_FX6_H | |
13 | ||
e32028a7 NK |
14 | #include "mx6_common.h" |
15 | ||
16 | /* Machine config */ | |
e32028a7 NK |
17 | #define CONFIG_SYS_LITTLE_ENDIAN |
18 | #define CONFIG_MACH_TYPE 4273 | |
e32028a7 | 19 | |
e32028a7 | 20 | /* CMD */ |
63a93093 | 21 | #define CONFIG_CMD_MTDPARTS |
e32028a7 NK |
22 | |
23 | /* MMC */ | |
e32028a7 NK |
24 | #define CONFIG_SYS_FSL_USDHC_NUM 3 |
25 | #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR | |
26 | ||
27 | /* RAM */ | |
28 | #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR | |
29 | #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR | |
30 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
31 | #define CONFIG_NR_DRAM_BANKS 2 | |
32 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
33 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
34 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
35 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
36 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
37 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
38 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
39 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
40 | ||
41 | /* Serial console */ | |
42 | #define CONFIG_MXC_UART | |
43 | #define CONFIG_MXC_UART_BASE UART4_BASE | |
44 | #define CONFIG_BAUDRATE 115200 | |
45 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | |
46 | ||
47 | /* Shell */ | |
e32028a7 NK |
48 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
49 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
50 | ||
51 | /* SPI flash */ | |
e32028a7 NK |
52 | #define CONFIG_SF_DEFAULT_BUS 0 |
53 | #define CONFIG_SF_DEFAULT_CS 0 | |
54 | #define CONFIG_SF_DEFAULT_SPEED 25000000 | |
55 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | |
56 | ||
63a93093 CS |
57 | /* MTD support */ |
58 | #ifndef CONFIG_SPL_BUILD | |
59 | #define CONFIG_FDT_FIXUP_PARTITIONS | |
60 | #define CONFIG_MTD_DEVICE | |
61 | #define CONFIG_MTD_PARTITIONS | |
62 | #define CONFIG_SPI_FLASH_MTD | |
63 | #endif | |
64 | ||
65 | #define MTDIDS_DEFAULT "nor0=spi0.0" | |
66 | #define MTDPARTS_DEFAULT "mtdparts=spi0.0:" \ | |
67 | "768k(uboot)," \ | |
68 | "256k(uboot-environment)," \ | |
69 | "-(reserved)" | |
70 | ||
e32028a7 | 71 | /* Environment */ |
e32028a7 NK |
72 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
73 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
74 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
75 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
76 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
77 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
78 | #define CONFIG_ENV_SIZE (8 * 1024) | |
79 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
80 | ||
81 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
1c2e5292 | 82 | "stdin=serial,usbkbd\0" \ |
deb94d61 NK |
83 | "stdout=serial,vga\0" \ |
84 | "stderr=serial,vga\0" \ | |
85 | "panel=HDMI\0" \ | |
e32028a7 | 86 | "autoload=no\0" \ |
f0f6724f CS |
87 | "uImage=uImage-cm-fx6\0" \ |
88 | "zImage=zImage-cm-fx6\0" \ | |
508a6ede NK |
89 | "kernel=uImage-cm-fx6\0" \ |
90 | "script=boot.scr\0" \ | |
91 | "dtb=cm-fx6.dtb\0" \ | |
92 | "bootm_low=18000000\0" \ | |
e32028a7 NK |
93 | "loadaddr=0x10800000\0" \ |
94 | "fdtaddr=0x11000000\0" \ | |
95 | "console=ttymxc3,115200\0" \ | |
96 | "ethprime=FEC0\0" \ | |
e32028a7 NK |
97 | "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ |
98 | "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ | |
e32028a7 | 99 | "doboot=bootm ${loadaddr}\0" \ |
508a6ede | 100 | "doloadfdt=false\0" \ |
63a93093 CS |
101 | "mtdids=" MTDIDS_DEFAULT "\0" \ |
102 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
f0f6724f | 103 | "setboottypez=setenv kernel ${zImage};" \ |
e32028a7 | 104 | "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ |
508a6ede | 105 | "setenv doloadfdt true;\0" \ |
f0f6724f | 106 | "setboottypem=setenv kernel ${uImage};" \ |
e32028a7 | 107 | "setenv doboot bootm ${loadaddr};" \ |
508a6ede | 108 | "setenv doloadfdt false;\0"\ |
e32028a7 | 109 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ |
206f38f7 | 110 | "sataroot=/dev/sda2 rw rootwait\0" \ |
a6b0652b NK |
111 | "nandroot=/dev/mtdblock4 rw\0" \ |
112 | "nandrootfstype=ubifs\0" \ | |
508a6ede | 113 | "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ |
f0f6724f | 114 | "${video} ${extrabootargs}\0" \ |
508a6ede | 115 | "sataargs=setenv bootargs console=${console} root=${sataroot} " \ |
f0f6724f | 116 | "${video} ${extrabootargs}\0" \ |
a6b0652b NK |
117 | "nandargs=setenv bootargs console=${console} " \ |
118 | "root=${nandroot} " \ | |
119 | "rootfstype=${nandrootfstype} " \ | |
f0f6724f | 120 | "${video} ${extrabootargs}\0" \ |
508a6ede | 121 | "nandboot=if run nandloadkernel; then " \ |
a6b0652b | 122 | "run nandloadfdt;" \ |
508a6ede NK |
123 | "run setboottypem;" \ |
124 | "run storagebootcmd;" \ | |
125 | "run setboottypez;" \ | |
126 | "run storagebootcmd;" \ | |
127 | "fi;\0" \ | |
128 | "run_eboot=echo Starting EBOOT ...; "\ | |
129 | "mmc dev 2 && " \ | |
130 | "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ | |
131 | "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\ | |
132 | "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\ | |
133 | "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \ | |
134 | "bootscript=echo Running bootscript from ${storagetype} ...;" \ | |
135 | "source ${loadaddr};\0" \ | |
136 | "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \ | |
137 | "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ | |
138 | "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ | |
139 | "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ | |
140 | "setupnandboot=setenv storagetype nand;\0" \ | |
141 | "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \ | |
142 | "storagebootcmd=echo Booting from ${storagetype} ...;" \ | |
143 | "run ${storagetype}args; run doboot;\0" \ | |
144 | "trybootk=if run loadkernel; then " \ | |
145 | "if ${doloadfdt}; then " \ | |
146 | "run loadfdt;" \ | |
a6b0652b | 147 | "fi;" \ |
508a6ede NK |
148 | "run storagebootcmd;" \ |
149 | "fi;\0" \ | |
150 | "trybootsmz=if run loadscript; then " \ | |
151 | "run bootscript;" \ | |
206f38f7 | 152 | "fi;" \ |
508a6ede NK |
153 | "run setboottypem;" \ |
154 | "run trybootk;" \ | |
155 | "run setboottypez;" \ | |
156 | "run trybootk;\0" | |
e32028a7 NK |
157 | |
158 | #define CONFIG_BOOTCOMMAND \ | |
508a6ede NK |
159 | "run setupmmcboot;" \ |
160 | "mmc dev ${storagedev};" \ | |
161 | "if mmc rescan; then " \ | |
162 | "run trybootsmz;" \ | |
163 | "fi;" \ | |
164 | "run setupusbboot;" \ | |
165 | "if usb start; then "\ | |
166 | "if run loadscript; then " \ | |
167 | "run bootscript;" \ | |
168 | "fi;" \ | |
169 | "fi;" \ | |
170 | "run setupsataboot;" \ | |
171 | "if sata init; then " \ | |
172 | "run trybootsmz;" \ | |
173 | "fi;" \ | |
174 | "run setupnandboot;" \ | |
175 | "run nandboot;" | |
e32028a7 | 176 | |
63a93093 | 177 | #define CONFIG_PREBOOT "usb start;sf probe" |
1c2e5292 | 178 | |
e32028a7 NK |
179 | /* SPI */ |
180 | #define CONFIG_SPI | |
181 | #define CONFIG_MXC_SPI | |
e32028a7 | 182 | |
a6b0652b NK |
183 | /* NAND */ |
184 | #ifndef CONFIG_SPL_BUILD | |
185 | #define CONFIG_CMD_NAND | |
186 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
187 | #define CONFIG_SYS_NAND_MAX_CHIPS 1 | |
188 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
189 | #define CONFIG_NAND_MXS | |
190 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
191 | /* APBH DMA is required for NAND support */ | |
192 | #define CONFIG_APBH_DMA | |
193 | #define CONFIG_APBH_DMA_BURST | |
194 | #define CONFIG_APBH_DMA_BURST8 | |
195 | #endif | |
196 | ||
02b1343e NK |
197 | /* Ethernet */ |
198 | #define CONFIG_FEC_MXC | |
199 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
200 | #define CONFIG_FEC_XCV_TYPE RGMII | |
201 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
202 | #define CONFIG_PHYLIB | |
203 | #define CONFIG_PHY_ATHEROS | |
204 | #define CONFIG_MII | |
205 | #define CONFIG_ETHPRIME "FEC0" | |
206 | #define CONFIG_ARP_TIMEOUT 200UL | |
02b1343e NK |
207 | #define CONFIG_NET_RETRY_COUNT 5 |
208 | ||
0f3effb9 | 209 | /* USB */ |
0f3effb9 NK |
210 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
211 | #define CONFIG_MXC_USB_FLAGS 0 | |
212 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
213 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
1c2e5292 | 214 | #define CONFIG_SYS_STDIO_DEREGISTER |
0f3effb9 | 215 | |
f42b2f60 | 216 | /* I2C */ |
f42b2f60 NK |
217 | #define CONFIG_SYS_I2C |
218 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
219 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
220 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 221 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
f42b2f60 NK |
222 | #define CONFIG_SYS_I2C_SPEED 100000 |
223 | #define CONFIG_SYS_MXC_I2C3_SPEED 400000 | |
224 | ||
225 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
226 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
227 | #define CONFIG_SYS_I2C_EEPROM_BUS 2 | |
228 | ||
206f38f7 NK |
229 | /* SATA */ |
230 | #define CONFIG_CMD_SATA | |
231 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
232 | #define CONFIG_LIBATA | |
233 | #define CONFIG_LBA48 | |
234 | #define CONFIG_DWC_AHSATA | |
235 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
236 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
237 | ||
e32028a7 | 238 | /* Boot */ |
e32028a7 | 239 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
f66113c0 | 240 | #define CONFIG_SERIAL_TAG |
e32028a7 NK |
241 | |
242 | /* misc */ | |
e32028a7 | 243 | #define CONFIG_STACKSIZE (128 * 1024) |
9fbdcf01 | 244 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
e32028a7 | 245 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ |
7d1abb7d | 246 | #define CONFIG_MISC_INIT_R |
e32028a7 NK |
247 | |
248 | /* SPL */ | |
249 | #include "imx6_spl.h" | |
1fdf7c64 | 250 | #undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR |
e32028a7 | 251 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ |
e32028a7 NK |
252 | #define CONFIG_SPL_SPI_SUPPORT |
253 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
254 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) | |
255 | #define CONFIG_SPL_SPI_LOAD | |
256 | ||
deb94d61 NK |
257 | /* Display */ |
258 | #define CONFIG_VIDEO | |
259 | #define CONFIG_VIDEO_IPUV3 | |
260 | #define CONFIG_IPUV3_CLK 260000000 | |
261 | #define CONFIG_IMX_HDMI | |
deb94d61 NK |
262 | #define CONFIG_CFB_CONSOLE |
263 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
264 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
265 | #define CONFIG_CONSOLE_MUX | |
266 | #define CONFIG_VIDEO_SW_CURSOR | |
267 | ||
3a236a35 | 268 | #define CONFIG_SPLASH_SCREEN |
f82eb2fa | 269 | #define CONFIG_SPLASH_SOURCE |
3a236a35 NK |
270 | #define CONFIG_CMD_BMP |
271 | #define CONFIG_VIDEO_BMP_RLE8 | |
272 | ||
8015dde8 NK |
273 | #define CONFIG_VIDEO_LOGO |
274 | #define CONFIG_VIDEO_BMP_LOGO | |
275 | ||
12616531 NK |
276 | /* EEPROM */ |
277 | #define CONFIG_CMD_EEPROM | |
278 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | |
279 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
280 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
281 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
282 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
283 | ||
284 | #define CONFIG_CMD_EEPROM_LAYOUT | |
285 | #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3" | |
286 | ||
e32028a7 | 287 | #endif /* __CONFIG_CM_FX6_H */ |