[people/ms/u-boot.git] / include / configs / cm_fx6.h

/*
 * Config file for Compulab CM-FX6 board
 *
 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
 *
 * Author: Nikita Kiryanov <nikita@compulab.co.il>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_CM_FX6_H
#define __CONFIG_CM_FX6_H

#include "mx6_common.h"

/* Machine config */
#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_MACH_TYPE		4273

/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM	3
#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR

/* RAM */
#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_MEMTEST_START	0x10000000
#define CONFIG_SYS_MEMTEST_END		0x10010000
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* Serial console */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE		UART4_BASE
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/* SPI flash */
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED		25000000
#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)

/* MTD support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SPI_FLASH_MTD
#endif

/* Environment */
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_OFFSET		(768 * 1024)

#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"fdt_addr_r=0x18000000\0" \
	"ramdisk_addr_r=0x13000000\0" \
	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
	"stdin=serial,usbkbd\0" \
	"stdout=serial,vga\0" \
	"stderr=serial,vga\0" \
	"panel=HDMI\0" \
	"autoload=no\0" \
	"uImage=uImage-cm-fx6\0" \
	"zImage=zImage-cm-fx6\0" \
	"kernel=uImage-cm-fx6\0" \
	"script=boot.scr\0" \
	"dtb=cm-fx6.dtb\0" \
	"console=ttymxc3,115200\0" \
	"ethprime=FEC0\0" \
	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
	"doboot=bootm ${kernel_addr_r}\0" \
	"doloadfdt=false\0" \
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	"setboottypez=setenv kernel ${zImage};" \
		"setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \
		"setenv doloadfdt true;\0" \
	"setboottypem=setenv kernel ${uImage};" \
		"setenv doboot bootm ${kernel_addr_r};" \
		"setenv doloadfdt false;\0"\
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"sataroot=/dev/sda2 rw rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
		"${video} ${extrabootargs}\0" \
	"sataargs=setenv bootargs console=${console} root=${sataroot} " \
		"${video} ${extrabootargs}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype} " \
		"${video} ${extrabootargs}\0" \
	"nandboot=if run nandloadkernel; then " \
			"run nandloadfdt;" \
			"run setboottypem;" \
			"run storagebootcmd;" \
			"run setboottypez;" \
			"run storagebootcmd;" \
		"fi;\0" \
	"run_eboot=echo Starting EBOOT ...; "\
		"mmc dev 2 && " \
		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
	"loadscript=load ${storagetype} ${storagedev} ${scriptaddr} ${script};\0"\
	"loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\
	"loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \
	"bootscript=echo Running bootscript from ${storagetype} ...;" \
		   "source ${scriptaddr};\0" \
	"nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \
	"nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \
	"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
	"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
	"setupnandboot=setenv storagetype nand;\0" \
	"setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \
	"storagebootcmd=echo Booting from ${storagetype} ...;" \
			"run ${storagetype}args; run doboot;\0" \
	"trybootk=if run loadkernel; then " \
		"if ${doloadfdt}; then " \
			"run loadfdt;" \
		"fi;" \
		"run storagebootcmd;" \
		"fi;\0" \
	"trybootsmz=if run loadscript; then " \
			"run bootscript;" \
		"fi;" \
		"run setboottypem;" \
		"run trybootk;" \
		"run setboottypez;" \
		"run trybootk;\0"

#define CONFIG_BOOTCOMMAND \
	"run setupmmcboot;" \
	"mmc dev ${storagedev};" \
	"if mmc rescan; then " \
		"run trybootsmz;" \
	"fi;" \
	"run setupusbboot;" \
	"if usb start; then "\
		"if run loadscript; then " \
			"run bootscript;" \
		"fi;" \
	"fi;" \
	"run setupsataboot;" \
	"if sata init; then " \
		"run trybootsmz;" \
	"fi;" \
	"run setupnandboot;" \
	"run nandboot;"

#define CONFIG_PREBOOT		"usb start;sf probe"

/* SPI */
#define CONFIG_SPI
#define CONFIG_MXC_SPI

/* NAND */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_MAX_CHIPS	1
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_MXS
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* APBH DMA is required for NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
#endif

/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR		0
#define CONFIG_FEC_XCV_TYPE		RGMII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_PHY_ATHEROS
#define CONFIG_MII
#define CONFIG_ETHPRIME			"FEC0"
#define CONFIG_ARP_TIMEOUT		200UL
#define CONFIG_NET_RETRY_COUNT		5

/* USB */
#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS		0
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_MXC_I2C3_SPEED	400000

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	2

/* SATA */
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_LBA48
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR

/* Boot */
#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
#define CONFIG_SERIAL_TAG

/* misc */
#define CONFIG_SYS_MALLOC_LEN			(10 * 1024 * 1024)
#define CONFIG_MISC_INIT_R

/* SPL */
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
#define CONFIG_SPL_SPI_LOAD

/* Display */
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IMX_HDMI

#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_VIDEO_BMP_RLE8

#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#endif	/* __CONFIG_CM_FX6_H */
Commit	Line	Data
e32028a7 NK	1	/*
	2	* Config file for Compulab CM-FX6 board
	3	*
	4	* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
	5	*
	6	* Author: Nikita Kiryanov <nikita@compulab.co.il>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#ifndef __CONFIG_CM_FX6_H
	12	#define __CONFIG_CM_FX6_H
	13
e32028a7 NK	14	#include "mx6_common.h"
	15
	16	/* Machine config */
e32028a7 NK	17	#define CONFIG_SYS_LITTLE_ENDIAN
e32028a7 NK	18	#define CONFIG_MACH_TYPE 4273
e32028a7	19
e32028a7	20	/* MMC */
e32028a7 NK	21	#define CONFIG_SYS_FSL_USDHC_NUM 3
	22	#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
	23
	24	/* RAM */
	25	#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
	26	#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
	27	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	28	#define CONFIG_NR_DRAM_BANKS 2
	29	#define CONFIG_SYS_MEMTEST_START 0x10000000
	30	#define CONFIG_SYS_MEMTEST_END 0x10010000
	31	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	32	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	33	#define CONFIG_SYS_INIT_SP_OFFSET \
	34	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	35	#define CONFIG_SYS_INIT_SP_ADDR \
	36	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	37
	38	/* Serial console */
	39	#define CONFIG_MXC_UART
	40	#define CONFIG_MXC_UART_BASE UART4_BASE
e32028a7 NK	41	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
e32028a7 NK	42
e32028a7	43	/* SPI flash */
e32028a7 NK	44	#define CONFIG_SF_DEFAULT_BUS 0
	45	#define CONFIG_SF_DEFAULT_CS 0
	46	#define CONFIG_SF_DEFAULT_SPEED 25000000
	47	#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
	48
63a93093 CS	49	/* MTD support */
63a93093 CS	50	#ifndef CONFIG_SPL_BUILD
63a93093 CS	51	#define CONFIG_MTD_DEVICE
	52	#define CONFIG_MTD_PARTITIONS
	53	#define CONFIG_SPI_FLASH_MTD
	54	#endif
	55
e32028a7	56	/* Environment */
e32028a7 NK	57	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	58	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	59	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	60	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	61	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	62	#define CONFIG_ENV_SIZE (8 * 1024)
	63	#define CONFIG_ENV_OFFSET (768 * 1024)
	64
	65	#define CONFIG_EXTRA_ENV_SETTINGS \
6b79f71c CS	66	"fdt_high=0xffffffff\0" \
	67	"initrd_high=0xffffffff\0" \
	68	"fdt_addr_r=0x18000000\0" \
	69	"ramdisk_addr_r=0x13000000\0" \
	70	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	71	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	72	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
1c2e5292	73	"stdin=serial,usbkbd\0" \
deb94d61 NK	74	"stdout=serial,vga\0" \
	75	"stderr=serial,vga\0" \
	76	"panel=HDMI\0" \
e32028a7	77	"autoload=no\0" \
f0f6724f CS	78	"uImage=uImage-cm-fx6\0" \
f0f6724f CS	79	"zImage=zImage-cm-fx6\0" \
508a6ede NK	80	"kernel=uImage-cm-fx6\0" \
	81	"script=boot.scr\0" \
	82	"dtb=cm-fx6.dtb\0" \
e32028a7 NK	83	"console=ttymxc3,115200\0" \
e32028a7 NK	84	"ethprime=FEC0\0" \
e32028a7 NK	85	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
e32028a7 NK	86	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
6b79f71c	87	"doboot=bootm ${kernel_addr_r}\0" \
508a6ede	88	"doloadfdt=false\0" \
43ede0bc TR	89	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	90	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
f0f6724f	91	"setboottypez=setenv kernel ${zImage};" \
6b79f71c	92	"setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \
508a6ede	93	"setenv doloadfdt true;\0" \
f0f6724f	94	"setboottypem=setenv kernel ${uImage};" \
6b79f71c	95	"setenv doboot bootm ${kernel_addr_r};" \
508a6ede	96	"setenv doloadfdt false;\0"\
e32028a7	97	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
206f38f7	98	"sataroot=/dev/sda2 rw rootwait\0" \
a6b0652b NK	99	"nandroot=/dev/mtdblock4 rw\0" \
a6b0652b NK	100	"nandrootfstype=ubifs\0" \
508a6ede	101	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
f0f6724f	102	"${video} ${extrabootargs}\0" \
508a6ede	103	"sataargs=setenv bootargs console=${console} root=${sataroot} " \
f0f6724f	104	"${video} ${extrabootargs}\0" \
a6b0652b NK	105	"nandargs=setenv bootargs console=${console} " \
	106	"root=${nandroot} " \
	107	"rootfstype=${nandrootfstype} " \
f0f6724f	108	"${video} ${extrabootargs}\0" \
508a6ede	109	"nandboot=if run nandloadkernel; then " \
a6b0652b	110	"run nandloadfdt;" \
508a6ede NK	111	"run setboottypem;" \
	112	"run storagebootcmd;" \
	113	"run setboottypez;" \
	114	"run storagebootcmd;" \
	115	"fi;\0" \
	116	"run_eboot=echo Starting EBOOT ...; "\
	117	"mmc dev 2 && " \
	118	"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
6b79f71c CS	119	"loadscript=load ${storagetype} ${storagedev} ${scriptaddr} ${script};\0"\
	120	"loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\
	121	"loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \
508a6ede	122	"bootscript=echo Running bootscript from ${storagetype} ...;" \
6b79f71c CS	123	"source ${scriptaddr};\0" \
	124	"nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \
	125	"nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \
508a6ede NK	126	"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
	127	"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
	128	"setupnandboot=setenv storagetype nand;\0" \
	129	"setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \
	130	"storagebootcmd=echo Booting from ${storagetype} ...;" \
	131	"run ${storagetype}args; run doboot;\0" \
	132	"trybootk=if run loadkernel; then " \
	133	"if ${doloadfdt}; then " \
	134	"run loadfdt;" \
a6b0652b	135	"fi;" \
508a6ede NK	136	"run storagebootcmd;" \
	137	"fi;\0" \
	138	"trybootsmz=if run loadscript; then " \
	139	"run bootscript;" \
206f38f7	140	"fi;" \
508a6ede NK	141	"run setboottypem;" \
	142	"run trybootk;" \
	143	"run setboottypez;" \
	144	"run trybootk;\0"
e32028a7 NK	145
e32028a7 NK	146	#define CONFIG_BOOTCOMMAND \
508a6ede NK	147	"run setupmmcboot;" \
	148	"mmc dev ${storagedev};" \
	149	"if mmc rescan; then " \
	150	"run trybootsmz;" \
	151	"fi;" \
	152	"run setupusbboot;" \
	153	"if usb start; then "\
	154	"if run loadscript; then " \
	155	"run bootscript;" \
	156	"fi;" \
	157	"fi;" \
	158	"run setupsataboot;" \
	159	"if sata init; then " \
	160	"run trybootsmz;" \
	161	"fi;" \
	162	"run setupnandboot;" \
	163	"run nandboot;"
e32028a7	164
63a93093	165	#define CONFIG_PREBOOT "usb start;sf probe"
1c2e5292	166
e32028a7 NK	167	/* SPI */
	168	#define CONFIG_SPI
	169	#define CONFIG_MXC_SPI
e32028a7	170
a6b0652b NK	171	/* NAND */
a6b0652b NK	172	#ifndef CONFIG_SPL_BUILD
a6b0652b NK	173	#define CONFIG_SYS_NAND_BASE 0x40000000
	174	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	175	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	176	#define CONFIG_NAND_MXS
	177	#define CONFIG_SYS_NAND_ONFI_DETECTION
	178	/* APBH DMA is required for NAND support */
	179	#define CONFIG_APBH_DMA
	180	#define CONFIG_APBH_DMA_BURST
	181	#define CONFIG_APBH_DMA_BURST8
	182	#endif
	183
02b1343e NK	184	/* Ethernet */
	185	#define CONFIG_FEC_MXC
	186	#define CONFIG_FEC_MXC_PHYADDR 0
	187	#define CONFIG_FEC_XCV_TYPE RGMII
	188	#define IMX_FEC_BASE ENET_BASE_ADDR
02b1343e NK	189	#define CONFIG_PHY_ATHEROS
	190	#define CONFIG_MII
	191	#define CONFIG_ETHPRIME "FEC0"
	192	#define CONFIG_ARP_TIMEOUT 200UL
02b1343e NK	193	#define CONFIG_NET_RETRY_COUNT 5
02b1343e NK	194
0f3effb9	195	/* USB */
0f3effb9 NK	196	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	197	#define CONFIG_MXC_USB_FLAGS 0
	198	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	199	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
	200
f42b2f60	201	/* I2C */
f42b2f60 NK	202	#define CONFIG_SYS_I2C
f42b2f60 NK	203	#define CONFIG_SYS_I2C_MXC
03544c66 AA	204	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	205	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	206	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
f42b2f60 NK	207	#define CONFIG_SYS_I2C_SPEED 100000
	208	#define CONFIG_SYS_MXC_I2C3_SPEED 400000
	209
	210	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	211	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	212	#define CONFIG_SYS_I2C_EEPROM_BUS 2
	213
206f38f7	214	/* SATA */
206f38f7	215	#define CONFIG_SYS_SATA_MAX_DEVICE 1
206f38f7	216	#define CONFIG_LBA48
206f38f7 NK	217	#define CONFIG_DWC_AHSATA_PORT_ID 0
	218	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	219
e32028a7	220	/* Boot */
e32028a7	221	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
f66113c0	222	#define CONFIG_SERIAL_TAG
e32028a7 NK	223
e32028a7 NK	224	/* misc */
9fbdcf01	225	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
7d1abb7d	226	#define CONFIG_MISC_INIT_R
e32028a7 NK	227
	228	/* SPL */
	229	#include "imx6_spl.h"
e32028a7 NK	230	#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
	231	#define CONFIG_SPL_SPI_LOAD
	232
deb94d61	233	/* Display */
deb94d61	234	#define CONFIG_VIDEO_IPUV3
deb94d61	235	#define CONFIG_IMX_HDMI
deb94d61	236
3a236a35	237	#define CONFIG_SPLASH_SCREEN
f82eb2fa	238	#define CONFIG_SPLASH_SOURCE
3a236a35 NK	239	#define CONFIG_VIDEO_BMP_RLE8
3a236a35 NK	240
8015dde8 NK	241	#define CONFIG_VIDEO_LOGO
	242	#define CONFIG_VIDEO_BMP_LOGO
	243
12616531	244	/* EEPROM */
12616531 NK	245	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	246	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	247	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	248	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	249	#define CONFIG_SYS_EEPROM_SIZE 256
	250
e32028a7	251	#endif /* __CONFIG_CM_FX6_H */