[people/ms/u-boot.git] / include / configs / cm_t35.h

/*
 * (C) Copyright 2010
 * CompuLab, Ltd.
 * Mike Rapoport <mike@compulab.co.il>
 *
 * Based on omap3_beagle.h
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the CompuLab CM-T35 board
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_CM_T35		1	/* working with CM-T35 */

#define CONFIG_SYS_TEXT_BASE	0x80008000

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT		1
/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
						/* initial data */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyS2,115200n8\0" \
	"mpurate=500\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"CM-T35 # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CS1 is never populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#if defined(CONFIG_CMD_NET)
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CM_T35_SMC911X_BASE	0x2C000000
#define SB_T35_SMC911X_BASE	(CM_T35_SMC911X_BASE + (16 << 20))
#define CONFIG_SMC911X_BASE	CM_T35_SMC911X_BASE
#endif /* (CONFIG_CMD_NET) */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

#endif /* __CONFIG_H */
Commit	Line	Data
36b4e2dd MR	1	/*
	2	* (C) Copyright 2010
	3	* CompuLab, Ltd.
	4	* Mike Rapoport <mike@compulab.co.il>
	5	*
	6	* Based on omap3_beagle.h
	7	* (C) Copyright 2006-2008
	8	* Texas Instruments.
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <x0khasim@ti.com>
	11	*
	12	* Configuration settings for the CompuLab CM-T35 board
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/*
	37	* High Level Configuration Options
	38	*/
	39	#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
	40	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	41	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	42	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	43	#define CONFIG_CM_T35 1 /* working with CM-T35 */
	44
	45	#define CONFIG_SYS_TEXT_BASE 0x80008000
	46
	47	#define CONFIG_SDRC /* The chip has SDRC controller */
	48
	49	#include <asm/arch/cpu.h> /* get chip and board defs */
	50	#include <asm/arch/omap3.h>
	51
	52	/*
	53	* Display CPU and Board information
	54	*/
	55	#define CONFIG_DISPLAY_CPUINFO 1
	56	#define CONFIG_DISPLAY_BOARDINFO 1
	57
	58	/* Clock Defines */
	59	#define V_OSCK 26000000 /* Clock output from T2 */
	60	#define V_SCLK (V_OSCK >> 1)
	61
	62	#undef CONFIG_USE_IRQ /* no support for IRQs */
	63	#define CONFIG_MISC_INIT_R
	64
65	#define CONFIG_OF_LIBFDT 1
66	/*
67	* The early kernel mapping on ARM currently only maps from the base of DRAM
68	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
69	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
70	* so that leaves DRAM base to DRAM base + 0x4000 available.
71	*/
72	#define CONFIG_SYS_BOOTMAPSZ 0x4000
73
74	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
75	#define CONFIG_SETUP_MEMORY_TAGS 1
76	#define CONFIG_INITRD_TAG 1
77	#define CONFIG_REVISION_TAG 1
78
79	/*
80	* Size of malloc() pool
81	*/
82	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
83	/* Sector */
84	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
85	/* initial data */
86
87	/*
88	* Hardware drivers
89	*/
90
91	/*
92	* NS16550 Configuration
93	*/
94	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
95
96	#define CONFIG_SYS_NS16550
97	#define CONFIG_SYS_NS16550_SERIAL
98	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
99	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
100
101	/*
102	* select serial console configuration
103	*/
104	#define CONFIG_CONS_INDEX 3
105	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
106	#define CONFIG_SERIAL3 3 /* UART3 */
107
108	/* allow to overwrite serial and ethaddr */
109	#define CONFIG_ENV_OVERWRITE
110	#define CONFIG_BAUDRATE 115200
111	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
112	115200}
113	#define CONFIG_GENERIC_MMC 1
114	#define CONFIG_MMC 1
115	#define CONFIG_OMAP_HSMMC 1
116	#define CONFIG_DOS_PARTITION 1
117
118	/* DDR - I use Micron DDR */
119	#define CONFIG_OMAP3_MICRON_DDR 1
120
121	/* USB */
122	#define CONFIG_MUSB_UDC 1
123	#define CONFIG_USB_OMAP3 1
124	#define CONFIG_TWL4030_USB 1
125
126	/* USB device configuration */
127	#define CONFIG_USB_DEVICE 1
128	#define CONFIG_USB_TTY 1
129	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
130
131	/* commands to include */
132	#include <config_cmd_default.h>
133
134	#define CONFIG_CMD_CACHE
135	#define CONFIG_CMD_EXT2 /* EXT2 Support */
136	#define CONFIG_CMD_FAT /* FAT support */
137	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
138	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
139	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
140	#define MTDIDS_DEFAULT "nand0=nand"
141	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
142	"1920k(u-boot),128k(u-boot-env),"\
143	"4m(kernel),-(fs)"
144
145	#define CONFIG_CMD_I2C /* I2C serial bus support */
146	#define CONFIG_CMD_MMC /* MMC support */
147	#define CONFIG_CMD_NAND /* NAND support */
148	#define CONFIG_CMD_DHCP
149	#define CONFIG_CMD_PING
150
151	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
152	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
153	#undef CONFIG_CMD_IMLS /* List all found images */
154
155	#define CONFIG_SYS_NO_FLASH
156	#define CONFIG_HARD_I2C 1
157	#define CONFIG_SYS_I2C_SPEED 100000
158	#define CONFIG_SYS_I2C_SLAVE 1
159	#define CONFIG_SYS_I2C_BUS 0
160	#define CONFIG_SYS_I2C_BUS_SELECT 1
161	#define CONFIG_DRIVER_OMAP34XX_I2C 1
162
163	/*
164	* TWL4030
165	*/
166	#define CONFIG_TWL4030_POWER 1
167	#define CONFIG_TWL4030_LED 1
168
169	/*
170	* Board NAND Info.
171	*/
172	#define CONFIG_SYS_NAND_QUIET_TEST 1
173	#define CONFIG_NAND_OMAP_GPMC
174	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
175	/* to access nand */
176	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
177	/* to access nand at */
178	/* CS0 */
179	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
180
181	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
182	/* devices */
183	#define CONFIG_JFFS2_NAND
184	/* nand device jffs2 lives on */
185	#define CONFIG_JFFS2_DEV "nand0"
186	/* start of jffs2 partition */
187	#define CONFIG_JFFS2_PART_OFFSET 0x680000
188	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
189	/* partition */
190
191	/* Environment information */
192	#define CONFIG_BOOTDELAY 10
193
194	#define CONFIG_EXTRA_ENV_SETTINGS \
195	"loadaddr=0x82000000\0" \
196	"usbtty=cdc_acm\0" \
197	"console=ttyS2,115200n8\0" \
198	"mpurate=500\0" \
199	"vram=12M\0" \
200	"dvimode=1024x768MR-16@60\0" \
201	"defaultdisplay=dvi\0" \
202	"mmcdev=0\0" \
203	"mmcroot=/dev/mmcblk0p2 rw\0" \
204	"mmcrootfstype=ext3 rootwait\0" \
205	"nandroot=/dev/mtdblock4 rw\0" \
206	"nandrootfstype=jffs2\0" \
207	"mmcargs=setenv bootargs console=${console} " \
208	"mpurate=${mpurate} " \
209	"vram=${vram} " \
210	"omapfb.mode=dvi:${dvimode} " \
211	"omapfb.debug=y " \
212	"omapdss.def_disp=${defaultdisplay} " \
213	"root=${mmcroot} " \
214	"rootfstype=${mmcrootfstype}\0" \
215	"nandargs=setenv bootargs console=${console} " \
216	"mpurate=${mpurate} " \
217	"vram=${vram} " \
218	"omapfb.mode=dvi:${dvimode} " \
219	"omapfb.debug=y " \
220	"omapdss.def_disp=${defaultdisplay} " \
221	"root=${nandroot} " \
222	"rootfstype=${nandrootfstype}\0" \
223	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
224	"bootscript=echo Running bootscript from mmc ...; " \
225	"source ${loadaddr}\0" \
226	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
227	"mmcboot=echo Booting from mmc ...; " \
228	"run mmcargs; " \
229	"bootm ${loadaddr}\0" \
230	"nandboot=echo Booting from nand ...; " \
231	"run nandargs; " \
232	"nand read ${loadaddr} 280000 400000; " \
233	"bootm ${loadaddr}\0" \
234
235	#define CONFIG_BOOTCOMMAND \
236	"if mmc rescan ${mmcdev}; then " \
237	"if run loadbootscript; then " \
238	"run bootscript; " \
239	"else " \
240	"if run loaduimage; then " \
241	"run mmcboot; " \
242	"else run nandboot; " \
243	"fi; " \
244	"fi; " \
245	"else run nandboot; fi"
246
247	#define CONFIG_AUTO_COMPLETE 1
248	/*
249	* Miscellaneous configurable options
250	*/
251	#define CONFIG_SYS_LONGHELP /* undef to save memory */
252	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
253	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
254	#define CONFIG_SYS_PROMPT "CM-T35 # "
255	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
256	/* Print Buffer Size */
257	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
258	sizeof(CONFIG_SYS_PROMPT) + 16)
259	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
260	/* Boot Argument Buffer Size */
261	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
262
263	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
264	/* works on */
265	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
266	0x01F00000) /* 31MB */
267
268	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
269	/* load address */
270
271	/*
272	* OMAP3 has 12 GP timers, they can be driven by the system clock
273	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
274	* This rate is divided by a local divisor.
275	*/
276	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
277	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
278	#define CONFIG_SYS_HZ 1000
279
280	/*-----------------------------------------------------------------------
281	* Stack sizes
282	*
283	* The stack sizes are set up in start.S using the settings below
284	*/
285	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
286	#ifdef CONFIG_USE_IRQ
287	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
288	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
289	#endif
290
291	/*-----------------------------------------------------------------------
292	* Physical Memory Map
293	*/
294	#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
295	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
296	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
297
298	/* SDRAM Bank Allocation method */
299	#define SDRC_R_B_C 1
300
301	/*-----------------------------------------------------------------------
302	* FLASH and environment organization
303	*/
304
305	/* ** PISMO SUPPORT * */
306
307	/* Configure the PISMO */
308	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
309	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
310
311	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
312
313	#define CONFIG_SYS_FLASH_BASE boot_flash_base
314
315	/* Monitor at start of flash */
316	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
317	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
318
319	#define CONFIG_ENV_IS_IN_NAND 1
320	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
321	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
322
323	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
324	#define CONFIG_ENV_OFFSET boot_flash_off
325	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
326
327	#ifndef __ASSEMBLY__
328	extern unsigned int boot_flash_base;
329	extern volatile unsigned int boot_flash_env_addr;
330	extern unsigned int boot_flash_off;
331	extern unsigned int boot_flash_sec;
332	extern unsigned int boot_flash_type;
333	#endif
334
335	#if defined(CONFIG_CMD_NET)
336	#define CONFIG_NET_MULTI
337	#define CONFIG_SMC911X
338	#define CONFIG_SMC911X_32_BIT
339	#define CM_T35_SMC911X_BASE 0x2C000000
340	#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20))
341	#define CONFIG_SMC911X_BASE CM_T35_SMC911X_BASE
342	#endif /* (CONFIG_CMD_NET) */
343
344	/* additions for new relocation code, must be added to all boards */
345	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
346	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
347	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
348	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
349	CONFIG_SYS_INIT_RAM_SIZE - \
350	GENERATED_GBL_DATA_SIZE)
351
352	#endif /* __CONFIG_H */