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b09bf723 IG |
1 | /* |
2 | * (C) Copyright 2013 CompuLab, Ltd. | |
3 | * Author: Igor Grinberg <grinberg@compulab.co.il> | |
4 | * | |
5 | * Configuration settings for the CompuLab CM-T3517 board | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
3709844f AA |
13 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
14 | ||
b09bf723 IG |
15 | /* |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_OMAP /* in a TI OMAP core */ | |
19 | #define CONFIG_CM_T3517 /* working with CM-T3517 */ | |
20 | #define CONFIG_OMAP_COMMON | |
c6f90e14 NM |
21 | /* Common ARM Erratas */ |
22 | #define CONFIG_ARM_ERRATA_454179 | |
23 | #define CONFIG_ARM_ERRATA_430973 | |
24 | #define CONFIG_ARM_ERRATA_621766 | |
b09bf723 IG |
25 | |
26 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
27 | ||
28 | /* | |
29 | * This is needed for the DMA stuff. | |
30 | * Although the default iss 64, we still define it | |
31 | * to be on the safe side once the default is changed. | |
32 | */ | |
33 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
34 | ||
35 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ | |
36 | ||
37 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 38 | #include <asm/arch/omap.h> |
b09bf723 | 39 | |
f3b44e8b DL |
40 | #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 |
41 | ||
b09bf723 IG |
42 | /* |
43 | * Display CPU and Board information | |
44 | */ | |
45 | #define CONFIG_DISPLAY_CPUINFO | |
46 | #define CONFIG_DISPLAY_BOARDINFO | |
47 | ||
48 | /* Clock Defines */ | |
49 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
50 | #define V_SCLK (V_OSCK >> 1) | |
51 | ||
52 | #define CONFIG_MISC_INIT_R | |
53 | ||
b09bf723 IG |
54 | /* |
55 | * The early kernel mapping on ARM currently only maps from the base of DRAM | |
56 | * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. | |
57 | * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, | |
58 | * so that leaves DRAM base to DRAM base + 0x4000 available. | |
59 | */ | |
60 | #define CONFIG_SYS_BOOTMAPSZ 0x4000 | |
61 | ||
62 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
63 | #define CONFIG_SETUP_MEMORY_TAGS | |
64 | #define CONFIG_INITRD_TAG | |
65 | #define CONFIG_REVISION_TAG | |
66 | #define CONFIG_SERIAL_TAG | |
67 | ||
68 | /* | |
69 | * Size of malloc() pool | |
70 | */ | |
2f6e4bf8 | 71 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
b09bf723 IG |
72 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
73 | ||
74 | /* | |
75 | * Hardware drivers | |
76 | */ | |
77 | ||
78 | /* | |
79 | * NS16550 Configuration | |
80 | */ | |
b09bf723 IG |
81 | #define CONFIG_SYS_NS16550_SERIAL |
82 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
83 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
84 | ||
85 | /* | |
86 | * select serial console configuration | |
87 | */ | |
88 | #define CONFIG_CONS_INDEX 3 | |
89 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
90 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
91 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
92 | ||
93 | /* allow to overwrite serial and ethaddr */ | |
94 | #define CONFIG_ENV_OVERWRITE | |
95 | #define CONFIG_BAUDRATE 115200 | |
96 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
97 | 115200} | |
98 | ||
99 | #define CONFIG_OMAP_GPIO | |
100 | ||
101 | #define CONFIG_GENERIC_MMC | |
102 | #define CONFIG_MMC | |
103 | #define CONFIG_OMAP_HSMMC | |
104 | #define CONFIG_DOS_PARTITION | |
105 | ||
011f5c13 IG |
106 | /* USB */ |
107 | #define CONFIG_USB_MUSB_AM35X | |
108 | ||
109 | #ifndef CONFIG_USB_MUSB_AM35X | |
110 | #define CONFIG_USB_OMAP3 | |
111 | #define CONFIG_USB_EHCI | |
112 | #define CONFIG_USB_EHCI_OMAP | |
113 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 | |
114 | #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 | |
115 | #else /* !CONFIG_USB_MUSB_AM35X */ | |
95de1e2f | 116 | #define CONFIG_USB_MUSB_PIO_ONLY |
011f5c13 IG |
117 | #endif /* CONFIG_USB_MUSB_AM35X */ |
118 | ||
119 | #define CONFIG_USB_STORAGE | |
011f5c13 | 120 | |
b09bf723 | 121 | /* commands to include */ |
b09bf723 IG |
122 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
123 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
124 | #define CONFIG_MTD_PARTITIONS | |
125 | #define MTDIDS_DEFAULT "nand0=nand" | |
126 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
127 | "1920k(u-boot),256k(u-boot-env),"\ | |
128 | "4m(kernel),-(fs)" | |
129 | ||
b09bf723 | 130 | #define CONFIG_CMD_NAND /* NAND support */ |
b09bf723 | 131 | |
b09bf723 IG |
132 | #define CONFIG_SYS_NO_FLASH |
133 | #define CONFIG_SYS_I2C | |
134 | #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 | |
135 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
136 | #define CONFIG_SYS_I2C_OMAP34XX | |
137 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
138 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
139 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 | |
140 | #define CONFIG_I2C_MULTI_BUS | |
141 | ||
142 | /* | |
143 | * Board NAND Info. | |
144 | */ | |
b09bf723 IG |
145 | #define CONFIG_NAND_OMAP_GPMC |
146 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
147 | /* to access nand */ | |
148 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
149 | /* to access nand at */ | |
150 | /* CS0 */ | |
151 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
152 | /* devices */ | |
153 | ||
154 | /* Environment information */ | |
155 | #define CONFIG_BOOTDELAY 3 | |
156 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
157 | ||
158 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
159 | "loadaddr=0x82000000\0" \ | |
160 | "baudrate=115200\0" \ | |
161 | "console=ttyO2,115200n8\0" \ | |
e093d0b2 | 162 | "netretry=yes\0" \ |
b09bf723 IG |
163 | "mpurate=auto\0" \ |
164 | "vram=12M\0" \ | |
165 | "dvimode=1024x768MR-16@60\0" \ | |
166 | "defaultdisplay=dvi\0" \ | |
167 | "mmcdev=0\0" \ | |
168 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
169 | "mmcrootfstype=ext4\0" \ | |
170 | "nandroot=/dev/mtdblock4 rw\0" \ | |
171 | "nandrootfstype=ubifs\0" \ | |
172 | "mmcargs=setenv bootargs console=${console} " \ | |
173 | "mpurate=${mpurate} " \ | |
174 | "vram=${vram} " \ | |
175 | "omapfb.mode=dvi:${dvimode} " \ | |
176 | "omapdss.def_disp=${defaultdisplay} " \ | |
177 | "root=${mmcroot} " \ | |
178 | "rootfstype=${mmcrootfstype}\0" \ | |
179 | "nandargs=setenv bootargs console=${console} " \ | |
180 | "mpurate=${mpurate} " \ | |
181 | "vram=${vram} " \ | |
182 | "omapfb.mode=dvi:${dvimode} " \ | |
183 | "omapdss.def_disp=${defaultdisplay} " \ | |
184 | "root=${nandroot} " \ | |
185 | "rootfstype=${nandrootfstype}\0" \ | |
186 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
187 | "bootscript=echo Running bootscript from mmc ...; " \ | |
188 | "source ${loadaddr}\0" \ | |
189 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
190 | "mmcboot=echo Booting from mmc ...; " \ | |
191 | "run mmcargs; " \ | |
192 | "bootm ${loadaddr}\0" \ | |
193 | "nandboot=echo Booting from nand ...; " \ | |
194 | "run nandargs; " \ | |
195 | "nand read ${loadaddr} 2a0000 400000; " \ | |
196 | "bootm ${loadaddr}\0" \ | |
197 | ||
b09bf723 IG |
198 | #define CONFIG_BOOTCOMMAND \ |
199 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
200 | "if run loadbootscript; then " \ | |
201 | "run bootscript; " \ | |
202 | "else " \ | |
203 | "if run loaduimage; then " \ | |
204 | "run mmcboot; " \ | |
205 | "else run nandboot; " \ | |
206 | "fi; " \ | |
207 | "fi; " \ | |
208 | "else run nandboot; fi" | |
209 | ||
210 | /* | |
211 | * Miscellaneous configurable options | |
212 | */ | |
213 | #define CONFIG_AUTO_COMPLETE | |
214 | #define CONFIG_CMDLINE_EDITING | |
215 | #define CONFIG_TIMESTAMP | |
216 | #define CONFIG_SYS_AUTOLOAD "no" | |
217 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
b09bf723 IG |
218 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
219 | /* Print Buffer Size */ | |
220 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
221 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
222 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
223 | /* Boot Argument Buffer Size */ | |
224 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
225 | ||
226 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) | |
227 | ||
228 | /* | |
229 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
230 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
231 | * This rate is divided by a local divisor. | |
232 | */ | |
233 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
234 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
235 | #define CONFIG_SYS_HZ 1000 | |
236 | ||
237 | /*----------------------------------------------------------------------- | |
238 | * Physical Memory Map | |
239 | */ | |
240 | #define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ | |
241 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
242 | #define CONFIG_SYS_CS0_SIZE (256 << 20) | |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * FLASH and environment organization | |
246 | */ | |
247 | ||
248 | /* **** PISMO SUPPORT *** */ | |
249 | /* Monitor at start of flash */ | |
250 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
251 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ | |
252 | ||
253 | #define CONFIG_ENV_IS_IN_NAND | |
254 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
255 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
256 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
257 | ||
a8a78c74 IG |
258 | #if defined(CONFIG_CMD_NET) |
259 | #define CONFIG_DRIVER_TI_EMAC | |
260 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
261 | #define CONFIG_MII | |
262 | #define CONFIG_SMC911X | |
263 | #define CONFIG_SMC911X_32_BIT | |
264 | #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) | |
e093d0b2 DL |
265 | #define CONFIG_ARP_TIMEOUT 200UL |
266 | #define CONFIG_NET_RETRY_COUNT 5 | |
a8a78c74 IG |
267 | #endif /* CONFIG_CMD_NET */ |
268 | ||
b09bf723 IG |
269 | /* additions for new relocation code, must be added to all boards */ |
270 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
271 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
272 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
273 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
274 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
275 | GENERATED_GBL_DATA_SIZE) | |
276 | ||
277 | /* Status LED */ | |
278 | #define CONFIG_STATUS_LED /* Status LED enabled */ | |
279 | #define CONFIG_BOARD_SPECIFIC_LED | |
280 | #define CONFIG_GPIO_LED | |
281 | #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ | |
282 | #define GREEN_LED_DEV 0 | |
283 | #define STATUS_LED_BIT GREEN_LED_GPIO | |
284 | #define STATUS_LED_STATE STATUS_LED_ON | |
285 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
286 | #define STATUS_LED_BOOT GREEN_LED_DEV | |
287 | ||
288 | /* GPIO banks */ | |
289 | #ifdef CONFIG_STATUS_LED | |
290 | #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ | |
291 | #endif | |
292 | ||
40bbd52a IG |
293 | /* Display Configuration */ |
294 | #define CONFIG_OMAP3_GPIO_2 | |
295 | #define CONFIG_OMAP3_GPIO_5 | |
296 | #define CONFIG_VIDEO_OMAP3 | |
297 | #define LCD_BPP LCD_COLOR16 | |
298 | ||
299 | #define CONFIG_LCD | |
300 | #define CONFIG_SPLASH_SCREEN | |
301 | #define CONFIG_SPLASHIMAGE_GUARD | |
302 | #define CONFIG_CMD_BMP | |
303 | #define CONFIG_BMP_16BPP | |
304 | #define CONFIG_SCF0403_LCD | |
305 | ||
306 | #define CONFIG_OMAP3_SPI | |
307 | ||
b09bf723 | 308 | #endif /* __CONFIG_H */ |