[people/ms/u-boot.git] / include / configs / cm_t3517.h

/*
 * (C) Copyright 2013 CompuLab, Ltd.
 * Author: Igor Grinberg <grinberg@compulab.co.il>
 *
 * Configuration settings for the CompuLab CM-T3517 board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_CM_T3517	/* working with CM-T3517 */

/*
 * This is needed for the DMA stuff.
 * Although the default iss 64, we still define it
 * to be on the safe side once the default is changed.
 */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

#define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* USB */

#ifndef CONFIG_USB_MUSB_AM35X
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
#endif /* CONFIG_USB_MUSB_AM35X */

/* commands to include */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0
#define CONFIG_I2C_MULTI_BUS

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"baudrate=115200\0" \
	"console=ttyO2,115200n8\0" \
	"netretry=yes\0" \
	"mpurate=auto\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"mmcrootfstype=ext4\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define CONFIG_SYS_CS0_SIZE		(256 << 20)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_OFFSET		0x260000
#define CONFIG_ENV_ADDR			0x260000

#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_ARP_TIMEOUT		200UL
#define CONFIG_NET_RETRY_COUNT		5
#endif /* CONFIG_CMD_NET */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */

/* Display Configuration */
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP		LCD_COLOR16

#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#endif /* __CONFIG_H */
Commit	Line	Data
b09bf723 IG	1	/*
	2	* (C) Copyright 2013 CompuLab, Ltd.
	3	* Author: Igor Grinberg <grinberg@compulab.co.il>
	4	*
	5	* Configuration settings for the CompuLab CM-T3517 board
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
b09bf723	16	#define CONFIG_CM_T3517 /* working with CM-T3517 */
b09bf723	17
b09bf723 IG	18	/*
	19	* This is needed for the DMA stuff.
	20	* Although the default iss 64, we still define it
	21	* to be on the safe side once the default is changed.
	22	*/
b09bf723	23
b09bf723	24	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	25	#include <asm/arch/omap.h>
b09bf723	26
f3b44e8b DL	27	#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
f3b44e8b DL	28
b09bf723 IG	29	/* Clock Defines */
	30	#define V_OSCK 26000000 /* Clock output from T2 */
	31	#define V_SCLK (V_OSCK >> 1)
	32
	33	#define CONFIG_MISC_INIT_R
	34
b09bf723 IG	35	/*
	36	* The early kernel mapping on ARM currently only maps from the base of DRAM
	37	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
	38	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
	39	* so that leaves DRAM base to DRAM base + 0x4000 available.
	40	*/
	41	#define CONFIG_SYS_BOOTMAPSZ 0x4000
	42
	43	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	44	#define CONFIG_SETUP_MEMORY_TAGS
	45	#define CONFIG_INITRD_TAG
	46	#define CONFIG_REVISION_TAG
	47	#define CONFIG_SERIAL_TAG
	48
	49	/*
	50	* Size of malloc() pool
	51	*/
2f6e4bf8	52	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
b09bf723 IG	53	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	54
	55	/*
	56	* Hardware drivers
	57	*/
	58
	59	/*
	60	* NS16550 Configuration
	61	*/
b09bf723 IG	62	#define CONFIG_SYS_NS16550_SERIAL
	63	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	64	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	65
	66	/*
	67	* select serial console configuration
	68	*/
	69	#define CONFIG_CONS_INDEX 3
	70	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	71	#define CONFIG_SERIAL3 3 /* UART3 */
b09bf723 IG	72
	73	/* allow to overwrite serial and ethaddr */
	74	#define CONFIG_ENV_OVERWRITE
b09bf723 IG	75	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	76	115200}
	77
011f5c13	78	/* USB */
011f5c13 IG	79
011f5c13 IG	80	#ifndef CONFIG_USB_MUSB_AM35X
011f5c13 IG	81	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
011f5c13 IG	82	#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
011f5c13 IG	83	#endif /* CONFIG_USB_MUSB_AM35X */
011f5c13 IG	84
b09bf723	85	/* commands to include */
b09bf723 IG	86	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
b09bf723 IG	87	#define CONFIG_MTD_PARTITIONS
b09bf723	88
b09bf723	89	#define CONFIG_SYS_I2C
b09bf723 IG	90	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	91	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	92	#define CONFIG_SYS_I2C_EEPROM_BUS 0
	93	#define CONFIG_I2C_MULTI_BUS
	94
	95	/*
	96	* Board NAND Info.
	97	*/
b09bf723 IG	98	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	99	/* to access nand */
	100	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	101	/* to access nand at */
	102	/* CS0 */
	103	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	104	/* devices */
	105
	106	/* Environment information */
b09bf723 IG	107	#define CONFIG_EXTRA_ENV_SETTINGS \
	108	"loadaddr=0x82000000\0" \
	109	"baudrate=115200\0" \
	110	"console=ttyO2,115200n8\0" \
e093d0b2	111	"netretry=yes\0" \
b09bf723 IG	112	"mpurate=auto\0" \
	113	"vram=12M\0" \
	114	"dvimode=1024x768MR-16@60\0" \
	115	"defaultdisplay=dvi\0" \
	116	"mmcdev=0\0" \
	117	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	118	"mmcrootfstype=ext4\0" \
	119	"nandroot=/dev/mtdblock4 rw\0" \
	120	"nandrootfstype=ubifs\0" \
	121	"mmcargs=setenv bootargs console=${console} " \
	122	"mpurate=${mpurate} " \
	123	"vram=${vram} " \
	124	"omapfb.mode=dvi:${dvimode} " \
	125	"omapdss.def_disp=${defaultdisplay} " \
	126	"root=${mmcroot} " \
	127	"rootfstype=${mmcrootfstype}\0" \
	128	"nandargs=setenv bootargs console=${console} " \
	129	"mpurate=${mpurate} " \
	130	"vram=${vram} " \
	131	"omapfb.mode=dvi:${dvimode} " \
	132	"omapdss.def_disp=${defaultdisplay} " \
	133	"root=${nandroot} " \
	134	"rootfstype=${nandrootfstype}\0" \
	135	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	136	"bootscript=echo Running bootscript from mmc ...; " \
	137	"source ${loadaddr}\0" \
	138	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	139	"mmcboot=echo Booting from mmc ...; " \
	140	"run mmcargs; " \
	141	"bootm ${loadaddr}\0" \
	142	"nandboot=echo Booting from nand ...; " \
	143	"run nandargs; " \
	144	"nand read ${loadaddr} 2a0000 400000; " \
	145	"bootm ${loadaddr}\0" \
	146
b09bf723 IG	147	#define CONFIG_BOOTCOMMAND \
	148	"mmc dev ${mmcdev}; if mmc rescan; then " \
	149	"if run loadbootscript; then " \
	150	"run bootscript; " \
	151	"else " \
	152	"if run loaduimage; then " \
	153	"run mmcboot; " \
	154	"else run nandboot; " \
	155	"fi; " \
	156	"fi; " \
	157	"else run nandboot; fi"
	158
	159	/*
	160	* Miscellaneous configurable options
	161	*/
b09bf723 IG	162	#define CONFIG_TIMESTAMP
b09bf723 IG	163	#define CONFIG_SYS_AUTOLOAD "no"
b09bf723	164	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
b09bf723	165	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
b09bf723 IG	166
	167	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	168
	169	/*
	170	* AM3517 has 12 GP timers, they can be driven by the system clock
	171	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	172	* This rate is divided by a local divisor.
	173	*/
	174	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	175	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	176	#define CONFIG_SYS_HZ 1000
	177
	178	/*-----------------------------------------------------------------------
	179	* Physical Memory Map
	180	*/
	181	#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
	182	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	183	#define CONFIG_SYS_CS0_SIZE (256 << 20)
	184
	185	/*-----------------------------------------------------------------------
	186	* FLASH and environment organization
	187	*/
	188
	189	/* ** PISMO SUPPORT * */
	190	/* Monitor at start of flash */
	191	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	192	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	193
7672d9d5 AF	194	#define CONFIG_ENV_OFFSET 0x260000
7672d9d5 AF	195	#define CONFIG_ENV_ADDR 0x260000
b09bf723	196
a8a78c74 IG	197	#if defined(CONFIG_CMD_NET)
	198	#define CONFIG_DRIVER_TI_EMAC
	199	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	200	#define CONFIG_MII
e093d0b2 DL	201	#define CONFIG_ARP_TIMEOUT 200UL
e093d0b2 DL	202	#define CONFIG_NET_RETRY_COUNT 5
a8a78c74 IG	203	#endif /* CONFIG_CMD_NET */
a8a78c74 IG	204
b09bf723 IG	205	/* additions for new relocation code, must be added to all boards */
	206	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	207	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	208	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	209	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	210	CONFIG_SYS_INIT_RAM_SIZE - \
	211	GENERATED_GBL_DATA_SIZE)
	212
	213	/* Status LED */
b09bf723	214	#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
b09bf723	215
40bbd52a	216	/* Display Configuration */
40bbd52a IG	217	#define CONFIG_VIDEO_OMAP3
	218	#define LCD_BPP LCD_COLOR16
	219
40bbd52a IG	220	#define CONFIG_SPLASH_SCREEN
40bbd52a IG	221	#define CONFIG_SPLASHIMAGE_GUARD
40bbd52a IG	222	#define CONFIG_BMP_16BPP
	223	#define CONFIG_SCF0403_LCD
	224
19a90ed6	225	/* EEPROM */
19a90ed6 NK	226	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	227	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	228	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	229	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	230	#define CONFIG_SYS_EEPROM_SIZE 256
	231
b09bf723	232	#endif /* __CONFIG_H */