[people/ms/u-boot.git] / include / configs / cm_t3517.h

/*
 * (C) Copyright 2013 CompuLab, Ltd.
 * Author: Igor Grinberg <grinberg@compulab.co.il>
 *
 * Configuration settings for the CompuLab CM-T3517 board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_CACHELINE_SIZE	64

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP	/* in a TI OMAP core */
#define CONFIG_CM_T3517	/* working with CM-T3517 */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SYS_TEXT_BASE	0x80008000

/*
 * This is needed for the DMA stuff.
 * Although the default iss 64, we still define it
 * to be on the safe side once the default is changed.
 */
#define CONFIG_SYS_CACHELINE_SIZE	64

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

#define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

#define CONFIG_OMAP_GPIO

#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_MUSB_AM35X

#ifndef CONFIG_USB_MUSB_AM35X
#define CONFIG_USB_OMAP3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
#else /* !CONFIG_USB_MUSB_AM35X */
#define CONFIG_USB_MUSB_HOST
#define CONFIG_USB_MUSB_PIO_ONLY
#endif /* CONFIG_USB_MUSB_AM35X */

#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

/* commands to include */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
				"1920k(u-boot),256k(u-boot-env),"\
				"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING


#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0
#define CONFIG_I2C_MULTI_BUS

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_BOOTDELAY		3
#define CONFIG_ZERO_BOOTDELAY_CHECK

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"baudrate=115200\0" \
	"console=ttyO2,115200n8\0" \
	"netretry=yes\0" \
	"mpurate=auto\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"mmcrootfstype=ext4\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_CMD_BOOTZ
#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define CONFIG_SYS_CS0_SIZE		(256 << 20)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
#define CONFIG_ARP_TIMEOUT		200UL
#define CONFIG_NET_RETRY_COUNT		5
#endif /* CONFIG_CMD_NET */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define CONFIG_STATUS_LED		/* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED
#define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */
#define GREEN_LED_DEV			0
#define STATUS_LED_BIT			GREEN_LED_GPIO
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			GREEN_LED_DEV

/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
#endif

/* Display Configuration */
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP		LCD_COLOR16

#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

#define CONFIG_OMAP3_SPI

#endif /* __CONFIG_H */
Commit	Line	Data
b09bf723 IG	1	/*
	2	* (C) Copyright 2013 CompuLab, Ltd.
	3	* Author: Igor Grinberg <grinberg@compulab.co.il>
	4	*
	5	* Configuration settings for the CompuLab CM-T3517 board
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
3709844f AA	13	#define CONFIG_SYS_CACHELINE_SIZE 64
3709844f AA	14
b09bf723 IG	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_OMAP /* in a TI OMAP core */
	19	#define CONFIG_CM_T3517 /* working with CM-T3517 */
	20	#define CONFIG_OMAP_COMMON
c6f90e14 NM	21	/* Common ARM Erratas */
	22	#define CONFIG_ARM_ERRATA_454179
	23	#define CONFIG_ARM_ERRATA_430973
	24	#define CONFIG_ARM_ERRATA_621766
b09bf723 IG	25
	26	#define CONFIG_SYS_TEXT_BASE 0x80008000
	27
	28	/*
	29	* This is needed for the DMA stuff.
	30	* Although the default iss 64, we still define it
	31	* to be on the safe side once the default is changed.
	32	*/
	33	#define CONFIG_SYS_CACHELINE_SIZE 64
	34
	35	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	36
	37	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	38	#include <asm/arch/omap.h>
b09bf723	39
f3b44e8b DL	40	#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
f3b44e8b DL	41
b09bf723 IG	42	/*
	43	* Display CPU and Board information
	44	*/
	45	#define CONFIG_DISPLAY_CPUINFO
	46	#define CONFIG_DISPLAY_BOARDINFO
	47
	48	/* Clock Defines */
	49	#define V_OSCK 26000000 /* Clock output from T2 */
	50	#define V_SCLK (V_OSCK >> 1)
	51
	52	#define CONFIG_MISC_INIT_R
	53
b09bf723 IG	54	/*
	55	* The early kernel mapping on ARM currently only maps from the base of DRAM
	56	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
	57	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
	58	* so that leaves DRAM base to DRAM base + 0x4000 available.
	59	*/
	60	#define CONFIG_SYS_BOOTMAPSZ 0x4000
	61
	62	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	63	#define CONFIG_SETUP_MEMORY_TAGS
	64	#define CONFIG_INITRD_TAG
	65	#define CONFIG_REVISION_TAG
	66	#define CONFIG_SERIAL_TAG
	67
	68	/*
	69	* Size of malloc() pool
	70	*/
2f6e4bf8	71	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
b09bf723 IG	72	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	73
	74	/*
	75	* Hardware drivers
	76	*/
	77
	78	/*
	79	* NS16550 Configuration
	80	*/
b09bf723 IG	81	#define CONFIG_SYS_NS16550_SERIAL
	82	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	83	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	84
	85	/*
	86	* select serial console configuration
	87	*/
	88	#define CONFIG_CONS_INDEX 3
	89	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	90	#define CONFIG_SERIAL3 3 /* UART3 */
	91	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	92
	93	/* allow to overwrite serial and ethaddr */
	94	#define CONFIG_ENV_OVERWRITE
	95	#define CONFIG_BAUDRATE 115200
	96	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	97	115200}
	98
	99	#define CONFIG_OMAP_GPIO
	100
	101	#define CONFIG_GENERIC_MMC
	102	#define CONFIG_MMC
	103	#define CONFIG_OMAP_HSMMC
	104	#define CONFIG_DOS_PARTITION
	105
011f5c13 IG	106	/* USB */
	107	#define CONFIG_USB_MUSB_AM35X
	108
	109	#ifndef CONFIG_USB_MUSB_AM35X
	110	#define CONFIG_USB_OMAP3
	111	#define CONFIG_USB_EHCI
	112	#define CONFIG_USB_EHCI_OMAP
	113	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
	114	#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
	115	#else /* !CONFIG_USB_MUSB_AM35X */
95de1e2f PK	116	#define CONFIG_USB_MUSB_HOST
95de1e2f PK	117	#define CONFIG_USB_MUSB_PIO_ONLY
011f5c13 IG	118	#endif /* CONFIG_USB_MUSB_AM35X */
	119
	120	#define CONFIG_USB_STORAGE
	121	#define CONFIG_CMD_USB
	122
b09bf723	123	/* commands to include */
b09bf723 IG	124	#define CONFIG_CMD_CACHE
	125	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	126	#define CONFIG_CMD_FAT /* FAT support */
	127	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	128	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	129	#define CONFIG_MTD_PARTITIONS
	130	#define MTDIDS_DEFAULT "nand0=nand"
	131	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	132	"1920k(u-boot),256k(u-boot-env),"\
	133	"4m(kernel),-(fs)"
	134
	135	#define CONFIG_CMD_I2C /* I2C serial bus support */
	136	#define CONFIG_CMD_MMC /* MMC support */
	137	#define CONFIG_CMD_NAND /* NAND support */
a8a78c74 IG	138	#define CONFIG_CMD_DHCP
a8a78c74 IG	139	#define CONFIG_CMD_PING
b09bf723	140
b09bf723 IG	141
	142	#define CONFIG_SYS_NO_FLASH
	143	#define CONFIG_SYS_I2C
	144	#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
	145	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	146	#define CONFIG_SYS_I2C_OMAP34XX
	147	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	148	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	149	#define CONFIG_SYS_I2C_EEPROM_BUS 0
	150	#define CONFIG_I2C_MULTI_BUS
	151
	152	/*
	153	* Board NAND Info.
	154	*/
b09bf723 IG	155	#define CONFIG_NAND_OMAP_GPMC
	156	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	157	/* to access nand */
	158	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	159	/* to access nand at */
	160	/* CS0 */
	161	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	162	/* devices */
	163
	164	/* Environment information */
	165	#define CONFIG_BOOTDELAY 3
	166	#define CONFIG_ZERO_BOOTDELAY_CHECK
	167
	168	#define CONFIG_EXTRA_ENV_SETTINGS \
	169	"loadaddr=0x82000000\0" \
	170	"baudrate=115200\0" \
	171	"console=ttyO2,115200n8\0" \
e093d0b2	172	"netretry=yes\0" \
b09bf723 IG	173	"mpurate=auto\0" \
	174	"vram=12M\0" \
	175	"dvimode=1024x768MR-16@60\0" \
	176	"defaultdisplay=dvi\0" \
	177	"mmcdev=0\0" \
	178	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	179	"mmcrootfstype=ext4\0" \
	180	"nandroot=/dev/mtdblock4 rw\0" \
	181	"nandrootfstype=ubifs\0" \
	182	"mmcargs=setenv bootargs console=${console} " \
	183	"mpurate=${mpurate} " \
	184	"vram=${vram} " \
	185	"omapfb.mode=dvi:${dvimode} " \
	186	"omapdss.def_disp=${defaultdisplay} " \
	187	"root=${mmcroot} " \
	188	"rootfstype=${mmcrootfstype}\0" \
	189	"nandargs=setenv bootargs console=${console} " \
	190	"mpurate=${mpurate} " \
	191	"vram=${vram} " \
	192	"omapfb.mode=dvi:${dvimode} " \
	193	"omapdss.def_disp=${defaultdisplay} " \
	194	"root=${nandroot} " \
	195	"rootfstype=${nandrootfstype}\0" \
	196	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	197	"bootscript=echo Running bootscript from mmc ...; " \
	198	"source ${loadaddr}\0" \
	199	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	200	"mmcboot=echo Booting from mmc ...; " \
	201	"run mmcargs; " \
	202	"bootm ${loadaddr}\0" \
	203	"nandboot=echo Booting from nand ...; " \
	204	"run nandargs; " \
	205	"nand read ${loadaddr} 2a0000 400000; " \
	206	"bootm ${loadaddr}\0" \
	207
	208	#define CONFIG_CMD_BOOTZ
	209	#define CONFIG_BOOTCOMMAND \
	210	"mmc dev ${mmcdev}; if mmc rescan; then " \
	211	"if run loadbootscript; then " \
	212	"run bootscript; " \
	213	"else " \
	214	"if run loaduimage; then " \
	215	"run mmcboot; " \
	216	"else run nandboot; " \
	217	"fi; " \
	218	"fi; " \
	219	"else run nandboot; fi"
	220
	221	/*
	222	* Miscellaneous configurable options
	223	*/
	224	#define CONFIG_AUTO_COMPLETE
	225	#define CONFIG_CMDLINE_EDITING
	226	#define CONFIG_TIMESTAMP
	227	#define CONFIG_SYS_AUTOLOAD "no"
	228	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	229	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
b09bf723 IG	230	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	231	/* Print Buffer Size */
	232	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	233	sizeof(CONFIG_SYS_PROMPT) + 16)
	234	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	235	/* Boot Argument Buffer Size */
	236	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	237
	238	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	239
	240	/*
	241	* AM3517 has 12 GP timers, they can be driven by the system clock
	242	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	243	* This rate is divided by a local divisor.
	244	*/
	245	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	246	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	247	#define CONFIG_SYS_HZ 1000
	248
	249	/*-----------------------------------------------------------------------
	250	* Physical Memory Map
	251	*/
	252	#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
	253	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	254	#define CONFIG_SYS_CS0_SIZE (256 << 20)
	255
	256	/*-----------------------------------------------------------------------
	257	* FLASH and environment organization
	258	*/
	259
	260	/* ** PISMO SUPPORT * */
	261	/* Monitor at start of flash */
	262	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	263	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	264
	265	#define CONFIG_ENV_IS_IN_NAND
	266	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	267	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	268	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	269
a8a78c74 IG	270	#if defined(CONFIG_CMD_NET)
	271	#define CONFIG_DRIVER_TI_EMAC
	272	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	273	#define CONFIG_MII
	274	#define CONFIG_SMC911X
	275	#define CONFIG_SMC911X_32_BIT
	276	#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
e093d0b2 DL	277	#define CONFIG_ARP_TIMEOUT 200UL
e093d0b2 DL	278	#define CONFIG_NET_RETRY_COUNT 5
a8a78c74 IG	279	#endif /* CONFIG_CMD_NET */
a8a78c74 IG	280
b09bf723 IG	281	/* additions for new relocation code, must be added to all boards */
	282	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	283	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	284	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	285	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	286	CONFIG_SYS_INIT_RAM_SIZE - \
	287	GENERATED_GBL_DATA_SIZE)
	288
	289	/* Status LED */
	290	#define CONFIG_STATUS_LED /* Status LED enabled */
	291	#define CONFIG_BOARD_SPECIFIC_LED
	292	#define CONFIG_GPIO_LED
	293	#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
	294	#define GREEN_LED_DEV 0
	295	#define STATUS_LED_BIT GREEN_LED_GPIO
	296	#define STATUS_LED_STATE STATUS_LED_ON
	297	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	298	#define STATUS_LED_BOOT GREEN_LED_DEV
	299
	300	/* GPIO banks */
	301	#ifdef CONFIG_STATUS_LED
	302	#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
	303	#endif
	304
40bbd52a IG	305	/* Display Configuration */
	306	#define CONFIG_OMAP3_GPIO_2
	307	#define CONFIG_OMAP3_GPIO_5
	308	#define CONFIG_VIDEO_OMAP3
	309	#define LCD_BPP LCD_COLOR16
	310
	311	#define CONFIG_LCD
	312	#define CONFIG_SPLASH_SCREEN
	313	#define CONFIG_SPLASHIMAGE_GUARD
	314	#define CONFIG_CMD_BMP
	315	#define CONFIG_BMP_16BPP
	316	#define CONFIG_SCF0403_LCD
	317
	318	#define CONFIG_OMAP3_SPI
	319
b09bf723	320	#endif /* __CONFIG_H */