[people/ms/u-boot.git] / include / configs / cobra5272.h

/*
 * Configuation settings for the Sentec Cobra Board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ---
 * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
 * Date: 2004-03-29
 * Author: Florian Schlote
 *
 * For a description of configuration options please refer also to the
 * general u-boot-1.x.x/README file
 * ---
 */

/* ---
 * board/config.h - configuration options, board specific
 * ---
 */

#ifndef _CONFIG_COBRA5272_H
#define _CONFIG_COBRA5272_H

/* ---
 * Define processor
 * possible values for Sentec board: only Coldfire M5272 processor supported
 * (please do not change)
 * ---
 */

#define CONFIG_MCF52x2			/* define processor family */
#define CONFIG_M5272			/* define processor type */

/* ---
 * Defines processor clock - important for correct timings concerning serial
 * interface etc.
 * ---
 */

#define CONFIG_SYS_CLK			66000000
#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */

/* ---
 * Enable use of Ethernet
 * ---
 */
#define CONFIG_MCFFEC

/* Enable Dma Timer */
#define CONFIG_MCFTMR

/* ---
 * Define baudrate for UART1 (console output, tftp, ...)
 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
 * interface
 * ---
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		19200

/* ---
 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
 * timeout acc. to your needs
 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
 * for 10 sec
 * ---
 */

#if 0
#define CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
#endif

/* ---
 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
 * bootloader residing in flash ('chainloading'); if you want to use
 * chainloading or want to compile a u-boot binary that can be loaded into
 * RAM via BDM set
 *	"#if 0" to "#if 1"
 * You will need a first stage bootloader then, e. g. colilo or a working BDM
 * cable (Background Debug Mode)
 *
 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
 *
 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
 *
 * ---
 */

#if 0
#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
#endif

/* ---
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 * ---
 */

#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING

#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_MII

#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/*
 *-----------------------------------------------------------------------------
 * Define user parameters that have to be customized most likely
 *-----------------------------------------------------------------------------
 */

/*AUTOBOOT settings - booting images automatically by u-boot after power on*/

#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
seconds u-boot will wait before starting defined (auto-)boot command, setting
to -1 disables delay, setting to 0 will too prevent access to u-boot command
interface: u-boot then has to reflashed */


/* The following settings will be contained in the environment block ; if you
want to use a neutral environment all those settings can be manually set in
u-boot: 'set' command */

#if 0

#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
enter a valid image address in flash */

#define CONFIG_BOOTARGS		" "			/* default bootargs that are
considered during boot */

/* User network settings */

#define CONFIG_ETHADDR 00:00:00:00:00:09	/* default ethernet MAC addr. */
#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */

#endif

#define CONFIG_SYS_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/

#define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
from which user programs will be started */

/*---*/

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

/*
 *-----------------------------------------------------------------------------
 * End of user parameters to be customized
 *-----------------------------------------------------------------------------
 */

/* ---
 * Defines memory range for test
 * ---
 */

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

/* ---
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * ---
 */

/* ---
 * Base register address
 * ---
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */

/* ---
 * System Conf. Reg. & System Protection Reg.
 * ---
 */

#define CONFIG_SYS_SCR			0x0003
#define CONFIG_SYS_SPR			0xffff

/* ---
 * Ethernet settings
 * ---
 */

#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_ENET_BD_BASE	0x780000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in internal SRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000

/*
 *-------------------------------------------------------------------------
 * RAM SIZE (is defined above)
 *-----------------------------------------------------------------------
 */

/* #define CONFIG_SYS_SDRAM_SIZE		16 */

/*
 *-----------------------------------------------------------------------
 */

#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 *
 * Please refer also to Motorola Coldfire user manual - Chapter XXX
 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
 */
#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
#define CONFIG_SYS_OR0_PRELIM		0xFFE00014

#define CONFIG_SYS_BR1_PRELIM		0
#define CONFIG_SYS_OR1_PRELIM		0

#define CONFIG_SYS_BR2_PRELIM		0
#define CONFIG_SYS_OR2_PRELIM		0

#define CONFIG_SYS_BR3_PRELIM		0
#define CONFIG_SYS_OR3_PRELIM		0

#define CONFIG_SYS_BR4_PRELIM		0
#define CONFIG_SYS_OR4_PRELIM		0

#define CONFIG_SYS_BR5_PRELIM		0
#define CONFIG_SYS_OR5_PRELIM		0

#define CONFIG_SYS_BR6_PRELIM		0
#define CONFIG_SYS_OR6_PRELIM		0

#define CONFIG_SYS_BR7_PRELIM		0x00000701
#define CONFIG_SYS_OR7_PRELIM		0xFF00007C

/*-----------------------------------------------------------------------
 * LED config
 */
#define	LED_STAT_0	0xffff /*all LEDs off*/
#define	LED_STAT_1	0xfffe
#define	LED_STAT_2	0xfffd
#define	LED_STAT_3	0xfffb
#define	LED_STAT_4	0xfff7
#define	LED_STAT_5	0xffef
#define	LED_STAT_6	0xffdf
#define	LED_STAT_7	0xff00 /*all LEDs on*/

/*-----------------------------------------------------------------------
 * Port configuration (GPIO)
 */
#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
GPIO*/
#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
(1^=output, 0^=input) */
#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
configuration */
#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */

#endif	/* _CONFIG_COBRA5272_H */
Commit	Line	Data
a562e1bd WD	1	/*
	2	* Configuation settings for the Sentec Cobra Board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
a562e1bd WD	7	*/
	8
	9	/* ---
	10	* Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
	11	* Date: 2004-03-29
	12	* Author: Florian Schlote
	13	*
	14	* For a description of configuration options please refer also to the
	15	* general u-boot-1.x.x/README file
	16	* ---
	17	*/
	18
	19	/* ---
	20	* board/config.h - configuration options, board specific
	21	* ---
	22	*/
	23
	24	#ifndef _CONFIG_COBRA5272_H
	25	#define _CONFIG_COBRA5272_H
	26
	27	/* ---
	28	* Define processor
	29	* possible values for Sentec board: only Coldfire M5272 processor supported
	30	* (please do not change)
	31	* ---
	32	*/
	33
	34	#define CONFIG_MCF52x2 /* define processor family */
	35	#define CONFIG_M5272 /* define processor type */
	36
	37	/* ---
	38	* Defines processor clock - important for correct timings concerning serial
	39	* interface etc.
a562e1bd WD	40	* ---
	41	*/
	42
6d0f6bcf JCPV	43	#define CONFIG_SYS_CLK 66000000
6d0f6bcf JCPV	44	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
a562e1bd WD	45
	46	/* ---
	47	* Enable use of Ethernet
	48	* ---
	49	*/
6706424d	50	#define CONFIG_MCFFEC
a562e1bd	51
6706424d TL	52	/* Enable Dma Timer */
6706424d TL	53	#define CONFIG_MCFTMR
a562e1bd WD	54
	55	/* ---
	56	* Define baudrate for UART1 (console output, tftp, ...)
	57	* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
6d0f6bcf	58	* CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
a562e1bd WD	59	* interface
	60	* ---
	61	*/
	62
6706424d	63	#define CONFIG_MCFUART
6d0f6bcf	64	#define CONFIG_SYS_UART_PORT (0)
a562e1bd	65	#define CONFIG_BAUDRATE 19200
a562e1bd WD	66
	67	/* ---
	68	* set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
	69	* timeout acc. to your needs
	70	* #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
	71	* for 10 sec
	72	* ---
	73	*/
	74
	75	#if 0
	76	#define CONFIG_WATCHDOG
	77	#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
	78	#endif
	79
	80	/* ---
	81	* CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
	82	* bootloader residing in flash ('chainloading'); if you want to use
	83	* chainloading or want to compile a u-boot binary that can be loaded into
	84	* RAM via BDM set
53677ef1	85	* "#if 0" to "#if 1"
a562e1bd WD	86	* You will need a first stage bootloader then, e. g. colilo or a working BDM
	87	* cable (Background Debug Mode)
	88	*
	89	* Setting #if 0: u-boot will start from flash and relocate itself to RAM
	90	*
14d0a02a	91	* Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
a562e1bd WD	92	* in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
	93	*
	94	* ---
	95	*/
	96
	97	#if 0
	98	#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
	99	#endif
	100
	101	/* ---
	102	* Configuration for environment
	103	* Environment is embedded in u-boot in the second sector of the flash
	104	* ---
	105	*/
	106
	107	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	108	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	109	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	110	#define CONFIG_ENV_IS_IN_FLASH 1
a562e1bd	111	#else
0e8d1586 JCPV	112	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	113	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	114	#define CONFIG_ENV_IS_IN_FLASH 1
a562e1bd WD	115	#endif
a562e1bd WD	116
37e4f24b	117
80ff4f99 JL	118	/*
	119	* BOOTP options
	120	*/
	121	#define CONFIG_BOOTP_BOOTFILESIZE
	122	#define CONFIG_BOOTP_BOOTPATH
	123	#define CONFIG_BOOTP_GATEWAY
	124	#define CONFIG_BOOTP_HOSTNAME
	125
	126
37e4f24b JL	127	/*
37e4f24b JL	128	* Command line configuration.
a562e1bd	129	*/
37e4f24b JL	130	#include <config_cmd_default.h>
	131
	132	#define CONFIG_CMD_PING
a562e1bd	133
37e4f24b JL	134	#undef CONFIG_CMD_LOADS
	135	#undef CONFIG_CMD_LOADB
	136	#undef CONFIG_CMD_MII
a562e1bd	137
6706424d	138	#ifdef CONFIG_MCFFEC
6706424d	139	# define CONFIG_MII 1
0f3ba7e9	140	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	141	# define CONFIG_SYS_DISCOVER_PHY
	142	# define CONFIG_SYS_RX_ETH_BUFFER 8
	143	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6706424d	144
6d0f6bcf JCPV	145	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	146	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	147	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	148	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	149	# ifndef CONFIG_SYS_DISCOVER_PHY
6706424d TL	150	# define FECDUPLEX FULL
	151	# define FECSPEED _100BASET
	152	# else
6d0f6bcf JCPV	153	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	154	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6706424d	155	# endif
6d0f6bcf	156	# endif /* CONFIG_SYS_DISCOVER_PHY */
6706424d	157	#endif
a562e1bd WD	158
	159	/*
	160	*-----------------------------------------------------------------------------
	161	* Define user parameters that have to be customized most likely
	162	*-----------------------------------------------------------------------------
	163	*/
	164
	165	/AUTOBOOT settings - booting images automatically by u-boot after power on/
	166
	167	#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in
	168	seconds u-boot will wait before starting defined (auto-)boot command, setting
	169	to -1 disables delay, setting to 0 will too prevent access to u-boot command
	170	interface: u-boot then has to reflashed */
	171
	172
	173	/* The following settings will be contained in the environment block ; if you
	174	want to use a neutral environment all those settings can be manually set in
	175	u-boot: 'set' command */
	176
	177	#if 0
	178
	179	#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
	180	enter a valid image address in flash */
	181
	182	#define CONFIG_BOOTARGS " " /* default bootargs that are
	183	considered during boot */
	184
	185	/* User network settings */
	186
	187	#define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */
	188	#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
	189	#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
	190
	191	#endif
	192
6d0f6bcf	193	#define CONFIG_SYS_PROMPT "COBRA > " /* Layout of u-boot prompt*/
a562e1bd	194
6d0f6bcf	195	#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
a562e1bd WD	196	from which user programs will be started */
	197
	198	/---/
	199
6d0f6bcf	200	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a562e1bd	201
37e4f24b	202	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	203	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a562e1bd	204	#else
6d0f6bcf	205	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a562e1bd	206	#endif
6d0f6bcf JCPV	207	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	208	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	209	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a562e1bd WD	210
	211	/*
	212	*-----------------------------------------------------------------------------
	213	* End of user parameters to be customized
	214	*-----------------------------------------------------------------------------
	215	*/
	216
	217	/* ---
	218	* Defines memory range for test
	219	* ---
	220	*/
	221
6d0f6bcf JCPV	222	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	223	#define CONFIG_SYS_MEMTEST_END 0x380000
a562e1bd WD	224
	225	/* ---
	226	* Low Level Configuration Settings
	227	* (address mappings, register initial values, etc.)
	228	* You should know what you are doing if you make changes here.
	229	* ---
	230	*/
	231
	232	/* ---
	233	* Base register address
	234	* ---
	235	*/
	236
6d0f6bcf	237	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
a562e1bd WD	238
	239	/* ---
	240	* System Conf. Reg. & System Protection Reg.
	241	* ---
	242	*/
	243
6d0f6bcf JCPV	244	#define CONFIG_SYS_SCR 0x0003
6d0f6bcf JCPV	245	#define CONFIG_SYS_SPR 0xffff
a562e1bd WD	246
	247	/* ---
	248	* Ethernet settings
	249	* ---
	250	*/
	251
6d0f6bcf JCPV	252	#define CONFIG_SYS_DISCOVER_PHY
6d0f6bcf JCPV	253	#define CONFIG_SYS_ENET_BD_BASE 0x780000
a562e1bd WD	254
	255	/*-----------------------------------------------------------------------
	256	* Definitions for initial stack pointer and data area (in internal SRAM)
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	259	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	260	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	261	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a562e1bd WD	262
	263	/*-----------------------------------------------------------------------
	264	* Start addresses for the final memory configuration
	265	* (Set up by the startup code)
6d0f6bcf	266	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a562e1bd	267	*/
6d0f6bcf	268	#define CONFIG_SYS_SDRAM_BASE 0x00000000
a562e1bd WD	269
	270	/*
	271	*-------------------------------------------------------------------------
	272	* RAM SIZE (is defined above)
	273	*-----------------------------------------------------------------------
	274	*/
	275
6d0f6bcf	276	/* #define CONFIG_SYS_SDRAM_SIZE 16 */
a562e1bd WD	277
	278	/*
	279	*-----------------------------------------------------------------------
	280	*/
	281
6d0f6bcf	282	#define CONFIG_SYS_FLASH_BASE 0xffe00000
a562e1bd WD	283
a562e1bd WD	284	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	285	#define CONFIG_SYS_MONITOR_BASE 0x20000
a562e1bd	286	#else
6d0f6bcf	287	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a562e1bd WD	288	#endif
a562e1bd WD	289
6d0f6bcf JCPV	290	#define CONFIG_SYS_MONITOR_LEN 0x20000
	291	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	292	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
a562e1bd WD	293
	294	/*
	295	* For booting Linux, the board info and command line data
	296	* have to be in the first 8 MB of memory, since this is
	297	* the maximum mapped by the Linux kernel during initialization ??
	298	*/
6d0f6bcf	299	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
a562e1bd WD	300
	301	/*-----------------------------------------------------------------------
	302	* FLASH organization
	303	*/
6d0f6bcf JCPV	304	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	305	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	306	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
a562e1bd WD	307
	308	/*-----------------------------------------------------------------------
	309	* Cache Configuration
	310	*/
6d0f6bcf	311	#define CONFIG_SYS_CACHELINE_SIZE 16
a562e1bd	312
dd9f054e	313	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	314	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	315	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	316	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	317	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	318	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	319	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	320	CF_ACR_EN \| CF_ACR_SM_ALL)
	321	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	322	CF_CACR_DISD \| CF_CACR_INVI \| \
	323	CF_CACR_CEIB \| CF_CACR_DCM \| \
	324	CF_CACR_EUSP)
	325
a562e1bd WD	326	/*-----------------------------------------------------------------------
	327	* Memory bank definitions
	328	*
	329	* Please refer also to Motorola Coldfire user manual - Chapter XXX
	330	* <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
	331	*/
6d0f6bcf JCPV	332	#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
6d0f6bcf JCPV	333	#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
a562e1bd	334
6d0f6bcf JCPV	335	#define CONFIG_SYS_BR1_PRELIM 0
6d0f6bcf JCPV	336	#define CONFIG_SYS_OR1_PRELIM 0
a562e1bd	337
6d0f6bcf JCPV	338	#define CONFIG_SYS_BR2_PRELIM 0
6d0f6bcf JCPV	339	#define CONFIG_SYS_OR2_PRELIM 0
a562e1bd	340
6d0f6bcf JCPV	341	#define CONFIG_SYS_BR3_PRELIM 0
6d0f6bcf JCPV	342	#define CONFIG_SYS_OR3_PRELIM 0
a562e1bd	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_BR4_PRELIM 0
6d0f6bcf JCPV	345	#define CONFIG_SYS_OR4_PRELIM 0
a562e1bd	346
6d0f6bcf JCPV	347	#define CONFIG_SYS_BR5_PRELIM 0
6d0f6bcf JCPV	348	#define CONFIG_SYS_OR5_PRELIM 0
a562e1bd	349
6d0f6bcf JCPV	350	#define CONFIG_SYS_BR6_PRELIM 0
6d0f6bcf JCPV	351	#define CONFIG_SYS_OR6_PRELIM 0
a562e1bd	352
6d0f6bcf JCPV	353	#define CONFIG_SYS_BR7_PRELIM 0x00000701
6d0f6bcf JCPV	354	#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
a562e1bd WD	355
	356	/*-----------------------------------------------------------------------
	357	* LED config
	358	*/
	359	#define LED_STAT_0 0xffff /all LEDs off/
	360	#define LED_STAT_1 0xfffe
	361	#define LED_STAT_2 0xfffd
	362	#define LED_STAT_3 0xfffb
	363	#define LED_STAT_4 0xfff7
	364	#define LED_STAT_5 0xffef
	365	#define LED_STAT_6 0xffdf
	366	#define LED_STAT_7 0xff00 /all LEDs on/
	367
	368	/*-----------------------------------------------------------------------
	369	* Port configuration (GPIO)
	370	*/
6d0f6bcf	371	#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
a562e1bd	372	GPIO*/
6d0f6bcf	373	#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
a562e1bd	374	(1^=output, 0^=input) */
6d0f6bcf JCPV	375	#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
6d0f6bcf JCPV	376	#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
a562e1bd	377	configuration */
6d0f6bcf JCPV	378	#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
	379	#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
	380	#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
a562e1bd WD	381
a562e1bd WD	382	#endif /* _CONFIG_COBRA5272_H */