projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| b9944a77 DE |
1 | /* |
| 2 | * (C) Copyright 2013 | |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc | |
| 4 | * | |
| 5 | * based on P1022DS.h | |
| 6 | * | |
| 7 | * See file CREDITS for list of people who contributed to this | |
| 8 | * project. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| 25 | ||
| 26 | #ifndef __CONFIG_H | |
| 27 | #define __CONFIG_H | |
| 28 | ||
| 29 | #ifdef CONFIG_36BIT | |
| 30 | #define CONFIG_PHYS_64BIT | |
| 31 | #endif | |
| 32 | ||
| 33 | #ifdef CONFIG_SDCARD | |
| 34 | #define CONFIG_RAMBOOT_SDCARD | |
| 35 | #endif | |
| 36 | ||
| 37 | #ifdef CONFIG_SPIFLASH | |
| 38 | #define CONFIG_RAMBOOT_SPIFLASH | |
| 39 | #endif | |
| 40 | ||
| 41 | /* High Level Configuration Options */ | |
| 42 | #define CONFIG_BOOKE /* BOOKE */ | |
| 43 | #define CONFIG_E500 /* BOOKE e500 family */ | |
| 44 | #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ | |
| 45 | #define CONFIG_P1022 | |
| 46 | #define CONFIG_CONTROLCENTERD | |
| 47 | #define CONFIG_MP /* support multiple processors */ | |
| 48 | ||
| 49 | #define CONFIG_SYS_NO_FLASH | |
| 50 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 51 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
| 52 | ||
| 53 | #ifdef CONFIG_TRAILBLAZER | |
| 54 | #define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01" | |
| 55 | #else | |
| 56 | #define CONFIG_IDENT_STRING " controlcenterd 0.01" | |
| 57 | #endif | |
| 58 | ||
| 59 | #ifdef CONFIG_PHYS_64BIT | |
| 60 | #define CONFIG_ADDR_MAP | |
| 61 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 62 | #endif | |
| 63 | ||
| 64 | #define CONFIG_L2_CACHE | |
| 65 | #define CONFIG_BTB | |
| 66 | ||
| 67 | #define CONFIG_SYS_CLK_FREQ 66666600 | |
| 68 | #define CONFIG_DDR_CLK_FREQ 66666600 | |
| 69 | ||
| 70 | #define CONFIG_SYS_RAMBOOT | |
| 71 | ||
| 72 | #ifdef CONFIG_TRAILBLAZER | |
| 73 | ||
| 74 | #define CONFIG_SYS_TEXT_BASE 0xf8fc0000 | |
| 75 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc | |
| 76 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
| 77 | ||
| 78 | /* | |
| 79 | * Config the L2 Cache | |
| 80 | */ | |
| 81 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 | |
| 82 | #ifdef CONFIG_PHYS_64BIT | |
| 83 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull | |
| 84 | #else | |
| 85 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 86 | #endif | |
| 87 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 88 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 89 | ||
| 90 | #else /* CONFIG_TRAILBLAZER */ | |
| 91 | ||
| 92 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| 93 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
| 94 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
| 95 | ||
| 96 | #endif /* CONFIG_TRAILBLAZER */ | |
| 97 | ||
| 98 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
| 99 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
| 100 | ||
| 101 | ||
| 102 | /* | |
| 103 | * Memory map | |
| 104 | * | |
| 105 | * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable | |
| 106 | * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable | |
| 107 | * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable | |
| 108 | * | |
| 109 | * Localbus non-cacheable | |
| 110 | * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable | |
| 111 | * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable | |
| 112 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 113 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 114 | */ | |
| 115 | ||
| 116 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 117 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 118 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ | |
| 119 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
| 120 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 121 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 122 | ||
| 123 | #ifdef CONFIG_TRAILBLAZER | |
| 124 | /* leave CCSRBAR at default, because u-boot expects it to be exactly there */ | |
| 125 | #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT | |
| 126 | #else | |
| 127 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
| 128 | #endif | |
| 129 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 130 | #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) | |
| 131 | ||
| 132 | /* | |
| 133 | * DDR Setup | |
| 134 | */ | |
| 135 | ||
| 136 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 137 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 138 | #define CONFIG_SYS_SDRAM_SIZE 1024 | |
| 139 | #define CONFIG_VERY_BIG_RAM | |
| 140 | ||
| 5614e71b | 141 | #define CONFIG_SYS_FSL_DDR3 |
| b9944a77 DE |
142 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 143 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 144 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 145 | ||
| 146 | #define CONFIG_SYS_MEMTEST_START 0x00000000 | |
| 147 | #define CONFIG_SYS_MEMTEST_END 0x3fffffff | |
| 148 | ||
| 149 | #ifdef CONFIG_TRAILBLAZER | |
| 150 | #define CONFIG_SPD_EEPROM | |
| 151 | #define SPD_EEPROM_ADDRESS 0x52 | |
| 152 | /*#define CONFIG_FSL_DDR_INTERACTIVE*/ | |
| 153 | #endif | |
| 154 | ||
| 155 | /* | |
| 156 | * Local Bus Definitions | |
| 157 | */ | |
| 158 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
| 159 | ||
| 160 | #define CONFIG_SYS_ELBC_BASE 0xe0000000 | |
| 161 | #ifdef CONFIG_PHYS_64BIT | |
| 162 | #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull | |
| 163 | #else | |
| 164 | #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE | |
| 165 | #endif | |
| 166 | ||
| 167 | #define CONFIG_UART_BR_PRELIM \ | |
| 168 | (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) | |
| 169 | #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) | |
| 170 | ||
| 171 | #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ | |
| 172 | #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ | |
| 173 | ||
| 174 | #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM | |
| 175 | #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM | |
| 176 | ||
| 177 | /* | |
| 178 | * Serial Port | |
| 179 | */ | |
| 180 | #define CONFIG_CONS_INDEX 2 | |
| 181 | #define CONFIG_SYS_NS16550 | |
| 182 | #define CONFIG_SYS_NS16550_SERIAL | |
| 183 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 184 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 185 | ||
| 186 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 187 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 188 | ||
| 189 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 190 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 191 | ||
| 192 | /* | |
| 193 | * I2C | |
| 194 | */ | |
| 00f792e0 HS |
195 | #define CONFIG_SYS_I2C |
| 196 | #define CONFIG_SYS_I2C_FSL | |
| 197 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 198 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 199 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 200 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 201 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 202 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| b9944a77 DE |
203 | /* Probing DP501 I2C-Bridge will hang */ |
| 204 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \ | |
| 205 | {0, 0x3b}, {0, 0x50} } | |
| 206 | ||
| 207 | #define CONFIG_PCA9698 /* NXP PCA9698 */ | |
| 208 | ||
| 209 | #define CONFIG_CMD_EEPROM | |
| 210 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
| 211 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 212 | ||
| 213 | #ifndef CONFIG_TRAILBLAZER | |
| 214 | /* | |
| 215 | * eSPI - Enhanced SPI | |
| 216 | */ | |
| 217 | #define CONFIG_HARD_SPI | |
| 218 | #define CONFIG_FSL_ESPI | |
| 219 | ||
| 220 | #define CONFIG_SPI_FLASH | |
| 221 | #define CONFIG_SPI_FLASH_STMICRO | |
| 222 | ||
| 223 | #define CONFIG_CMD_SF | |
| 224 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 225 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 226 | #endif | |
| 227 | ||
| 228 | /* | |
| 229 | * TPM | |
| 230 | */ | |
| 231 | #define CONFIG_TPM_ATMEL_TWI | |
| 232 | #define CONFIG_TPM | |
| 233 | #define CONFIG_TPM_AUTH_SESSIONS | |
| 234 | #define CONFIG_SHA1 | |
| 235 | #define CONFIG_CMD_TPM | |
| 236 | ||
| 237 | /* | |
| 238 | * MMC | |
| 239 | */ | |
| 240 | #define CONFIG_MMC | |
| 241 | #define CONFIG_GENERIC_MMC | |
| 242 | #define CONFIG_CMD_MMC | |
| 243 | ||
| 244 | #define CONFIG_FSL_ESDHC | |
| 245 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 246 | ||
| 247 | ||
| 248 | #ifndef CONFIG_TRAILBLAZER | |
| 249 | ||
| 250 | /* | |
| 251 | * Video | |
| 252 | */ | |
| 253 | #define CONFIG_FSL_DIU_FB | |
| 254 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) | |
| 255 | #define CONFIG_VIDEO | |
| 256 | #define CONFIG_CFB_CONSOLE | |
| 257 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 258 | #define CONFIG_CMD_BMP | |
| 259 | ||
| 260 | /* | |
| 261 | * General PCI | |
| 262 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 263 | */ | |
| 264 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 265 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
| 266 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
| 267 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 268 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 269 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 270 | #define CONFIG_CMD_PCI | |
| 271 | ||
| 272 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 273 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
| 274 | ||
| 275 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
| 276 | #ifdef CONFIG_PHYS_64BIT | |
| 277 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 278 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull | |
| 279 | #else | |
| 280 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
| 281 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
| 282 | #endif | |
| 283 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 284 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
| 285 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 286 | #ifdef CONFIG_PHYS_64BIT | |
| 287 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
| 288 | #else | |
| 289 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
| 290 | #endif | |
| 291 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 292 | ||
| 293 | /* | |
| 294 | * SATA | |
| 295 | */ | |
| 296 | #define CONFIG_LIBATA | |
| 297 | #define CONFIG_LBA48 | |
| 298 | #define CONFIG_CMD_SATA | |
| 299 | ||
| 300 | #define CONFIG_FSL_SATA | |
| 301 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 302 | #define CONFIG_SATA1 | |
| 303 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 304 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 305 | #define CONFIG_SATA2 | |
| 306 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 307 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 308 | ||
| 309 | /* | |
| 310 | * Ethernet | |
| 311 | */ | |
| 312 | #define CONFIG_TSEC_ENET | |
| 313 | ||
| 314 | #define CONFIG_TSECV2 | |
| 315 | ||
| 316 | #define CONFIG_MII /* MII PHY management */ | |
| 317 | #define CONFIG_TSEC1 1 | |
| 318 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 319 | #define CONFIG_TSEC2 1 | |
| 320 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 321 | ||
| 322 | #define TSEC1_PHY_ADDR 0 | |
| 323 | #define TSEC2_PHY_ADDR 1 | |
| 324 | ||
| 325 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 326 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 327 | ||
| 328 | #define TSEC1_PHYIDX 0 | |
| 329 | #define TSEC2_PHYIDX 0 | |
| 330 | ||
| 331 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 332 | ||
| 333 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 334 | ||
| 335 | /* | |
| 336 | * USB | |
| 337 | */ | |
| 338 | #define CONFIG_USB_EHCI | |
| 339 | #define CONFIG_CMD_USB | |
| 340 | #define CONFIG_USB_STORAGE | |
| 341 | ||
| 342 | #define CONFIG_HAS_FSL_DR_USB | |
| 343 | #define CONFIG_USB_EHCI_FSL | |
| 344 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 345 | ||
| 346 | #endif /* CONFIG_TRAILBLAZER */ | |
| 347 | ||
| 348 | /* | |
| 349 | * Environment | |
| 350 | */ | |
| 351 | #if defined(CONFIG_TRAILBLAZER) | |
| 352 | #define CONFIG_ENV_IS_NOWHERE | |
| 353 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 354 | #undef CONFIG_CMD_SAVEENV | |
| 355 | #elif defined(CONFIG_RAMBOOT_SPIFLASH) | |
| 356 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 357 | #define CONFIG_ENV_SPI_BUS 0 | |
| 358 | #define CONFIG_ENV_SPI_CS 0 | |
| 359 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 360 | #define CONFIG_ENV_SPI_MODE 0 | |
| 361 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 362 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 363 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 364 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
| 365 | #define CONFIG_ENV_IS_IN_MMC | |
| 366 | #define CONFIG_FSL_FIXED_MMC_LOCATION | |
| 367 | #define CONFIG_ENV_SIZE 0x2000 | |
| 368 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 369 | #endif | |
| 370 | ||
| 371 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 372 | ||
| 373 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 374 | ||
| 375 | /* | |
| 376 | * Command line configuration. | |
| 377 | */ | |
| 378 | #ifndef CONFIG_TRAILBLAZER | |
| 379 | #define CONFIG_SYS_HUSH_PARSER | |
| 380 | #define CONFIG_SYS_LONGHELP | |
| 381 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 382 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 383 | #endif /* CONFIG_TRAILBLAZER */ | |
| 384 | ||
| 385 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| b9944a77 DE |
386 | #ifdef CONFIG_CMD_KGDB |
| 387 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 388 | #else | |
| 389 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 390 | #endif | |
| 391 | /* Print Buffer Size */ | |
| 392 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 393 | #define CONFIG_SYS_MAXARGS 16 | |
| 394 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 395 | ||
| 396 | #include <config_cmd_default.h> | |
| 397 | ||
| 398 | #ifndef CONFIG_TRAILBLAZER | |
| 399 | ||
| 400 | #define CONFIG_CMD_ELF | |
| 401 | #define CONFIG_CMD_ERRATA | |
| 402 | #define CONFIG_CMD_EXT2 | |
| 403 | #define CONFIG_CMD_FAT | |
| 404 | #define CONFIG_CMD_IRQ | |
| 405 | #define CONFIG_CMD_MII | |
| 406 | #define CONFIG_CMD_NET | |
| 407 | #define CONFIG_CMD_PING | |
| 408 | #define CONFIG_CMD_SETEXPR | |
| 409 | #define CONFIG_CMD_REGINFO | |
| 410 | ||
| 411 | /* | |
| 412 | * Board initialisation callbacks | |
| 413 | */ | |
| 414 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 415 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 416 | #define CONFIG_MISC_INIT_R | |
| 417 | #define CONFIG_LAST_STAGE_INIT | |
| 418 | ||
| 419 | /* | |
| 420 | * Pass open firmware flat tree | |
| 421 | */ | |
| 422 | #define CONFIG_OF_LIBFDT | |
| 423 | #define CONFIG_OF_BOARD_SETUP | |
| 424 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 425 | ||
| 426 | /* new uImage format support */ | |
| 427 | #define CONFIG_FIT | |
| 428 | #define CONFIG_FIT_VERBOSE | |
| 429 | ||
| 430 | #else /* CONFIG_TRAILBLAZER */ | |
| 431 | ||
| 432 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 433 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 434 | #define CONFIG_LAST_STAGE_INIT | |
| 435 | #undef CONFIG_CMD_BOOTM | |
| 436 | ||
| 437 | #endif /* CONFIG_TRAILBLAZER */ | |
| 438 | ||
| 439 | /* | |
| 440 | * Miscellaneous configurable options | |
| 441 | */ | |
| b9944a77 DE |
442 | #define CONFIG_HW_WATCHDOG |
| 443 | #define CONFIG_LOADS_ECHO | |
| 444 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
| 445 | #define CONFIG_DOS_PARTITION | |
| 446 | ||
| 447 | /* | |
| 448 | * For booting Linux, the board info and command line data | |
| 449 | * have to be in the first 64 MB of memory, since this is | |
| 450 | * the maximum mapped by the Linux kernel during initialization. | |
| 451 | */ | |
| 452 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ | |
| 453 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 454 | ||
| 455 | /* | |
| 456 | * Environment Configuration | |
| 457 | */ | |
| 458 | ||
| 459 | #ifdef CONFIG_TRAILBLAZER | |
| 460 | ||
| 461 | #define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */ | |
| 462 | #define CONFIG_BAUDRATE 115200 | |
| 463 | ||
| 464 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 465 | "mp_holdoff=1\0" | |
| 466 | ||
| 467 | #else | |
| 468 | ||
| 469 | #define CONFIG_HOSTNAME controlcenterd | |
| 470 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 471 | #define CONFIG_BOOTFILE "uImage" | |
| 472 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ | |
| 473 | ||
| 474 | #define CONFIG_LOADADDR 1000000 | |
| 475 | ||
| 476 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 477 | ||
| 478 | #define CONFIG_BAUDRATE 115200 | |
| 479 | ||
| 480 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 481 | "netdev=eth0\0" \ | |
| 482 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 483 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 484 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 485 | "protect off $ubootaddr +$filesize && " \ | |
| 486 | "erase $ubootaddr +$filesize && " \ | |
| 487 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 488 | "protect on $ubootaddr +$filesize && " \ | |
| 489 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 490 | "consoledev=ttyS1\0" \ | |
| 491 | "ramdiskaddr=2000000\0" \ | |
| 492 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 493 | "fdtaddr=c00000\0" \ | |
| 494 | "fdtfile=controlcenterd.dtb\0" \ | |
| 495 | "bdev=sda3\0" | |
| 496 | ||
| 497 | /* these are used and NUL-terminated in env_default.h */ | |
| 498 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 499 | "setenv bootargs root=/dev/nfs rw " \ | |
| 500 | "nfsroot=$serverip:$rootpath " \ | |
| 501 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 502 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ | |
| 503 | "tftp $loadaddr $bootfile;" \ | |
| 504 | "tftp $fdtaddr $fdtfile;" \ | |
| 505 | "bootm $loadaddr - $fdtaddr" | |
| 506 | ||
| 507 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 508 | "setenv bootargs root=/dev/ram rw " \ | |
| 509 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ | |
| 510 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 511 | "tftp $loadaddr $bootfile;" \ | |
| 512 | "tftp $fdtaddr $fdtfile;" \ | |
| 513 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 514 | ||
| 515 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 516 | ||
| 517 | #endif /* CONFIG_TRAILBLAZER */ | |
| 518 | ||
| 519 | #endif |