projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d1712369 | 1 | /* |
| 3d7506fa | 2 | * Copyright 2009-2012 Freescale Semiconductor, Inc. |
| d1712369 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| d1712369 KG |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * Corenet DS style board configuration file | |
| 9 | */ | |
| 10 | #ifndef __CONFIG_H | |
| 11 | #define __CONFIG_H | |
| 12 | ||
| 15672c6d YS |
13 | #define CONFIG_SYS_GENERIC_BOARD |
| 14 | #define CONFIG_DISPLAY_BOARDINFO | |
| 15 | ||
| d1712369 KG |
16 | #include "../board/freescale/common/ics307_clk.h" |
| 17 | ||
| 2a9fab82 | 18 | #ifdef CONFIG_RAMBOOT_PBL |
| 467a40df AB |
19 | #ifdef CONFIG_SECURE_BOOT |
| 20 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
| 21 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| 22 | #ifdef CONFIG_NAND | |
| 23 | #define CONFIG_RAMBOOT_NAND | |
| 24 | #endif | |
| 5050f6f0 | 25 | #define CONFIG_BOOTSCRIPT_COPY_RAM |
| 467a40df | 26 | #else |
| 2a9fab82 SX |
27 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
| 28 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| e4536f8e | 29 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg |
| 5d898a00 | 30 | #if defined(CONFIG_P3041DS) |
| e4536f8e | 31 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg |
| 5d898a00 | 32 | #elif defined(CONFIG_P4080DS) |
| e4536f8e | 33 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg |
| 5d898a00 | 34 | #elif defined(CONFIG_P5020DS) |
| e4536f8e | 35 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg |
| 94025b1c | 36 | #elif defined(CONFIG_P5040DS) |
| e4536f8e | 37 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg |
| 5d898a00 | 38 | #endif |
| 2a9fab82 | 39 | #endif |
| 467a40df | 40 | #endif |
| 2a9fab82 | 41 | |
| 461632bd | 42 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
| 292dc6c5 | 43 | /* Set 1M boot space */ |
| 461632bd LG |
44 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) |
| 45 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
| 46 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
| 292dc6c5 LG |
47 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
| 48 | #define CONFIG_SYS_NO_FLASH | |
| 49 | #endif | |
| 50 | ||
| d1712369 KG |
51 | /* High Level Configuration Options */ |
| 52 | #define CONFIG_BOOKE | |
| 53 | #define CONFIG_E500 /* BOOKE e500 family */ | |
| 54 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
| 55 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
| d1712369 KG |
56 | #define CONFIG_MP /* support multiple processors */ |
| 57 | ||
| ed179152 | 58 | #ifndef CONFIG_SYS_TEXT_BASE |
| e222b1f3 | 59 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| ed179152 KG |
60 | #endif |
| 61 | ||
| 7a577fda KG |
62 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 63 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 64 | #endif | |
| 65 | ||
| d1712369 KG |
66 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
| 67 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
| 68 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
| 737537ef | 69 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| d1712369 KG |
70 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
| 71 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
| 72 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
| d1712369 KG |
73 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 74 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| d1712369 | 75 | |
| d1712369 KG |
76 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
| 77 | ||
| 78 | #define CONFIG_ENV_OVERWRITE | |
| 79 | ||
| 80 | #ifdef CONFIG_SYS_NO_FLASH | |
| 461632bd | 81 | #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) |
| d1712369 | 82 | #define CONFIG_ENV_IS_NOWHERE |
| 0a85a9e7 | 83 | #endif |
| d1712369 | 84 | #else |
| d1712369 KG |
85 | #define CONFIG_FLASH_CFI_DRIVER |
| 86 | #define CONFIG_SYS_FLASH_CFI | |
| 80e5c83a | 87 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| be827c7a SX |
88 | #endif |
| 89 | ||
| 90 | #if defined(CONFIG_SPIFLASH) | |
| 91 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 92 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 93 | #define CONFIG_ENV_SPI_BUS 0 | |
| 94 | #define CONFIG_ENV_SPI_CS 0 | |
| 95 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 96 | #define CONFIG_ENV_SPI_MODE 0 | |
| 97 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 98 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 99 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 100 | #elif defined(CONFIG_SDCARD) | |
| 101 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 102 | #define CONFIG_ENV_IS_IN_MMC | |
| 4394d0c2 | 103 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| be827c7a SX |
104 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 105 | #define CONFIG_ENV_SIZE 0x2000 | |
| e222b1f3 | 106 | #define CONFIG_ENV_OFFSET (512 * 1658) |
| 374a235d SX |
107 | #elif defined(CONFIG_NAND) |
| 108 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 109 | #define CONFIG_ENV_IS_IN_NAND | |
| 110 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| e222b1f3 | 111 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 461632bd | 112 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 0a85a9e7 LG |
113 | #define CONFIG_ENV_IS_IN_REMOTE |
| 114 | #define CONFIG_ENV_ADDR 0xffe20000 | |
| 115 | #define CONFIG_ENV_SIZE 0x2000 | |
| fd0451e4 LG |
116 | #elif defined(CONFIG_ENV_IS_NOWHERE) |
| 117 | #define CONFIG_ENV_SIZE 0x2000 | |
| be827c7a SX |
118 | #else |
| 119 | #define CONFIG_ENV_IS_IN_FLASH | |
| 2a9fab82 | 120 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| be827c7a SX |
121 | #define CONFIG_ENV_SIZE 0x2000 |
| 122 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| d1712369 KG |
123 | #endif |
| 124 | ||
| 125 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
| d1712369 KG |
126 | |
| 127 | /* | |
| 128 | * These can be toggled for performance analysis, otherwise use default. | |
| 129 | */ | |
| 130 | #define CONFIG_SYS_CACHE_STASHING | |
| 131 | #define CONFIG_BACKSIDE_L2_CACHE | |
| 132 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
| 133 | #define CONFIG_BTB /* toggle branch predition */ | |
| 8ed20f2c | 134 | #define CONFIG_DDR_ECC |
| d1712369 KG |
135 | #ifdef CONFIG_DDR_ECC |
| 136 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 137 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 138 | #endif | |
| 139 | ||
| 140 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 141 | ||
| 142 | #ifdef CONFIG_PHYS_64BIT | |
| 143 | #define CONFIG_ADDR_MAP | |
| 144 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
| 145 | #endif | |
| 146 | ||
| 4672e1ea | 147 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
| d1712369 KG |
148 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 149 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 150 | #define CONFIG_SYS_ALT_MEMTEST | |
| 151 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 152 | ||
| 2a9fab82 SX |
153 | /* |
| 154 | * Config the L3 Cache as L3 SRAM | |
| 155 | */ | |
| 156 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
| 157 | #ifdef CONFIG_PHYS_64BIT | |
| 158 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) | |
| 159 | #else | |
| 160 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
| 161 | #endif | |
| 162 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
| 163 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
| 164 | ||
| d1712369 KG |
165 | #ifdef CONFIG_PHYS_64BIT |
| 166 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 167 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 168 | #endif | |
| 169 | ||
| 170 | /* EEPROM */ | |
| 171 | #define CONFIG_ID_EEPROM | |
| 172 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 173 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 174 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 175 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 176 | ||
| 177 | /* | |
| 178 | * DDR Setup | |
| 179 | */ | |
| 180 | #define CONFIG_VERY_BIG_RAM | |
| 181 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 182 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 183 | ||
| 184 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 90870d98 | 185 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| d1712369 KG |
186 | |
| 187 | #define CONFIG_DDR_SPD | |
| 5614e71b | 188 | #define CONFIG_SYS_FSL_DDR3 |
| d1712369 | 189 | |
| d1712369 KG |
190 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| 191 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 192 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| e02aea61 | 193 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
| 28a96671 | 194 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
| d1712369 KG |
195 | |
| 196 | /* | |
| 197 | * Local Bus Definitions | |
| 198 | */ | |
| 199 | ||
| 200 | /* Set the local bus clock 1/8 of platform clock */ | |
| 201 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
| 202 | ||
| 203 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
| 204 | #ifdef CONFIG_PHYS_64BIT | |
| 205 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
| 206 | #else | |
| 207 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 208 | #endif | |
| 209 | ||
| 374a235d | 210 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
| 7ee41107 | 211 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ |
| 374a235d SX |
212 | | BR_PS_16 | BR_V) |
| 213 | #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
| d1712369 KG |
214 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) |
| 215 | ||
| 216 | #define CONFIG_SYS_BR1_PRELIM \ | |
| 217 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
| 218 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
| 219 | ||
| d1712369 KG |
220 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
| 221 | #ifdef CONFIG_PHYS_64BIT | |
| 222 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
| 223 | #else | |
| 224 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
| 225 | #endif | |
| 226 | ||
| 227 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
| 228 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
| 229 | ||
| 230 | #define PIXIS_LBMAP_SWITCH 7 | |
| 231 | #define PIXIS_LBMAP_MASK 0xf0 | |
| 232 | #define PIXIS_LBMAP_SHIFT 4 | |
| 233 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
| 234 | ||
| 235 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 236 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 237 | ||
| 238 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 239 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 240 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 241 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 242 | ||
| 14d0a02a | 243 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| d1712369 | 244 | |
| 2a9fab82 SX |
245 | #if defined(CONFIG_RAMBOOT_PBL) |
| 246 | #define CONFIG_SYS_RAMBOOT | |
| 247 | #endif | |
| 248 | ||
| e02aea61 | 249 | /* Nand Flash */ |
| e02aea61 KG |
250 | #ifdef CONFIG_NAND_FSL_ELBC |
| 251 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
| 252 | #ifdef CONFIG_PHYS_64BIT | |
| 253 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| 254 | #else | |
| 255 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 256 | #endif | |
| 257 | ||
| 258 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
| 259 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| e02aea61 KG |
260 | #define CONFIG_CMD_NAND |
| 261 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 262 | ||
| 263 | /* NAND flash config */ | |
| 264 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 265 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 266 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 267 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 268 | | BR_V) /* valid */ | |
| 269 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
| 270 | | OR_FCM_PGS /* Large Page*/ \ | |
| 271 | | OR_FCM_CSCT \ | |
| 272 | | OR_FCM_CST \ | |
| 273 | | OR_FCM_CHT \ | |
| 274 | | OR_FCM_SCY_1 \ | |
| 275 | | OR_FCM_TRLX \ | |
| 276 | | OR_FCM_EHTR) | |
| 277 | ||
| 374a235d SX |
278 | #ifdef CONFIG_NAND |
| 279 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
| 280 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 281 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 282 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
| 283 | #else | |
| 284 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 285 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
| 286 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
| 287 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 288 | #endif | |
| 374a235d SX |
289 | #else |
| 290 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 291 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
| c6d33901 | 292 | #endif /* CONFIG_NAND_FSL_ELBC */ |
| e02aea61 | 293 | |
| d1712369 KG |
294 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 295 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 296 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
| 297 | ||
| 298 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 299 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 300 | #define CONFIG_MISC_INIT_R | |
| 301 | ||
| 302 | #define CONFIG_HWCONFIG | |
| 303 | ||
| 304 | /* define to use L1 as initial stack */ | |
| 305 | #define CONFIG_L1_INIT_RAM | |
| 306 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 307 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 308 | #ifdef CONFIG_PHYS_64BIT | |
| 309 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| 310 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
| 311 | /* The assembler doesn't like typecast */ | |
| 312 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 313 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 314 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 315 | #else | |
| 316 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
| 317 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
| 318 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
| 319 | #endif | |
| 553f0982 | 320 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| d1712369 | 321 | |
| 25ddd1fb | 322 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| d1712369 KG |
323 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 324 | ||
| 9307cbab | 325 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| d1712369 KG |
326 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| 327 | ||
| 328 | /* Serial Port - controlled on board with jumper J8 | |
| 329 | * open - index 2 | |
| 330 | * shorted - index 1 | |
| 331 | */ | |
| 332 | #define CONFIG_CONS_INDEX 1 | |
| 333 | #define CONFIG_SYS_NS16550 | |
| 334 | #define CONFIG_SYS_NS16550_SERIAL | |
| 335 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 336 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 337 | ||
| 338 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 339 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 340 | ||
| 341 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 342 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 343 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 344 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 345 | ||
| 346 | /* Use the HUSH parser */ | |
| 347 | #define CONFIG_SYS_HUSH_PARSER | |
| d1712369 KG |
348 | |
| 349 | /* pass open firmware flat tree */ | |
| 350 | #define CONFIG_OF_LIBFDT | |
| 351 | #define CONFIG_OF_BOARD_SETUP | |
| 352 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 353 | ||
| 354 | /* new uImage format support */ | |
| 355 | #define CONFIG_FIT | |
| 356 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
| 357 | ||
| 358 | /* I2C */ | |
| 00f792e0 HS |
359 | #define CONFIG_SYS_I2C |
| 360 | #define CONFIG_SYS_I2C_FSL | |
| 361 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 362 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 363 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
| 364 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 365 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 366 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
| d1712369 KG |
367 | |
| 368 | /* | |
| 369 | * RapidIO | |
| 370 | */ | |
| a09b9b68 | 371 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
| d1712369 | 372 | #ifdef CONFIG_PHYS_64BIT |
| a09b9b68 | 373 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
| d1712369 | 374 | #else |
| a09b9b68 | 375 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
| d1712369 | 376 | #endif |
| a09b9b68 | 377 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
| d1712369 | 378 | |
| a09b9b68 | 379 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
| d1712369 | 380 | #ifdef CONFIG_PHYS_64BIT |
| a09b9b68 | 381 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
| d1712369 | 382 | #else |
| a09b9b68 | 383 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 |
| d1712369 | 384 | #endif |
| a09b9b68 | 385 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
| d1712369 | 386 | |
| 5ffa88ec LG |
387 | /* |
| 388 | * for slave u-boot IMAGE instored in master memory space, | |
| 389 | * PHYS must be aligned based on the SIZE | |
| 390 | */ | |
| e4911815 LG |
391 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 392 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
| 393 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
| 394 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
| 3f1af81b | 395 | /* |
| ff65f126 | 396 | * for slave UCODE and ENV instored in master memory space, |
| 3f1af81b LG |
397 | * PHYS must be aligned based on the SIZE |
| 398 | */ | |
| e4911815 | 399 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| b5f7c873 LG |
400 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 401 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
| ff65f126 | 402 | |
| 5056c8e0 | 403 | /* slave core release by master*/ |
| b5f7c873 LG |
404 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
| 405 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
| 5ffa88ec | 406 | |
| 292dc6c5 | 407 | /* |
| 461632bd | 408 | * SRIO_PCIE_BOOT - SLAVE |
| 292dc6c5 | 409 | */ |
| 461632bd LG |
410 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
| 411 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
| 412 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
| 413 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
| 292dc6c5 LG |
414 | #endif |
| 415 | ||
| 2dd3095d SX |
416 | /* |
| 417 | * eSPI - Enhanced SPI | |
| 418 | */ | |
| 419 | #define CONFIG_FSL_ESPI | |
| 2dd3095d SX |
420 | #define CONFIG_SPI_FLASH_SPANSION |
| 421 | #define CONFIG_CMD_SF | |
| 422 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 423 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 424 | ||
| d1712369 KG |
425 | /* |
| 426 | * General PCI | |
| 427 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 428 | */ | |
| 429 | ||
| 430 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 431 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 432 | #ifdef CONFIG_PHYS_64BIT | |
| 433 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 434 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 435 | #else | |
| 436 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 437 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
| 438 | #endif | |
| 439 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 440 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
| 441 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 442 | #ifdef CONFIG_PHYS_64BIT | |
| 443 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
| 444 | #else | |
| 445 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
| 446 | #endif | |
| 447 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 448 | ||
| 449 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 450 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| 451 | #ifdef CONFIG_PHYS_64BIT | |
| 452 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
| 453 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 454 | #else | |
| 455 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 456 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 457 | #endif | |
| 458 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 459 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
| 460 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 461 | #ifdef CONFIG_PHYS_64BIT | |
| 462 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
| 463 | #else | |
| 464 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
| 465 | #endif | |
| 466 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 467 | ||
| 468 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 02bb4989 | 469 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
| d1712369 KG |
470 | #ifdef CONFIG_PHYS_64BIT |
| 471 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 472 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
| 473 | #else | |
| 474 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
| 475 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
| 476 | #endif | |
| 477 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
| 478 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
| 479 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 480 | #ifdef CONFIG_PHYS_64BIT | |
| 481 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
| 482 | #else | |
| 483 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
| 484 | #endif | |
| 485 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 486 | ||
| 1bf8e9fd KG |
487 | /* controller 4, Base address 203000 */ |
| 488 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
| 489 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
| 490 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
| 491 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
| 492 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
| 493 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
| 494 | ||
| d1712369 | 495 | /* Qman/Bman */ |
| 24995d82 | 496 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
| d1712369 KG |
497 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
| 498 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
| 499 | #ifdef CONFIG_PHYS_64BIT | |
| 500 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 501 | #else | |
| 502 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
| 503 | #endif | |
| 504 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
| 3fa66db4 JL |
505 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 506 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 507 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 508 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 509 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 510 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 511 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 512 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| d1712369 KG |
513 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
| 514 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
| 515 | #ifdef CONFIG_PHYS_64BIT | |
| 516 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
| 517 | #else | |
| 518 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
| 519 | #endif | |
| 520 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
| 3fa66db4 JL |
521 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 522 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 523 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 524 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 525 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 526 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 527 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 528 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| d1712369 KG |
529 | |
| 530 | #define CONFIG_SYS_DPAA_FMAN | |
| 531 | #define CONFIG_SYS_DPAA_PME | |
| 532 | /* Default address of microcode for the Linux Fman driver */ | |
| ffadc441 TT |
533 | #if defined(CONFIG_SPIFLASH) |
| 534 | /* | |
| 535 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 536 | * env, so we got 0x110000. | |
| 537 | */ | |
| f2717b47 | 538 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
| dcf1d774 | 539 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| ffadc441 TT |
540 | #elif defined(CONFIG_SDCARD) |
| 541 | /* | |
| 542 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| e222b1f3 PK |
543 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
| 544 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
| ffadc441 | 545 | */ |
| f2717b47 | 546 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
| dcf1d774 | 547 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
| ffadc441 | 548 | #elif defined(CONFIG_NAND) |
| f2717b47 | 549 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
| dcf1d774 | 550 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 461632bd | 551 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 292dc6c5 LG |
552 | /* |
| 553 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
| 554 | * in two corenet boards, slave's ucode could be stored in master's memory | |
| 555 | * space, the address can be mapped from slave TLB->slave LAW-> | |
| 461632bd LG |
556 | * slave SRIO or PCIE outbound window->master inbound window-> |
| 557 | * master LAW->the ucode address in master's memory space. | |
| 292dc6c5 LG |
558 | */ |
| 559 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
| dcf1d774 | 560 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
| d1712369 | 561 | #else |
| f2717b47 | 562 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| dcf1d774 | 563 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| d1712369 | 564 | #endif |
| f2717b47 TT |
565 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 566 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| d1712369 KG |
567 | |
| 568 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 569 | #define CONFIG_FMAN_ENET | |
| 2915609a AF |
570 | #define CONFIG_PHYLIB_10G |
| 571 | #define CONFIG_PHY_VITESSE | |
| 572 | #define CONFIG_PHY_TERANETICS | |
| d1712369 KG |
573 | #endif |
| 574 | ||
| 575 | #ifdef CONFIG_PCI | |
| 842033e6 | 576 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| d1712369 | 577 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| d1712369 | 578 | |
| d1712369 KG |
579 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 580 | #define CONFIG_DOS_PARTITION | |
| 581 | #endif /* CONFIG_PCI */ | |
| 582 | ||
| 583 | /* SATA */ | |
| 584 | #ifdef CONFIG_FSL_SATA_V2 | |
| 585 | #define CONFIG_LIBATA | |
| 586 | #define CONFIG_FSL_SATA | |
| 587 | ||
| 588 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 589 | #define CONFIG_SATA1 | |
| 590 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 591 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 592 | #define CONFIG_SATA2 | |
| 593 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 594 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 595 | ||
| 596 | #define CONFIG_LBA48 | |
| 597 | #define CONFIG_CMD_SATA | |
| 598 | #define CONFIG_DOS_PARTITION | |
| 599 | #define CONFIG_CMD_EXT2 | |
| 600 | #endif | |
| 601 | ||
| 602 | #ifdef CONFIG_FMAN_ENET | |
| 603 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
| 604 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
| 605 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
| 606 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
| 607 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
| 608 | ||
| d1712369 KG |
609 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c |
| 610 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
| 611 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
| 612 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
| 613 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
| d1712369 KG |
614 | |
| 615 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
| 616 | #define CONFIG_MII /* MII PHY management */ | |
| 617 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
| 618 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 619 | #endif | |
| 620 | ||
| 621 | /* | |
| 622 | * Environment | |
| 623 | */ | |
| d1712369 KG |
624 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 625 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 626 | ||
| 627 | /* | |
| 628 | * Command line configuration. | |
| 629 | */ | |
| a000b795 | 630 | #define CONFIG_CMD_DHCP |
| d1712369 KG |
631 | #define CONFIG_CMD_ELF |
| 632 | #define CONFIG_CMD_ERRATA | |
| a000b795 | 633 | #define CONFIG_CMD_GREPENV |
| d1712369 KG |
634 | #define CONFIG_CMD_IRQ |
| 635 | #define CONFIG_CMD_I2C | |
| 636 | #define CONFIG_CMD_MII | |
| 637 | #define CONFIG_CMD_PING | |
| 9570cbda | 638 | #define CONFIG_CMD_REGINFO |
| d1712369 KG |
639 | |
| 640 | #ifdef CONFIG_PCI | |
| 641 | #define CONFIG_CMD_PCI | |
| d1712369 KG |
642 | #endif |
| 643 | ||
| 644 | /* | |
| 645 | * USB | |
| 646 | */ | |
| 3d7506fa | 647 | #define CONFIG_HAS_FSL_DR_USB |
| 648 | #define CONFIG_HAS_FSL_MPH_USB | |
| 649 | ||
| 650 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) | |
| d1712369 KG |
651 | #define CONFIG_CMD_USB |
| 652 | #define CONFIG_USB_STORAGE | |
| 653 | #define CONFIG_USB_EHCI | |
| 654 | #define CONFIG_USB_EHCI_FSL | |
| 655 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 656 | #define CONFIG_CMD_EXT2 | |
| 3d7506fa | 657 | #endif |
| d1712369 | 658 | |
| d1712369 KG |
659 | #ifdef CONFIG_MMC |
| 660 | #define CONFIG_FSL_ESDHC | |
| 661 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 662 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
| 663 | #define CONFIG_CMD_MMC | |
| 664 | #define CONFIG_GENERIC_MMC | |
| 665 | #define CONFIG_CMD_EXT2 | |
| 666 | #define CONFIG_CMD_FAT | |
| 667 | #define CONFIG_DOS_PARTITION | |
| 668 | #endif | |
| 669 | ||
| 737537ef RG |
670 | /* Hash command with SHA acceleration supported in hardware */ |
| 671 | #ifdef CONFIG_FSL_CAAM | |
| 672 | #define CONFIG_CMD_HASH | |
| 673 | #define CONFIG_SHA_HW_ACCEL | |
| 674 | #endif | |
| 675 | ||
| d1712369 KG |
676 | /* |
| 677 | * Miscellaneous configurable options | |
| 678 | */ | |
| 679 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 680 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 681 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 682 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| d1712369 KG |
683 | #ifdef CONFIG_CMD_KGDB |
| 684 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 685 | #else | |
| 686 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 687 | #endif | |
| 688 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| 689 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 690 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| d1712369 KG |
691 | |
| 692 | /* | |
| 693 | * For booting Linux, the board info and command line data | |
| a832ac41 | 694 | * have to be in the first 64 MB of memory, since this is |
| d1712369 KG |
695 | * the maximum mapped by the Linux kernel during initialization. |
| 696 | */ | |
| a832ac41 KG |
697 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 698 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| d1712369 | 699 | |
| d1712369 KG |
700 | #ifdef CONFIG_CMD_KGDB |
| 701 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| d1712369 KG |
702 | #endif |
| 703 | ||
| 704 | /* | |
| 705 | * Environment Configuration | |
| 706 | */ | |
| 8b3637c6 | 707 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 708 | #define CONFIG_BOOTFILE "uImage" |
| d1712369 KG |
709 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 710 | ||
| 711 | /* default location for tftp and bootm */ | |
| 712 | #define CONFIG_LOADADDR 1000000 | |
| 713 | ||
| 714 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 715 | ||
| 716 | #define CONFIG_BAUDRATE 115200 | |
| 717 | ||
| 055ce080 | 718 | #ifdef CONFIG_P4080DS |
| 68d4230c RM |
719 | #define __USB_PHY_TYPE ulpi |
| 720 | #else | |
| 721 | #define __USB_PHY_TYPE utmi | |
| 722 | #endif | |
| 723 | ||
| d1712369 | 724 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| c2b3b640 | 725 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
| 68d4230c | 726 | "bank_intlv=cs0_cs1;" \ |
| 55964bb6 | 727 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ |
| 728 | "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| d1712369 | 729 | "netdev=eth0\0" \ |
| 5368c55d MV |
730 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 731 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| c2b3b640 EM |
732 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 733 | "protect off $ubootaddr +$filesize && " \ | |
| 734 | "erase $ubootaddr +$filesize && " \ | |
| 735 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 736 | "protect on $ubootaddr +$filesize && " \ | |
| 737 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| d1712369 KG |
738 | "consoledev=ttyS0\0" \ |
| 739 | "ramdiskaddr=2000000\0" \ | |
| 740 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
| 741 | "fdtaddr=c00000\0" \ | |
| 742 | "fdtfile=p4080ds/p4080ds.dtb\0" \ | |
| 3246584d | 743 | "bdev=sda3\0" |
| d1712369 KG |
744 | |
| 745 | #define CONFIG_HDBOOT \ | |
| 746 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 747 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 748 | "tftp $loadaddr $bootfile;" \ | |
| 749 | "tftp $fdtaddr $fdtfile;" \ | |
| 750 | "bootm $loadaddr - $fdtaddr" | |
| 751 | ||
| 752 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 753 | "setenv bootargs root=/dev/nfs rw " \ | |
| 754 | "nfsroot=$serverip:$rootpath " \ | |
| 755 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 756 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 757 | "tftp $loadaddr $bootfile;" \ | |
| 758 | "tftp $fdtaddr $fdtfile;" \ | |
| 759 | "bootm $loadaddr - $fdtaddr" | |
| 760 | ||
| 761 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 762 | "setenv bootargs root=/dev/ram rw " \ | |
| 763 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 764 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 765 | "tftp $loadaddr $bootfile;" \ | |
| 766 | "tftp $fdtaddr $fdtfile;" \ | |
| 767 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 768 | ||
| 769 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 770 | ||
| 7065b7d4 | 771 | #include <asm/fsl_secure_boot.h> |
| 7065b7d4 | 772 | |
| 789490b6 RG |
773 | #ifdef CONFIG_SECURE_BOOT |
| 774 | #define CONFIG_CMD_BLOB | |
| 775 | #endif | |
| 776 | ||
| d1712369 | 777 | #endif /* __CONFIG_H */ |