]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/dbau1x00.h
net: Move the CMD_NET config to defconfigs
[people/ms/u-boot.git] / include / configs / dbau1x00.h
CommitLineData
5da627a4
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
5da627a4
WD
6 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
5da627a4 15#define CONFIG_DBAU1X00 1
8bde63eb 16#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4 17
74368693
DS
18#define CONFIG_DISPLAY_BOARDINFO
19
a2663ea4 20#ifdef CONFIG_DBAU1000
5da627a4 21/* Also known as Merlot */
8bde63eb 22#define CONFIG_SOC_AU1000 1
a2663ea4
WD
23#else
24#ifdef CONFIG_DBAU1100
8bde63eb 25#define CONFIG_SOC_AU1100 1
a2663ea4
WD
26#else
27#ifdef CONFIG_DBAU1500
8bde63eb 28#define CONFIG_SOC_AU1500 1
d4ca31c4 29#else
ff36fd85
WD
30#ifdef CONFIG_DBAU1550
31/* Cabernet */
8bde63eb 32#define CONFIG_SOC_AU1550 1
ff36fd85 33#else
a2663ea4
WD
34#error "No valid board set"
35#endif
36#endif
37#endif
ff36fd85 38#endif
5da627a4 39
5da627a4
WD
40#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
41
42#define CONFIG_BAUDRATE 115200
43
44/* valid baudrates */
5da627a4
WD
45
46#define CONFIG_TIMESTAMP /* Print image info with timestamp */
47#undef CONFIG_BOOTARGS
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
fe126d8b
WD
50 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
5da627a4
WD
52 "panic=1\0" \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b 54 "load=tftp 80500000 ${u-boot}\0" \
5da627a4 55 ""
ff36fd85
WD
56
57#ifdef CONFIG_DBAU1550
58/* Boot from flash by default, revert to bootp */
59#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85 60#else /* CONFIG_DBAU1550 */
ad88297e 61#define CONFIG_BOOTCOMMAND "bootp;bootm"
ff36fd85
WD
62#endif /* CONFIG_DBAU1550 */
63
ab999ba1 64
80ff4f99
JL
65/*
66 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
ab999ba1
JL
74/*
75 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
79#undef CONFIG_CMD_BDI
80#undef CONFIG_CMD_BEDBUG
81#undef CONFIG_CMD_ELF
bdab39d3 82#undef CONFIG_CMD_SAVEENV
ab999ba1
JL
83#undef CONFIG_CMD_FAT
84#undef CONFIG_CMD_FPGA
85#undef CONFIG_CMD_MII
86#undef CONFIG_CMD_RUN
87
88
89#ifdef CONFIG_DBAU1550
90
91#define CONFIG_CMD_FLASH
92#define CONFIG_CMD_LOADB
ab999ba1
JL
93
94#undef CONFIG_CMD_I2C
95#undef CONFIG_CMD_IDE
96#undef CONFIG_CMD_NFS
97#undef CONFIG_CMD_PCMCIA
98
99#else
100
101#define CONFIG_CMD_IDE
102#define CONFIG_CMD_DHCP
103
104#undef CONFIG_CMD_FLASH
105#undef CONFIG_CMD_LOADB
106#undef CONFIG_CMD_LOADS
107
108#endif
109
5da627a4
WD
110
111/*
112 * Miscellaneous configurable options
113 */
6d0f6bcf 114#define CONFIG_SYS_LONGHELP /* undef to save memory */
ff36fd85 115
6d0f6bcf 116#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
ff36fd85 117
6d0f6bcf
JCPV
118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
120#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
5da627a4 121
6d0f6bcf 122#define CONFIG_SYS_MALLOC_LEN 128*1024
5da627a4 123
6d0f6bcf 124#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
5da627a4 125
6d0f6bcf 126#define CONFIG_SYS_MHZ 396
ff36fd85 127
6d0f6bcf 128#if (CONFIG_SYS_MHZ % 12) != 0
ff36fd85
WD
129#error "Invalid CPU frequency - must be multiple of 12!"
130#endif
131
6d0f6bcf 132#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
a55d4817 133
6d0f6bcf 134#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
5da627a4 135
6d0f6bcf 136#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
5da627a4 137
6d0f6bcf
JCPV
138#define CONFIG_SYS_MEMTEST_START 0x80100000
139#define CONFIG_SYS_MEMTEST_END 0x80800000
5da627a4
WD
140
141/*-----------------------------------------------------------------------
142 * FLASH and environment organization
143 */
ff36fd85
WD
144#ifdef CONFIG_DBAU1550
145
6d0f6bcf
JCPV
146#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
147#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
ff36fd85
WD
148
149#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
150#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
151
ff36fd85
WD
152#else /* CONFIG_DBAU1550 */
153
6d0f6bcf
JCPV
154#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
155#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
5da627a4
WD
156
157#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
158#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
159
ff36fd85
WD
160#endif /* CONFIG_DBAU1550 */
161
6d0f6bcf 162#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e 163
6d0f6bcf 164#define CONFIG_SYS_FLASH_CFI 1
00b1883a 165#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85 166
5da627a4 167/* The following #defines are needed to get flash environment right */
14d0a02a 168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf 169#define CONFIG_SYS_MONITOR_LEN (192 << 10)
5da627a4 170
6d0f6bcf 171#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
5da627a4
WD
172
173/* We boot from this flash, selected with dip switch */
6d0f6bcf 174#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
5da627a4
WD
175
176/* timeout values are in ticks */
6d0f6bcf
JCPV
177#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
178#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
5da627a4 179
93f6d725 180#define CONFIG_ENV_IS_NOWHERE 1
5da627a4
WD
181
182/* Address and size of Primary Environment Sector */
0e8d1586
JCPV
183#define CONFIG_ENV_ADDR 0xB0030000
184#define CONFIG_ENV_SIZE 0x10000
5da627a4
WD
185
186#define CONFIG_FLASH_16BIT
187
188#define CONFIG_NR_DRAM_BANKS 2
189
5da627a4 190
ff36fd85
WD
191#ifdef CONFIG_DBAU1550
192#define MEM_SIZE 192
193#else
194#define MEM_SIZE 64
195#endif
196
5da627a4
WD
197#define CONFIG_MEMSIZE_IN_BYTES
198
ff36fd85 199#ifndef CONFIG_DBAU1550
5da627a4 200/*---ATA PCMCIA ------------------------------------*/
6d0f6bcf
JCPV
201#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
202#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
5da627a4
WD
203#define CONFIG_PCMCIA_SLOT_A
204
205#define CONFIG_ATAPI 1
206#define CONFIG_MAC_PARTITION 1
207
208/* We run CF in "true ide" mode or a harddrive via pcmcia */
209#define CONFIG_IDE_PCMCIA 1
210
211/* We only support one slot for now */
6d0f6bcf
JCPV
212#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
213#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
5da627a4
WD
214
215#undef CONFIG_IDE_LED /* LED for ide not supported */
216#undef CONFIG_IDE_RESET /* reset for ide not supported */
217
6d0f6bcf 218#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5da627a4 219
6d0f6bcf 220#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
5da627a4 221
d4ca31c4 222/* Offset for data I/O */
6d0f6bcf 223#define CONFIG_SYS_ATA_DATA_OFFSET 8
5da627a4
WD
224
225/* Offset for normal register accesses */
6d0f6bcf 226#define CONFIG_SYS_ATA_REG_OFFSET 0
5da627a4
WD
227
228/* Offset for alternate registers */
6d0f6bcf 229#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ff36fd85 230#endif /* CONFIG_DBAU1550 */
5da627a4
WD
231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
6d0f6bcf
JCPV
235#define CONFIG_SYS_DCACHE_SIZE 16384
236#define CONFIG_SYS_ICACHE_SIZE 16384
237#define CONFIG_SYS_CACHELINE_SIZE 32
5da627a4 238
5da627a4 239#endif /* __CONFIG_H */