]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/dbau1x00.h
Convert CONFIG_BOOTP_BOOTPATH et al to Kconfig
[people/ms/u-boot.git] / include / configs / dbau1x00.h
CommitLineData
5da627a4
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
5da627a4
WD
6 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
5da627a4 15#define CONFIG_DBAU1X00 1
8bde63eb 16#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4 17
a2663ea4 18#ifdef CONFIG_DBAU1000
5da627a4 19/* Also known as Merlot */
8bde63eb 20#define CONFIG_SOC_AU1000 1
a2663ea4
WD
21#else
22#ifdef CONFIG_DBAU1100
8bde63eb 23#define CONFIG_SOC_AU1100 1
a2663ea4
WD
24#else
25#ifdef CONFIG_DBAU1500
8bde63eb 26#define CONFIG_SOC_AU1500 1
d4ca31c4 27#else
ff36fd85
WD
28#ifdef CONFIG_DBAU1550
29/* Cabernet */
8bde63eb 30#define CONFIG_SOC_AU1550 1
ff36fd85 31#else
a2663ea4
WD
32#error "No valid board set"
33#endif
34#endif
35#endif
ff36fd85 36#endif
5da627a4 37
5da627a4 38/* valid baudrates */
5da627a4
WD
39
40#define CONFIG_TIMESTAMP /* Print image info with timestamp */
5da627a4
WD
41
42#define CONFIG_EXTRA_ENV_SETTINGS \
fe126d8b
WD
43 "addmisc=setenv bootargs ${bootargs} " \
44 "console=ttyS0,${baudrate} " \
5da627a4
WD
45 "panic=1\0" \
46 "bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b 47 "load=tftp 80500000 ${u-boot}\0" \
5da627a4 48 ""
ff36fd85
WD
49
50#ifdef CONFIG_DBAU1550
51/* Boot from flash by default, revert to bootp */
52#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85 53#else /* CONFIG_DBAU1550 */
ad88297e 54#define CONFIG_BOOTCOMMAND "bootp;bootm"
ff36fd85
WD
55#endif /* CONFIG_DBAU1550 */
56
80ff4f99
JL
57/*
58 * BOOTP options
59 */
60#define CONFIG_BOOTP_BOOTFILESIZE
80ff4f99 61
ab999ba1
JL
62/*
63 * Command line configuration.
64 */
ab999ba1 65
5da627a4
WD
66/*
67 * Miscellaneous configurable options
68 */
ff36fd85 69
6d0f6bcf 70#define CONFIG_SYS_MALLOC_LEN 128*1024
5da627a4 71
6d0f6bcf 72#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
5da627a4 73
6d0f6bcf 74#define CONFIG_SYS_MHZ 396
ff36fd85 75
6d0f6bcf 76#if (CONFIG_SYS_MHZ % 12) != 0
ff36fd85
WD
77#error "Invalid CPU frequency - must be multiple of 12!"
78#endif
79
6d0f6bcf 80#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
a55d4817 81
6d0f6bcf 82#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
5da627a4 83
6d0f6bcf 84#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
5da627a4 85
6d0f6bcf
JCPV
86#define CONFIG_SYS_MEMTEST_START 0x80100000
87#define CONFIG_SYS_MEMTEST_END 0x80800000
5da627a4
WD
88
89/*-----------------------------------------------------------------------
90 * FLASH and environment organization
91 */
ff36fd85
WD
92#ifdef CONFIG_DBAU1550
93
6d0f6bcf
JCPV
94#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
95#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
ff36fd85
WD
96
97#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
98#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
99
ff36fd85
WD
100#else /* CONFIG_DBAU1550 */
101
6d0f6bcf
JCPV
102#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
103#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
5da627a4
WD
104
105#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
106#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
107
ff36fd85
WD
108#endif /* CONFIG_DBAU1550 */
109
6d0f6bcf 110#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e 111
6d0f6bcf 112#define CONFIG_SYS_FLASH_CFI 1
00b1883a 113#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85 114
14d0a02a 115#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf 116#define CONFIG_SYS_MONITOR_LEN (192 << 10)
5da627a4 117
6d0f6bcf 118#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
5da627a4
WD
119
120/* We boot from this flash, selected with dip switch */
6d0f6bcf 121#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
5da627a4
WD
122
123/* timeout values are in ticks */
6d0f6bcf
JCPV
124#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
125#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
5da627a4 126
5da627a4 127/* Address and size of Primary Environment Sector */
0e8d1586
JCPV
128#define CONFIG_ENV_ADDR 0xB0030000
129#define CONFIG_ENV_SIZE 0x10000
5da627a4
WD
130
131#define CONFIG_FLASH_16BIT
132
133#define CONFIG_NR_DRAM_BANKS 2
134
ff36fd85
WD
135#ifdef CONFIG_DBAU1550
136#define MEM_SIZE 192
137#else
138#define MEM_SIZE 64
139#endif
140
5da627a4
WD
141#define CONFIG_MEMSIZE_IN_BYTES
142
ff36fd85 143#ifndef CONFIG_DBAU1550
5da627a4 144/*---ATA PCMCIA ------------------------------------*/
6d0f6bcf
JCPV
145#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
146#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
5da627a4
WD
147#define CONFIG_PCMCIA_SLOT_A
148
149#define CONFIG_ATAPI 1
5da627a4
WD
150
151/* We run CF in "true ide" mode or a harddrive via pcmcia */
152#define CONFIG_IDE_PCMCIA 1
153
154/* We only support one slot for now */
6d0f6bcf
JCPV
155#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
156#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
5da627a4 157
5da627a4
WD
158#undef CONFIG_IDE_RESET /* reset for ide not supported */
159
6d0f6bcf 160#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5da627a4 161
6d0f6bcf 162#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
5da627a4 163
d4ca31c4 164/* Offset for data I/O */
6d0f6bcf 165#define CONFIG_SYS_ATA_DATA_OFFSET 8
5da627a4
WD
166
167/* Offset for normal register accesses */
6d0f6bcf 168#define CONFIG_SYS_ATA_REG_OFFSET 0
5da627a4
WD
169
170/* Offset for alternate registers */
6d0f6bcf 171#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ff36fd85 172#endif /* CONFIG_DBAU1550 */
5da627a4 173
5da627a4 174#endif /* __CONFIG_H */