[people/ms/u-boot.git] / include / configs / debris.h

/*
 * (C) Copyright 2001, 2002
 * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

/* Environments */

/* bootargs */
#define CONFIG_BOOTARGS \
	"console=ttyS0,9600 init=/linuxrc " \
	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
	"/tftpboot/target " \
	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
	"255.255.255.0:debris:eth0:none " \
	"mtdparts=phys:12m(root),-(kernel)"

/* bootcmd */
#define CONFIG_BOOTCOMMAND \
	"tftp 800000 pImage; " \
	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	"${netmask}:${hostname}:eth0:none " \
	"mtdparts=phys:12m(root),-(kernel); " \
	"bootm 800000"

/* bootdelay */
#define CONFIG_BOOTDELAY	5	/* autoboot 5s */

/* baudrate */
#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/

/* loads_echo */
#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */

/* ethaddr */
#undef CONFIG_ETHADDR

/* eth2addr */
#undef CONFIG_ETH2ADDR

/* eth3addr */
#undef CONFIG_ETH3ADDR

/* ipaddr */
#define CONFIG_IPADDR	192.168.0.2

/* serverip */
#define CONFIG_SERVERIP	192.168.0.1

/* autoload */
#undef CONFIG_SYS_AUTOLOAD

/* rootpath */
#define CONFIG_ROOTPATH "/tftpboot/target"

/* gatewayip */
#define CONFIG_GATEWAYIP 192.168.0.1

/* netmask */
#define CONFIG_NETMASK 255.255.255.0

/* hostname */
#define CONFIG_HOSTNAME debris

/* bootfile */
#define CONFIG_BOOTFILE "pImage"

/* loadaddr */
#define CONFIG_LOADADDR 800000

/* preboot */
#undef CONFIG_PREBOOT

/* clocks_in_mhz */
#undef CONFIG_CLOCKS_IN_MHZ


/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_DEBRIS		1

#if 0
#define USE_DINK32		1
#else
#undef USE_DINK32
#endif

#define CONFIG_CONS_INDEX       1
#define CONFIG_BAUDRATE		9600
#define CONFIG_DRAM_SPEED	100		/* MHz */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_KGDB
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SDRAM


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP

#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
#define CONFIG_EEPRO100_SROM_WRITE

#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET0_MEMADDR	0x80000000
#define	PCI_ENET1_IOADDR	0x81000000
#define	PCI_ENET1_MEMADDR	0x81000000
/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#if defined (USE_DINK32)
#define CONFIG_SYS_MONITOR_LEN		0x00040000
#define CONFIG_SYS_MONITOR_BASE	0x00090000
#define CONFIG_SYS_RAMBOOT		1
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		0x00040000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE


#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#endif

#define CONFIG_SYS_FLASH_BASE		0x7C000000
#define CONFIG_SYS_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
#define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */

/* Use first bank for JFFS2, second bank contains U-Boot.
 *
 * Note: fake mtd_id's used, no linux mtd map file.
 */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=debris-0"
#define MTDPARTS_DEFAULT	"mtdparts=debris-0:-(jffs2)"
*/

#define CONFIG_ENV_IS_IN_NVRAM      1
#define CONFIG_ENV_OVERWRITE     1
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
#define CONFIG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
#define CONFIG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xff000000

/*
 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
 * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
 */
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900

/*
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
#undef  CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly.  Please review!"
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
#define I2C_READ		((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
				else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
				else    iop->pdat &= ~0x00020000
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif /* CONFIG_SYS_I2C_SOFT */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		7372800

#define CONFIG_SYS_NS16550_COM1	0xFF080000
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_NS16550_COM1 + 8)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_NS16550_COM1 + 16)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_NS16550_COM1 + 24)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3

#define CONFIG_SYS_DLL_EXTEND		0x00
#define CONFIG_SYS_PCI_HOLD_DEL	0x20

#define CONFIG_SYS_ROMNAL	15	/* rom/flash next access time */
#define CONFIG_SYS_ROMFAL	31	/* rom/flash access time */

#define CONFIG_SYS_REFINT	430	/* # of clocks between CBR refresh cycles */

#define CONFIG_SYS_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */

/* the following are for SDRAM only*/
#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
#define CONFIG_SYS_REFREC	8	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT	4	/* data latency from read command	*/
#define CONFIG_SYS_PRETOACT	3	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE	5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#if 0
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
#endif

#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
#define CONFIG_SYS_EXTROM 1
#define CONFIG_SYS_REGDIMM 0


/* memory bank settings*/
/*
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x04000000
#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
#define CONFIG_SYS_BANK1_ENABLE	1
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0
/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0x75	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
#else
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* values according to the manual */

#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#define CONFIG_DISK_SPINUP_TIME 1000000

#endif	/* __CONFIG_H */
Commit	Line	Data
15647dc7 WD	1	/*
	2	* (C) Copyright 2001, 2002
	3	* Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
15647dc7 WD	6	*/
	7
	8	/* ------------------------------------------------------------------------- */
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
2ae18241 WD	17	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	18
15647dc7 WD	19	/* Environments */
	20
	21	/* bootargs */
	22	#define CONFIG_BOOTARGS \
	23	"console=ttyS0,9600 init=/linuxrc " \
	24	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
	25	"/tftpboot/target " \
	26	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
	27	"255.255.255.0:debris:eth0:none " \
	28	"mtdparts=phys:12m(root),-(kernel)"
	29
	30	/* bootcmd */
	31	#define CONFIG_BOOTCOMMAND \
	32	"tftp 800000 pImage; " \
	33	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
fe126d8b WD	34	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	35	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	36	"${netmask}:${hostname}:eth0:none " \
15647dc7 WD	37	"mtdparts=phys:12m(root),-(kernel); " \
	38	"bootm 800000"
	39
	40	/* bootdelay */
	41	#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
	42
	43	/* baudrate */
	44	#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
	45
	46	/* loads_echo */
	47	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
	48
	49	/* ethaddr */
	50	#undef CONFIG_ETHADDR
	51
	52	/* eth2addr */
	53	#undef CONFIG_ETH2ADDR
	54
	55	/* eth3addr */
	56	#undef CONFIG_ETH3ADDR
	57
	58	/* ipaddr */
	59	#define CONFIG_IPADDR 192.168.0.2
	60
	61	/* serverip */
	62	#define CONFIG_SERVERIP 192.168.0.1
	63
	64	/* autoload */
6d0f6bcf	65	#undef CONFIG_SYS_AUTOLOAD
15647dc7 WD	66
15647dc7 WD	67	/* rootpath */
8b3637c6	68	#define CONFIG_ROOTPATH "/tftpboot/target"
15647dc7 WD	69
	70	/* gatewayip */
	71	#define CONFIG_GATEWAYIP 192.168.0.1
	72
	73	/* netmask */
	74	#define CONFIG_NETMASK 255.255.255.0
	75
	76	/* hostname */
	77	#define CONFIG_HOSTNAME debris
	78
	79	/* bootfile */
b3f44c21	80	#define CONFIG_BOOTFILE "pImage"
15647dc7 WD	81
	82	/* loadaddr */
	83	#define CONFIG_LOADADDR 800000
	84
	85	/* preboot */
	86	#undef CONFIG_PREBOOT
	87
	88	/* clocks_in_mhz */
	89	#undef CONFIG_CLOCKS_IN_MHZ
	90
	91
	92	/*
	93	* High Level Configuration Options
	94	* (easy to change)
	95	*/
	96
	97	#define CONFIG_MPC824X 1
	98	#define CONFIG_MPC8245 1
	99	#define CONFIG_DEBRIS 1
	100
	101	#if 0
	102	#define USE_DINK32 1
	103	#else
	104	#undef USE_DINK32
	105	#endif
	106
	107	#define CONFIG_CONS_INDEX 1
	108	#define CONFIG_BAUDRATE 9600
	109	#define CONFIG_DRAM_SPEED 100 /* MHz */
	110
ab999ba1	111
80ff4f99 JL	112	/*
	113	* BOOTP options
	114	*/
	115	#define CONFIG_BOOTP_BOOTFILESIZE
	116	#define CONFIG_BOOTP_BOOTPATH
	117	#define CONFIG_BOOTP_GATEWAY
	118	#define CONFIG_BOOTP_HOSTNAME
	119
	120
ab999ba1 JL	121	/*
	122	* Command line configuration.
	123	*/
	124	#include <config_cmd_default.h>
	125
	126	#define CONFIG_CMD_ASKENV
	127	#define CONFIG_CMD_CACHE
	128	#define CONFIG_CMD_DATE
	129	#define CONFIG_CMD_DHCP
	130	#define CONFIG_CMD_DIAG
	131	#define CONFIG_CMD_EEPROM
	132	#define CONFIG_CMD_ELF
	133	#define CONFIG_CMD_I2C
	134	#define CONFIG_CMD_JFFS2
d060b00e	135	#define CONFIG_CMD_KGDB
ab999ba1 JL	136	#define CONFIG_CMD_PCI
	137	#define CONFIG_CMD_PING
	138	#define CONFIG_CMD_SAVES
	139	#define CONFIG_CMD_SDRAM
15647dc7 WD	140
	141
	142	/*
	143	* Miscellaneous configurable options
	144	*/
6d0f6bcf	145	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	146	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	147	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	148	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	149	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	150	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
15647dc7 WD	151
	152	/*-----------------------------------------------------------------------
	153	* PCI stuff
	154	*-----------------------------------------------------------------------
	155	*/
	156	#define CONFIG_PCI /* include pci support */
842033e6	157	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
15647dc7 WD	158	#define CONFIG_PCI_PNP
15647dc7 WD	159
15647dc7	160	#define CONFIG_EEPRO100
6d0f6bcf	161	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
15647dc7 WD	162	#define CONFIG_EEPRO100_SROM_WRITE
	163
	164	#define PCI_ENET0_IOADDR 0x80000000
	165	#define PCI_ENET0_MEMADDR 0x80000000
	166	#define PCI_ENET1_IOADDR 0x81000000
	167	#define PCI_ENET1_MEMADDR 0x81000000
	168	/*-----------------------------------------------------------------------
	169	* Start addresses for the final memory configuration
	170	* (Set up by the startup code)
6d0f6bcf	171	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
15647dc7	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	174	#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
7abf0c58	175	#define CONFIG_VERY_BIG_RAM
15647dc7	176
6d0f6bcf	177	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
15647dc7 WD	178
15647dc7 WD	179	#if defined (USE_DINK32)
6d0f6bcf JCPV	180	#define CONFIG_SYS_MONITOR_LEN 0x00040000
	181	#define CONFIG_SYS_MONITOR_BASE 0x00090000
	182	#define CONFIG_SYS_RAMBOOT 1
	183	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
553f0982	184	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
25ddd1fb	185	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	186	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
15647dc7	187	#else
6d0f6bcf JCPV	188	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	189	#define CONFIG_SYS_MONITOR_LEN 0x00040000
14d0a02a	190	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
15647dc7	191
15647dc7	192
6d0f6bcf	193	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	194	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	195	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
15647dc7 WD	196
	197	#endif
	198
6d0f6bcf JCPV	199	#define CONFIG_SYS_FLASH_BASE 0x7C000000
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_SIZE (1610241024) /* debris has tiny eeprom */
15647dc7	201
6d0f6bcf	202	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
15647dc7	203
6d0f6bcf JCPV	204	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	205	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
15647dc7	206
6d0f6bcf	207	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
15647dc7	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
6d0f6bcf JCPV	210	#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
15647dc7 WD	211	#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
15647dc7 WD	212
700a0c64 WD	213	/*
	214	* JFFS2 partitions
	215	*
	216	*/
	217	/* No command line, one static partition, whole device */
68d7d651	218	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	219	#define CONFIG_JFFS2_DEV "nor0"
	220	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	221	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	222
	223	/* mtdparts command line support */
	224
	225	/* Use first bank for JFFS2, second bank contains U-Boot.
	226	*
	227	* Note: fake mtd_id's used, no linux mtd map file.
	228	*/
	229	/*
68d7d651	230	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	231	#define MTDIDS_DEFAULT "nor0=debris-0"
	232	#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
	233	*/
15647dc7	234
9314cee6	235	#define CONFIG_ENV_IS_IN_NVRAM 1
15647dc7	236	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf	237	#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
0e8d1586 JCPV	238	#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
	239	#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
	240	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
15647dc7	241
6d0f6bcf	242	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
15647dc7 WD	243
15647dc7 WD	244	/*
6d0f6bcf	245	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
15647dc7 WD	246	* NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
15647dc7 WD	247	*/
6d0f6bcf	248	#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
15647dc7 WD	249
	250	/*
	251	* select i2c support configuration
	252	*
	253	* Supported configurations are {none, software, hardware} drivers.
	254	* If the software driver is chosen, there are some additional
	255	* configuration items that the driver uses to drive the port pins.
	256	*/
	257	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
ea818dbb	258	#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
6d0f6bcf JCPV	259	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	260	#define CONFIG_SYS_I2C_SLAVE 0x7F
15647dc7	261
ea818dbb	262	#ifdef CONFIG_SYS_I2C_SOFT
15647dc7	263	#error "Soft I2C is not configured properly. Please review!"
ea818dbb HS	264	#define CONFIG_SYS_I2C
	265	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	266	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
15647dc7 WD	267	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	268	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	269	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	270	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	271	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	272	else iop->pdat &= ~0x00010000
	273	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	274	else iop->pdat &= ~0x00020000
	275	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
ea818dbb	276	#endif /* CONFIG_SYS_I2C_SOFT */
15647dc7	277
6d0f6bcf JCPV	278	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
	279	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	280	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	281	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
15647dc7	282
6d0f6bcf	283	#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
15647dc7 WD	284
	285	/*-----------------------------------------------------------------------
	286	* Definitions for initial stack pointer and data area (in DPRAM)
	287	*/
	288
	289	/*
	290	* NS16550 Configuration
	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	293	#define CONFIG_SYS_NS16550_SERIAL
15647dc7	294
6d0f6bcf	295	#define CONFIG_SYS_NS16550_REG_SIZE 1
15647dc7	296
6d0f6bcf	297	#define CONFIG_SYS_NS16550_CLK 7372800
15647dc7	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_NS16550_COM1 0xFF080000
	300	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
	301	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
	302	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
15647dc7 WD	303
	304	/*
	305	* Low Level Configuration Settings
	306	* (address mappings, register initial values, etc.)
	307	* You should know what you are doing if you make changes here.
	308	*/
	309
	310	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	311	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
	312
6d0f6bcf JCPV	313	#define CONFIG_SYS_DLL_EXTEND 0x00
6d0f6bcf JCPV	314	#define CONFIG_SYS_PCI_HOLD_DEL 0x20
15647dc7	315
6d0f6bcf JCPV	316	#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
6d0f6bcf JCPV	317	#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
15647dc7	318
6d0f6bcf	319	#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
15647dc7	320
6d0f6bcf	321	#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
15647dc7 WD	322
15647dc7 WD	323	/* the following are for SDRAM only*/
6d0f6bcf JCPV	324	#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
	325	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
	326	#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
	327	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	328	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	329	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	330	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
	331	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
15647dc7	332	#if 0
6d0f6bcf	333	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
15647dc7 WD	334	#endif
15647dc7 WD	335
6d0f6bcf JCPV	336	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	337	#define CONFIG_SYS_EXTROM 1
	338	#define CONFIG_SYS_REGDIMM 0
15647dc7 WD	339
	340
	341	/* memory bank settings*/
	342	/*
	343	* only bits 20-29 are actually used from these vales to set the
	344	* start/end address the upper two bits will be 0, and the lower 20
	345	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	346	* end address
	347	*/
6d0f6bcf JCPV	348	#define CONFIG_SYS_BANK0_START 0x00000000
	349	#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
	350	#define CONFIG_SYS_BANK0_ENABLE 1
	351	#define CONFIG_SYS_BANK1_START 0x04000000
	352	#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
	353	#define CONFIG_SYS_BANK1_ENABLE 1
	354	#define CONFIG_SYS_BANK2_START 0x3ff00000
	355	#define CONFIG_SYS_BANK2_END 0x3fffffff
	356	#define CONFIG_SYS_BANK2_ENABLE 0
	357	#define CONFIG_SYS_BANK3_START 0x3ff00000
	358	#define CONFIG_SYS_BANK3_END 0x3fffffff
	359	#define CONFIG_SYS_BANK3_ENABLE 0
	360	#define CONFIG_SYS_BANK4_START 0x00000000
	361	#define CONFIG_SYS_BANK4_END 0x00000000
	362	#define CONFIG_SYS_BANK4_ENABLE 0
	363	#define CONFIG_SYS_BANK5_START 0x00000000
	364	#define CONFIG_SYS_BANK5_END 0x00000000
	365	#define CONFIG_SYS_BANK5_ENABLE 0
	366	#define CONFIG_SYS_BANK6_START 0x00000000
	367	#define CONFIG_SYS_BANK6_END 0x00000000
	368	#define CONFIG_SYS_BANK6_ENABLE 0
	369	#define CONFIG_SYS_BANK7_START 0x00000000
	370	#define CONFIG_SYS_BANK7_END 0x00000000
	371	#define CONFIG_SYS_BANK7_ENABLE 0
15647dc7 WD	372	/*
	373	* Memory bank enable bitmask, specifying which of the banks defined above
	374	are actually present. MSB is for bank #7, LSB is for bank #0.
	375	*/
6d0f6bcf	376	#define CONFIG_SYS_BANK_ENABLE 0x01
15647dc7	377
6d0f6bcf	378	#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
15647dc7	379	/* see 8240 book for bit definitions */
6d0f6bcf	380	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
15647dc7 WD	381	/* currently accessed page in memory */
	382	/* see 8240 book for details */
	383
	384	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	385	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	386	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
15647dc7 WD	387
	388	/* stack in DCACHE @ 1GB (no backing mem) */
	389	#if defined(USE_DINK32)
6d0f6bcf JCPV	390	#define CONFIG_SYS_IBAT1L (0x40000000 \| BATL_PP_00 )
6d0f6bcf JCPV	391	#define CONFIG_SYS_IBAT1U (0x40000000 \| BATU_BL_128K )
15647dc7	392	#else
6d0f6bcf JCPV	393	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	394	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
15647dc7 WD	395	#endif
	396
	397	/* PCI memory */
6d0f6bcf JCPV	398	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	399	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
15647dc7 WD	400
15647dc7 WD	401	/* Flash, config addrs, etc */
6d0f6bcf JCPV	402	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	403	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	404
	405	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	406	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	407	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	408	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	409	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	410	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	411	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	412	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
15647dc7 WD	413
	414	/*
	415	* For booting Linux, the board info and command line data
	416	* have to be in the first 8 MB of memory, since this is
	417	* the maximum mapped by the Linux kernel during initialization.
	418	*/
6d0f6bcf	419	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
15647dc7 WD	420	/*-----------------------------------------------------------------------
	421	* FLASH organization
	422	*/
6d0f6bcf JCPV	423	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	424	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
15647dc7	425
6d0f6bcf JCPV	426	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	427	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
15647dc7 WD	428
	429	/*-----------------------------------------------------------------------
	430	* Cache Configuration
	431	*/
6d0f6bcf	432	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
ab999ba1	433	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	434	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
15647dc7 WD	435	#endif
15647dc7 WD	436
15647dc7 WD	437	/* values according to the manual */
	438
	439	#define CONFIG_DRAM_50MHZ 1
	440	#define CONFIG_SDRAM_50MHZ
	441
	442	#define CONFIG_DISK_SPINUP_TIME 1000000
	443
	444	#endif /* __CONFIG_H */