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1/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * (C) Copyright 2009
8 * Frederik Kriewitz <frederik@kriewitz.eu>
9 *
10 * Configuration settings for the DevKit8000 board.
11 *
3765b3e7 12 * SPDX-License-Identifier: GPL-2.0+
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13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
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17
18/* High Level Configuration Options */
2d52a9a3 19#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
308252ad 20
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21/*
22 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
23 * 64 bytes before this address should be set aside for u-boot.img's
24 * header. That is 0x800FFFC0--0x80100000 should not be used for any
25 * other needs.
26 */
27#define CONFIG_SYS_TEXT_BASE 0x80100000
66fca016 28
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29#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
30#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
31
32#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
33#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
cae377b5 34
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35/* Physical Memory Map */
36#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
875e4154 37
a91ef4ad 38#include <configs/ti_omap3_common.h>
875e4154 39
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40#define CONFIG_MISC_INIT_R
41
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42#define CONFIG_REVISION_TAG 1
43
44/* Size of malloc() pool */
9c44ddcc 45#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
c35d7cf0 46 /* Sector */
875e4154 47#undef CONFIG_SYS_MALLOC_LEN
9c44ddcc 48#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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49
50/* Hardware drivers */
c35d7cf0 51/* DM9000 */
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52#define CONFIG_NET_RETRY_COUNT 20
53#define CONFIG_DRIVER_DM9000 1
54#define CONFIG_DM9000_BASE 0x2c000000
55#define DM9000_IO CONFIG_DM9000_BASE
56#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
57#define CONFIG_DM9000_USE_16BIT 1
58#define CONFIG_DM9000_NO_SROM 1
59#undef CONFIG_DM9000_DEBUG
60
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61/* SPI */
62#undef CONFIG_SPI
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63
64/* I2C */
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65
66/* TWL4030 */
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67#define CONFIG_TWL4030_LED 1
68
69/* Board NAND Info */
c35d7cf0 70
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71#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
72 /* to access nand */
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73#define CONFIG_JFFS2_NAND
74/* nand device jffs2 lives on */
75#define CONFIG_JFFS2_DEV "nand0"
76/* start of jffs2 partition */
77#define CONFIG_JFFS2_PART_OFFSET 0x680000
78#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
79 /* partition */
80
875e4154 81#undef CONFIG_SUPPORT_RAW_INITRD
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82
83/* BOOTP/DHCP options */
84#define CONFIG_BOOTP_SUBNETMASK
85#define CONFIG_BOOTP_GATEWAY
86#define CONFIG_BOOTP_HOSTNAME
87#define CONFIG_BOOTP_NISDOMAIN
88#define CONFIG_BOOTP_BOOTPATH
89#define CONFIG_BOOTP_BOOTFILESIZE
90#define CONFIG_BOOTP_DNS
91#define CONFIG_BOOTP_DNS2
92#define CONFIG_BOOTP_SEND_HOSTNAME
93#define CONFIG_BOOTP_NTPSERVER
94#define CONFIG_BOOTP_TIMEOFFSET
95#undef CONFIG_BOOTP_VENDOREX
96
97/* Environment information */
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98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "loadaddr=0x82000000\0" \
2d76da24 100 "console=ttyO2,115200n8\0" \
f408501d 101 "mmcdev=0\0" \
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102 "vram=12M\0" \
103 "dvimode=1024x768MR-16@60\0" \
104 "defaultdisplay=dvi\0" \
105 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
106 "kernelopts=rw\0" \
107 "commonargs=" \
108 "setenv bootargs console=${console} " \
109 "vram=${vram} " \
110 "omapfb.mode=dvi:${dvimode} " \
111 "omapdss.def_disp=${defaultdisplay}\0" \
112 "mmcargs=" \
113 "run commonargs; " \
114 "setenv bootargs ${bootargs} " \
115 "root=/dev/mmcblk0p2 " \
b72db208 116 "rootwait " \
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117 "${kernelopts}\0" \
118 "nandargs=" \
119 "run commonargs; " \
120 "setenv bootargs ${bootargs} " \
121 "omapfb.mode=dvi:${dvimode} " \
122 "omapdss.def_disp=${defaultdisplay} " \
123 "root=/dev/mtdblock4 " \
124 "rootfstype=jffs2 " \
125 "${kernelopts}\0" \
126 "netargs=" \
127 "run commonargs; " \
128 "setenv bootargs ${bootargs} " \
129 "root=/dev/nfs " \
130 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
131 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
132 "${kernelopts} " \
133 "dnsip1=${dnsip} " \
134 "dnsip2=${dnsip2}\0" \
f408501d 135 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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136 "bootscript=echo Running bootscript from mmc ...; " \
137 "source ${loadaddr}\0" \
f408501d 138 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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139 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
140 "mmcboot=echo Booting from mmc ...; " \
141 "run mmcargs; " \
142 "bootm ${loadaddr}\0" \
143 "nandboot=echo Booting from nand ...; " \
144 "run nandargs; " \
145 "nand read ${loadaddr} 280000 400000; " \
146 "bootm ${loadaddr}\0" \
147 "netboot=echo Booting from network ...; " \
148 "dhcp ${loadaddr}; " \
149 "run netargs; " \
150 "bootm ${loadaddr}\0" \
66968110 151 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
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152 "if run loadbootscript; then " \
153 "run bootscript; " \
154 "else " \
155 "if run loaduimage; then " \
156 "run mmcboot; " \
157 "else run nandboot; " \
158 "fi; " \
159 "fi; " \
160 "else run nandboot; fi\0"
161
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162#define CONFIG_BOOTCOMMAND "run autoboot"
163
c35d7cf0 164/* Boot Argument Buffer Size */
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165#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
166#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
167 0x01000000) /* 16MB */
168
c35d7cf0 169/* NAND and environment organization */
c35d7cf0 170
7672d9d5 171#define CONFIG_ENV_OFFSET 0x260000
c35d7cf0 172
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173/* SRAM config */
174#define CONFIG_SYS_SRAM_START 0x40200000
175#define CONFIG_SYS_SRAM_SIZE 0x10000
176
177/* Defines for SPL */
3f6a4922 178
a91ef4ad 179#undef CONFIG_SPL_TEXT_BASE
3f6a4922 180#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
3f6a4922 181
3f6a4922 182/* NAND boot config */
c471ccb9 183#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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184#define CONFIG_SYS_NAND_PAGE_COUNT 64
185#define CONFIG_SYS_NAND_PAGE_SIZE 2048
186#define CONFIG_SYS_NAND_OOBSIZE 64
187#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
188#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
189#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
190 10, 11, 12, 13}
191
192#define CONFIG_SYS_NAND_ECCSIZE 512
193#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069 194#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
3f6a4922 195
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196#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
197#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
198
d38bc97d 199/* SPL OS boot options */
d38bc97d 200#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
b6144dfc 201
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202#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
203#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
204#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
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205#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
206#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
207#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
208
a91ef4ad 209#undef CONFIG_SYS_SPL_ARGS_ADDR
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210#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
211
c35d7cf0 212#endif /* __CONFIG_H */