[people/ms/u-boot.git] / include / configs / devkit8000.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * (C) Copyright 2009
 * Frederik Kriewitz <frederik@kriewitz.eu>
 *
 * Configuration settings for the DevKit8000 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */
#define CONFIG_MACH_TYPE	MACH_TYPE_DEVKIT8000

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE	0x80100000

#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

#define CONFIG_NAND

/*  Physical Memory Map  */
#define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */

#include <configs/ti_omap3_common.h>

#define CONFIG_MISC_INIT_R

#define CONFIG_REVISION_TAG		1

/* Size of malloc() pool */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/* Hardware drivers */
/* DM9000 */
#define CONFIG_NET_RETRY_COUNT		20
#define	CONFIG_DRIVER_DM9000		1
#define	CONFIG_DM9000_BASE		0x2c000000
#define	DM9000_IO			CONFIG_DM9000_BASE
#define	DM9000_DATA			(CONFIG_DM9000_BASE + 0x400)
#define	CONFIG_DM9000_USE_16BIT		1
#define CONFIG_DM9000_NO_SROM		1
#undef	CONFIG_DM9000_DEBUG

/* SPI */
#undef CONFIG_SPI
#undef CONFIG_OMAP3_SPI

/* I2C */
#undef CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_SYS_I2C_OMAP34XX

/* TWL4030 */
#define CONFIG_TWL4030_LED		1

/* Board NAND Info */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:" \
						"512k(x-loader)," \
						"1920k(u-boot)," \
						"128k(u-boot-env)," \
						"4m(kernel)," \
						"-(fs)"

#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* commands to include */
#define CONFIG_CMD_JFFS2		/* JFFS2 Support		*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/

#undef CONFIG_SUPPORT_RAW_INITRD
#undef CONFIG_FAT_WRITE

/* BOOTP/DHCP options */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET
#undef CONFIG_BOOTP_VENDOREX

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
	"kernelopts=rw\0" \
	"commonargs=" \
		"setenv bootargs console=${console} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay}\0" \
	"mmcargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 " \
		"rootwait " \
		"${kernelopts}\0" \
	"nandargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=/dev/mtdblock4 " \
		"rootfstype=jffs2 " \
		"${kernelopts}\0" \
	"netargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/nfs " \
		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
		"${kernelopts} " \
		"dnsip1=${dnsip} " \
		"dnsip2=${dnsip2}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \
	"netboot=echo Booting from network ...; " \
		"dhcp ${loadaddr}; " \
		"run netargs; " \
		"bootm ${loadaddr}\0" \
	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"if run loaduimage; then " \
					"run mmcboot; " \
				"else run nandboot; " \
				"fi; " \
			"fi; " \
		"else run nandboot; fi\0"

#define CONFIG_BOOTCOMMAND "run autoboot"

/* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					0x01000000) /* 16MB */

/* NAND and environment organization  */
#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET

/* SRAM config */
#define CONFIG_SYS_SRAM_START              0x40200000
#define CONFIG_SYS_SRAM_SIZE               0x10000

/* Defines for SPL */

#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/

/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000

/* SPL OS boot options */
#define CONFIG_CMD_SPL_WRITE_SIZE       0x400 /* 1024 byte */
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
					0x400000)
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000

#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x500 /* address 0xa0000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */

#undef CONFIG_SYS_SPL_ARGS_ADDR
#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)

#endif /* __CONFIG_H */
Commit	Line	Data
c35d7cf0 FK	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* (C) Copyright 2009
	8	* Frederik Kriewitz <frederik@kriewitz.eu>
	9	*
	10	* Configuration settings for the DevKit8000 board.
	11	*
3765b3e7	12	* SPDX-License-Identifier: GPL-2.0+
c35d7cf0 FK	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
c35d7cf0 FK	17
c35d7cf0 FK	18	/* High Level Configuration Options */
c35d7cf0	19	#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
2d52a9a3	20	#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
308252ad	21
5183b7ec SS	22	/*
	23	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	24	* 64 bytes before this address should be set aside for u-boot.img's
	25	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	26	* other needs.
	27	*/
	28	#define CONFIG_SYS_TEXT_BASE 0x80100000
66fca016	29
875e4154 AB	30	#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
	31	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	32
	33	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	34	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
cae377b5	35
875e4154	36	#define CONFIG_NAND
875e4154 AB	37
	38	/* Physical Memory Map */
	39	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
875e4154	40
a91ef4ad	41	#include <configs/ti_omap3_common.h>
875e4154	42
c35d7cf0 FK	43	#define CONFIG_MISC_INIT_R
c35d7cf0 FK	44
c35d7cf0 FK	45	#define CONFIG_REVISION_TAG 1
	46
	47	/* Size of malloc() pool */
9c44ddcc	48	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
c35d7cf0	49	/* Sector */
875e4154	50	#undef CONFIG_SYS_MALLOC_LEN
9c44ddcc	51	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
c35d7cf0 FK	52
c35d7cf0 FK	53	/* Hardware drivers */
c35d7cf0	54	/* DM9000 */
c35d7cf0 FK	55	#define CONFIG_NET_RETRY_COUNT 20
	56	#define CONFIG_DRIVER_DM9000 1
	57	#define CONFIG_DM9000_BASE 0x2c000000
	58	#define DM9000_IO CONFIG_DM9000_BASE
	59	#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
	60	#define CONFIG_DM9000_USE_16BIT 1
	61	#define CONFIG_DM9000_NO_SROM 1
	62	#undef CONFIG_DM9000_DEBUG
	63
875e4154 AB	64	/* SPI */
	65	#undef CONFIG_SPI
	66	#undef CONFIG_OMAP3_SPI
c35d7cf0 FK	67
c35d7cf0 FK	68	/* I2C */
875e4154	69	#undef CONFIG_SYS_I2C_OMAP24XX
6789e84e	70	#define CONFIG_SYS_I2C_OMAP34XX
c35d7cf0 FK	71
c35d7cf0 FK	72	/* TWL4030 */
c35d7cf0 FK	73	#define CONFIG_TWL4030_LED 1
	74
	75	/* Board NAND Info */
c35d7cf0 FK	76	#define MTDIDS_DEFAULT "nand0=nand"
	77	#define MTDPARTS_DEFAULT "mtdparts=nand:" \
	78	"512k(x-loader)," \
	79	"1920k(u-boot)," \
	80	"128k(u-boot-env)," \
	81	"4m(kernel)," \
	82	"-(fs)"
	83
c35d7cf0 FK	84	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
c35d7cf0 FK	85	/* to access nand */
c35d7cf0 FK	86	#define CONFIG_JFFS2_NAND
	87	/* nand device jffs2 lives on */
	88	#define CONFIG_JFFS2_DEV "nand0"
	89	/* start of jffs2 partition */
	90	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	91	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	92	/* partition */
	93
	94	/* commands to include */
c35d7cf0	95	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
c35d7cf0 FK	96	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
c35d7cf0 FK	97
875e4154 AB	98	#undef CONFIG_SUPPORT_RAW_INITRD
875e4154 AB	99	#undef CONFIG_FAT_WRITE
c35d7cf0 FK	100
	101	/* BOOTP/DHCP options */
	102	#define CONFIG_BOOTP_SUBNETMASK
	103	#define CONFIG_BOOTP_GATEWAY
	104	#define CONFIG_BOOTP_HOSTNAME
	105	#define CONFIG_BOOTP_NISDOMAIN
	106	#define CONFIG_BOOTP_BOOTPATH
	107	#define CONFIG_BOOTP_BOOTFILESIZE
	108	#define CONFIG_BOOTP_DNS
	109	#define CONFIG_BOOTP_DNS2
	110	#define CONFIG_BOOTP_SEND_HOSTNAME
	111	#define CONFIG_BOOTP_NTPSERVER
	112	#define CONFIG_BOOTP_TIMEOFFSET
	113	#undef CONFIG_BOOTP_VENDOREX
	114
	115	/* Environment information */
c35d7cf0 FK	116	#define CONFIG_EXTRA_ENV_SETTINGS \
c35d7cf0 FK	117	"loadaddr=0x82000000\0" \
2d76da24	118	"console=ttyO2,115200n8\0" \
f408501d	119	"mmcdev=0\0" \
c35d7cf0 FK	120	"vram=12M\0" \
	121	"dvimode=1024x768MR-16@60\0" \
	122	"defaultdisplay=dvi\0" \
	123	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
	124	"kernelopts=rw\0" \
	125	"commonargs=" \
	126	"setenv bootargs console=${console} " \
	127	"vram=${vram} " \
	128	"omapfb.mode=dvi:${dvimode} " \
	129	"omapdss.def_disp=${defaultdisplay}\0" \
	130	"mmcargs=" \
	131	"run commonargs; " \
	132	"setenv bootargs ${bootargs} " \
	133	"root=/dev/mmcblk0p2 " \
b72db208	134	"rootwait " \
c35d7cf0 FK	135	"${kernelopts}\0" \
	136	"nandargs=" \
	137	"run commonargs; " \
	138	"setenv bootargs ${bootargs} " \
	139	"omapfb.mode=dvi:${dvimode} " \
	140	"omapdss.def_disp=${defaultdisplay} " \
	141	"root=/dev/mtdblock4 " \
	142	"rootfstype=jffs2 " \
	143	"${kernelopts}\0" \
	144	"netargs=" \
	145	"run commonargs; " \
	146	"setenv bootargs ${bootargs} " \
	147	"root=/dev/nfs " \
	148	"nfsroot=${serverip}:${rootpath},${nfsopts} " \
	149	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
	150	"${kernelopts} " \
	151	"dnsip1=${dnsip} " \
	152	"dnsip2=${dnsip2}\0" \
f408501d	153	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
c35d7cf0 FK	154	"bootscript=echo Running bootscript from mmc ...; " \
c35d7cf0 FK	155	"source ${loadaddr}\0" \
f408501d	156	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
c35d7cf0 FK	157	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	158	"mmcboot=echo Booting from mmc ...; " \
	159	"run mmcargs; " \
	160	"bootm ${loadaddr}\0" \
	161	"nandboot=echo Booting from nand ...; " \
	162	"run nandargs; " \
	163	"nand read ${loadaddr} 280000 400000; " \
	164	"bootm ${loadaddr}\0" \
	165	"netboot=echo Booting from network ...; " \
	166	"dhcp ${loadaddr}; " \
	167	"run netargs; " \
	168	"bootm ${loadaddr}\0" \
66968110	169	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
c35d7cf0 FK	170	"if run loadbootscript; then " \
	171	"run bootscript; " \
	172	"else " \
	173	"if run loaduimage; then " \
	174	"run mmcboot; " \
	175	"else run nandboot; " \
	176	"fi; " \
	177	"fi; " \
	178	"else run nandboot; fi\0"
	179
c35d7cf0 FK	180	#define CONFIG_BOOTCOMMAND "run autoboot"
c35d7cf0 FK	181
c35d7cf0	182	/* Boot Argument Buffer Size */
c35d7cf0 FK	183	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
	184	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	185	0x01000000) /* 16MB */
	186
c35d7cf0	187	/* NAND and environment organization */
c35d7cf0 FK	188	#define CONFIG_ENV_IS_IN_NAND 1
	189	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	190
6cbec7b3	191	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
c35d7cf0	192
3f6a4922 SS	193	/* SRAM config */
	194	#define CONFIG_SYS_SRAM_START 0x40200000
	195	#define CONFIG_SYS_SRAM_SIZE 0x10000
	196
	197	/* Defines for SPL */
3f6a4922	198
a91ef4ad	199	#undef CONFIG_SPL_TEXT_BASE
3f6a4922	200	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
3f6a4922	201
3f6a4922	202	/* NAND boot config */
55f1b39f	203	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
c471ccb9	204	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
3f6a4922 SS	205	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	206	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	207	#define CONFIG_SYS_NAND_OOBSIZE 64
	208	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	209	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	210	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	211	10, 11, 12, 13}
	212
	213	#define CONFIG_SYS_NAND_ECCSIZE 512
	214	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	215	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
3f6a4922	216
3f6a4922 SS	217	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	218	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
	219
d38bc97d	220	/* SPL OS boot options */
d38bc97d SS	221	#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
	222	#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
	223	0x400000)
	224	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
b6144dfc	225
875e4154 AB	226	#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
	227	#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
	228	#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
b6144dfc TR	229	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
	230	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
	231	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
	232
a91ef4ad	233	#undef CONFIG_SYS_SPL_ARGS_ADDR
d38bc97d SS	234	#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
d38bc97d SS	235
c35d7cf0	236	#endif /* __CONFIG_H */