[people/ms/u-boot.git] / include / configs / dlvision-10g.h

/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_405EP		1	/* this is a PPC405 CPU */
#define CONFIG_DLVISION_10G	1	/*  on a DLVision-10G board */

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		dlvsion-10g
#define CONFIG_IDENT_STRING	" dlvision-10g 0.05"
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT

#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */

#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR " "

/*
 * Configure PLL
 */
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"fdt_addr=fc1e0000\0"						\
	"ramdisk_addr=fc200000\0"					\
	""

#define CONFIG_PHY_ADDR		4	/* PHY address			*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */

/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */

/*
 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		691200

/*
 * I2C stuff
 */
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000

/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63		1	/* National LM63	*/
#define CONFIG_DTT_SENSORS	{ 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE	\
		{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
		  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT	0xa10

/* EBC peripherals */

#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FPGA0_BASE		0x7f100000
#define CONFIG_SYS_FPGA1_BASE		0x7f200000
#define CONFIG_SYS_LATCH_BASE		0x7f300000

#define CONFIG_SYS_FPGA_BASE(k) \
	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)

#define CONFIG_SYS_FPGA_DONE(k) \
	(k ? 0x2000 : 0x1000)

#define CONFIG_SYS_FPGA_COUNT		2

#define CONFIG_SYS_FPGA_PTR { \
	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }

#define CONFIG_SYS_FPGA_COMMON

#define CONFIG_SYS_LATCH0_RESET		0xffff
#define CONFIG_SYS_LATCH0_BOOT		0xffff
#define CONFIG_SYS_LATCH1_RESET		0xffbf
#define CONFIG_SYS_LATCH1_BOOT		0xffff

#define CONFIG_SYS_FPGA_NO_RFL_HI

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */

#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/*
 * PPC405 GPIO Configuration
 */
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
} \
}

/*
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */

#define CONFIG_SYS_GBL_DATA_OFFSET \
	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (NOR-flash) */
#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_ENABLED		|	\
				 EBC_BXAP_FWT_ENCODE(8)		|	\
				 EBC_BXAP_BWT_ENCODE(7)		|	\
				 EBC_BXAP_BCE_DISABLE		|	\
				 EBC_BXAP_BCT_2TRANS		|	\
				 EBC_BXAP_CSN_ENCODE(0)		|	\
				 EBC_BXAP_OEN_ENCODE(2)		|	\
				 EBC_BXAP_WBN_ENCODE(2)		|	\
				 EBC_BXAP_WBF_ENCODE(2)		|	\
				 EBC_BXAP_TH_ENCODE(4)		|	\
				 EBC_BXAP_RE_DISABLED		|	\
				 EBC_BXAP_SOR_NONDELAYED	|	\
				 EBC_BXAP_BEM_WRITEONLY		|	\
				 EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
				 EBC_BXCR_BS_64MB		|	\
				 EBC_BXCR_BU_RW			|	\
				 EBC_BXCR_BW_16BIT)

/* Memory Bank 1 (FPGA0) */
#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
				 EBC_BXAP_TWT_ENCODE(5)		|	\
				 EBC_BXAP_BCE_DISABLE		|	\
				 EBC_BXAP_BCT_2TRANS		|	\
				 EBC_BXAP_CSN_ENCODE(0)		|	\
				 EBC_BXAP_OEN_ENCODE(2)		|	\
				 EBC_BXAP_WBN_ENCODE(1)		|	\
				 EBC_BXAP_WBF_ENCODE(1)		|	\
				 EBC_BXAP_TH_ENCODE(0)		|	\
				 EBC_BXAP_RE_DISABLED		|	\
				 EBC_BXAP_SOR_NONDELAYED	|	\
				 EBC_BXAP_BEM_WRITEONLY		|	\
				 EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
				 EBC_BXCR_BS_1MB		|	\
				 EBC_BXCR_BU_RW			|	\
				 EBC_BXCR_BW_16BIT)

/* Memory Bank 2 (FPGA1) */
#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
				 EBC_BXAP_TWT_ENCODE(6)		|	\
				 EBC_BXAP_BCE_DISABLE		|	\
				 EBC_BXAP_BCT_2TRANS		|	\
				 EBC_BXAP_CSN_ENCODE(0)		|	\
				 EBC_BXAP_OEN_ENCODE(2)		|	\
				 EBC_BXAP_WBN_ENCODE(1)		|	\
				 EBC_BXAP_WBF_ENCODE(1)		|	\
				 EBC_BXAP_TH_ENCODE(0)		|	\
				 EBC_BXAP_RE_DISABLED		|	\
				 EBC_BXAP_SOR_NONDELAYED	|	\
				 EBC_BXAP_BEM_WRITEONLY		|	\
				 EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
				 EBC_BXCR_BS_1MB		|	\
				 EBC_BXCR_BU_RW			|	\
				 EBC_BXCR_BW_16BIT)

/* Memory Bank 3 (Latches) */
#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
				 EBC_BXAP_FWT_ENCODE(8)		|	\
				 EBC_BXAP_BWT_ENCODE(4)		|	\
				 EBC_BXAP_BCE_DISABLE		|	\
				 EBC_BXAP_BCT_2TRANS		|	\
				 EBC_BXAP_CSN_ENCODE(0)		|	\
				 EBC_BXAP_OEN_ENCODE(1)		|	\
				 EBC_BXAP_WBN_ENCODE(1)		|	\
				 EBC_BXAP_WBF_ENCODE(1)		|	\
				 EBC_BXAP_TH_ENCODE(2)		|	\
				 EBC_BXAP_RE_DISABLED		|	\
				 EBC_BXAP_SOR_NONDELAYED	|	\
				 EBC_BXAP_BEM_WRITEONLY		|	\
				 EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
				 EBC_BXCR_BS_1MB		|	\
				 EBC_BXCR_BU_RW			|	\
				 EBC_BXCR_BW_16BIT)

/*
 * OSD Setup
 */
#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
#define CONFIG_SYS_SIL1178
#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT

#endif	/* __CONFIG_H */
Commit	Line	Data
2da0fc0d DE	1	/*
	2	* (C) Copyright 2010
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
2da0fc0d DE	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	#define CONFIG_405EP 1 /* this is a PPC405 CPU */
2da0fc0d DE	12	#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
	13
	14	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
	15
	16	/*
	17	* Include common defines/options for all AMCC eval boards
	18	*/
	19	#define CONFIG_HOSTNAME dlvsion-10g
3e24dd2b	20	#define CONFIG_IDENT_STRING " dlvision-10g 0.05"
2da0fc0d DE	21	#include "amcc-common.h"
2da0fc0d DE	22
6e9e6c36 DE	23	#define CONFIG_BOARD_EARLY_INIT_F
6e9e6c36 DE	24	#define CONFIG_BOARD_EARLY_INIT_R
b19bf834	25	#define CONFIG_MISC_INIT_R
2da0fc0d DE	26	#define CONFIG_LAST_STAGE_INIT
	27
	28	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	29
6cfa9eec DE	30	#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
	31	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
	32	#define CONFIG_AUTOBOOT_STOP_STR " "
	33
2da0fc0d DE	34	/*
	35	* Configure PLL
	36	*/
	37	#define PLLMR0_DEFAULT PLLMR0_266_133_66
	38	#define PLLMR1_DEFAULT PLLMR1_266_133_66
	39
	40	/* new uImage format support */
	41	#define CONFIG_FIT
	42	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	43
	44	#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
	45
	46	/*
	47	* Default environment variables
	48	*/
	49	#define CONFIG_EXTRA_ENV_SETTINGS \
	50	CONFIG_AMCC_DEF_ENV \
	51	CONFIG_AMCC_DEF_ENV_POWERPC \
	52	CONFIG_AMCC_DEF_ENV_NOR_UPD \
	53	"kernel_addr=fc000000\0" \
	54	"fdt_addr=fc1e0000\0" \
	55	"ramdisk_addr=fc200000\0" \
	56	""
	57
	58	#define CONFIG_PHY_ADDR 4 /* PHY address */
	59	#define CONFIG_HAS_ETH0
	60	#define CONFIG_HAS_ETH1
	61	#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
	62	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
	63
	64	/*
	65	* Commands additional to the ones defined in amcc-common.h
	66	*/
	67	#define CONFIG_CMD_CACHE
b19bf834	68	#define CONFIG_CMD_DTT
2da0fc0d DE	69	#undef CONFIG_CMD_EEPROM
	70
	71	/*
	72	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	73	*/
	74	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	75
	76	/* SDRAM timings used in datasheet */
	77	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	78	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	79	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
	80	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	81	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
	82
	83	/*
	84	* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	85	* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
	86	* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
	87	* The Linux BASE_BAUD define should match this configuration.
	88	* baseBaud = cpuClock/(uartDivisor*16)
	89	* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
	90	* set Linux BASE_BAUD to 403200.
	91	*/
	92	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	93	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
	94	#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	95	#define CONFIG_SYS_BASE_BAUD 691200
	96
	97	/*
	98	* I2C stuff
	99	*/
880540de	100	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
2da0fc0d DE	101
	102	/* Temp sensor/hwmon/dtt */
	103	#define CONFIG_DTT_LM63 1 /* National LM63 */
2ade7bee	104	#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
2da0fc0d	105	#define CONFIG_DTT_PWM_LOOKUPTABLE \
97ca7b3b DE	106	{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
97ca7b3b DE	107	{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
2da0fc0d DE	108	#define CONFIG_DTT_TACH_LIMIT 0xa10
	109
	110	/* EBC peripherals */
	111
	112	#define CONFIG_SYS_FLASH_BASE 0xFC000000
	113	#define CONFIG_SYS_FPGA0_BASE 0x7f100000
	114	#define CONFIG_SYS_FPGA1_BASE 0x7f200000
	115	#define CONFIG_SYS_LATCH_BASE 0x7f300000
	116
	117	#define CONFIG_SYS_FPGA_BASE(k) \
	118	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
	119
	120	#define CONFIG_SYS_FPGA_DONE(k) \
	121	(k ? 0x2000 : 0x1000)
	122
	123	#define CONFIG_SYS_FPGA_COUNT 2
	124
aba27acf DE	125	#define CONFIG_SYS_FPGA_PTR { \
	126	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
	127	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
	128
	129	#define CONFIG_SYS_FPGA_COMMON
	130
2da0fc0d DE	131	#define CONFIG_SYS_LATCH0_RESET 0xffff
2da0fc0d DE	132	#define CONFIG_SYS_LATCH0_BOOT 0xffff
3e24dd2b	133	#define CONFIG_SYS_LATCH1_RESET 0xffbf
2da0fc0d DE	134	#define CONFIG_SYS_LATCH1_BOOT 0xffff
2da0fc0d DE	135
5cb4100f DE	136	#define CONFIG_SYS_FPGA_NO_RFL_HI
5cb4100f DE	137
2da0fc0d DE	138	/*
	139	* FLASH organization
	140	*/
	141	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	142	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	143
	144	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	145
	146	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	147	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
	148
	149	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
	150	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
	151
	152	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
2da0fc0d DE	153
	154	#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
	155	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
	156
	157	#ifdef CONFIG_ENV_IS_IN_FLASH
	158	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	159	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
	160	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	161
	162	/* Address and size of Redundant Environment Sector */
	163	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
	164	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	165	#endif
	166
	167	/*
	168	* PPC405 GPIO Configuration
	169	*/
	170	#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
	171	{ \
	172	/* GPIO Core 0 */ \
	173	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
	174	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
	175	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
	176	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
	177	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
	178	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
	179	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
	180	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
	181	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
	182	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
	183	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
	184	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
	185	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
	186	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
	187	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
	188	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
	189	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
	190	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
	191	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
	192	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
	193	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
	194	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
	195	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
	196	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
	197	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
	198	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
	199	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
	200	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
	201	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
	202	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
	203	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
	204	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
	205	} \
	206	}
	207
	208	/*
	209	* Definitions for initial stack pointer and data area (in data cache)
	210	*/
	211	/* use on chip memory (OCM) for temperary stack until sdram is tested */
	212	#define CONFIG_SYS_TEMP_STACK_OCM 1
	213
	214	/* On Chip Memory location */
	215	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	216	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
217	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
218	#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
219
2da0fc0d	220	#define CONFIG_SYS_GBL_DATA_OFFSET \
627b73e2	221	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
2da0fc0d DE	222	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	223
	224	/*
	225	* External Bus Controller (EBC) Setup
	226	*/
	227
	228	/* Memory Bank 0 (NOR-flash) */
	229	#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED \| \
	230	EBC_BXAP_FWT_ENCODE(8) \| \
	231	EBC_BXAP_BWT_ENCODE(7) \| \
	232	EBC_BXAP_BCE_DISABLE \| \
	233	EBC_BXAP_BCT_2TRANS \| \
	234	EBC_BXAP_CSN_ENCODE(0) \| \
	235	EBC_BXAP_OEN_ENCODE(2) \| \
	236	EBC_BXAP_WBN_ENCODE(2) \| \
	237	EBC_BXAP_WBF_ENCODE(2) \| \
	238	EBC_BXAP_TH_ENCODE(4) \| \
	239	EBC_BXAP_RE_DISABLED \| \
	240	EBC_BXAP_SOR_NONDELAYED \| \
	241	EBC_BXAP_BEM_WRITEONLY \| \
	242	EBC_BXAP_PEN_DISABLED)
	243	#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) \| \
	244	EBC_BXCR_BS_64MB \| \
	245	EBC_BXCR_BU_RW \| \
	246	EBC_BXCR_BW_16BIT)
	247
	248	/* Memory Bank 1 (FPGA0) */
	249	#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED \| \
	250	EBC_BXAP_TWT_ENCODE(5) \| \
	251	EBC_BXAP_BCE_DISABLE \| \
	252	EBC_BXAP_BCT_2TRANS \| \
	253	EBC_BXAP_CSN_ENCODE(0) \| \
	254	EBC_BXAP_OEN_ENCODE(2) \| \
	255	EBC_BXAP_WBN_ENCODE(1) \| \
	256	EBC_BXAP_WBF_ENCODE(1) \| \
	257	EBC_BXAP_TH_ENCODE(0) \| \
	258	EBC_BXAP_RE_DISABLED \| \
	259	EBC_BXAP_SOR_NONDELAYED \| \
	260	EBC_BXAP_BEM_WRITEONLY \| \
	261	EBC_BXAP_PEN_DISABLED)
	262	#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) \| \
	263	EBC_BXCR_BS_1MB \| \
	264	EBC_BXCR_BU_RW \| \
	265	EBC_BXCR_BW_16BIT)
	266
	267	/* Memory Bank 2 (FPGA1) */
	268	#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED \| \
	269	EBC_BXAP_TWT_ENCODE(6) \| \
	270	EBC_BXAP_BCE_DISABLE \| \
	271	EBC_BXAP_BCT_2TRANS \| \
	272	EBC_BXAP_CSN_ENCODE(0) \| \
	273	EBC_BXAP_OEN_ENCODE(2) \| \
	274	EBC_BXAP_WBN_ENCODE(1) \| \
	275	EBC_BXAP_WBF_ENCODE(1) \| \
	276	EBC_BXAP_TH_ENCODE(0) \| \
	277	EBC_BXAP_RE_DISABLED \| \
	278	EBC_BXAP_SOR_NONDELAYED \| \
	279	EBC_BXAP_BEM_WRITEONLY \| \
	280	EBC_BXAP_PEN_DISABLED)
	281	#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) \| \
	282	EBC_BXCR_BS_1MB \| \
	283	EBC_BXCR_BU_RW \| \
	284	EBC_BXCR_BW_16BIT)
	285
286	/* Memory Bank 3 (Latches) */
287	#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED \| \
288	EBC_BXAP_FWT_ENCODE(8) \| \
289	EBC_BXAP_BWT_ENCODE(4) \| \
290	EBC_BXAP_BCE_DISABLE \| \
291	EBC_BXAP_BCT_2TRANS \| \
292	EBC_BXAP_CSN_ENCODE(0) \| \
293	EBC_BXAP_OEN_ENCODE(1) \| \
294	EBC_BXAP_WBN_ENCODE(1) \| \
295	EBC_BXAP_WBF_ENCODE(1) \| \
296	EBC_BXAP_TH_ENCODE(2) \| \
297	EBC_BXAP_RE_DISABLED \| \
298	EBC_BXAP_SOR_NONDELAYED \| \
299	EBC_BXAP_BEM_WRITEONLY \| \
300	EBC_BXAP_PEN_DISABLED)
301	#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) \| \
302	EBC_BXCR_BS_1MB \| \
303	EBC_BXCR_BU_RW \| \
304	EBC_BXCR_BW_16BIT)
305
306	/*
307	* OSD Setup
308	*/
309	#define CONFIG_SYS_ICS8N3QV01
7749c84e	310	#define CONFIG_SYS_MPC92469AC
2da0fc0d DE	311	#define CONFIG_SYS_SIL1178
	312	#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
	313
	314	#endif /* __CONFIG_H */