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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG | |
4 | * | |
5 | * This file is based on similar values for other boards found in other | |
6 | * U-Boot config files, and some that I found in the EP8260 manual. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
5b1d7137 WD |
9 | */ |
10 | ||
11 | /* | |
12 | * board/config.h - configuration options, board specific | |
a562e1bd | 13 | * |
9dd611b8 | 14 | * "EP8260 H, V.1.1" |
53677ef1 WD |
15 | * - 64M 60x Bus SDRAM |
16 | * - 32M Local Bus SDRAM | |
17 | * - 16M Flash (4 x AM29DL323DB90WDI) | |
18 | * - 128k NVRAM with RTC | |
9dd611b8 | 19 | * |
6d0f6bcf | 20 | * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2) |
53677ef1 WD |
21 | * - 300MHz/133MHz/66MHz |
22 | * - 64M 60x Bus SDRAM | |
23 | * - 32M Local Bus SDRAM | |
24 | * - 32M Flash | |
25 | * - 128k NVRAM with RTC | |
5b1d7137 WD |
26 | */ |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
9dd611b8 | 31 | /* Define this to enable support the EP8260 H2 version */ |
6d0f6bcf JCPV |
32 | #define CONFIG_SYS_EP8260_H2 1 |
33 | /* #undef CONFIG_SYS_EP8260_H2 */ | |
9dd611b8 | 34 | |
2ae18241 WD |
35 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
36 | ||
9c4c5ae3 JL |
37 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
38 | ||
5b1d7137 WD |
39 | /* What is the oscillator's (UX2) frequency in Hz? */ |
40 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
41 | ||
42 | /*----------------------------------------------------------------------- | |
43 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
44 | *----------------------------------------------------------------------- | |
45 | * What should MODCK_H be? It is dependent on the oscillator | |
46 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
47 | * Here are some example values (all frequencies are in MHz): | |
48 | * | |
49 | * MODCK_H MODCK[1-3] Osc CPM Core | |
50 | * ------- ---------- --- --- ---- | |
51 | * 0x2 0x2 33 133 133 | |
52 | * 0x2 0x3 33 133 166 | |
53 | * 0x2 0x4 33 133 200 | |
54 | * 0x2 0x5 33 133 233 | |
55 | * 0x2 0x6 33 133 266 | |
56 | * | |
57 | * 0x5 0x5 66 133 133 | |
58 | * 0x5 0x6 66 133 166 | |
59 | * 0x5 0x7 66 133 200 * | |
60 | * 0x6 0x0 66 133 233 | |
61 | * 0x6 0x1 66 133 266 | |
62 | * 0x6 0x2 66 133 300 | |
63 | */ | |
6d0f6bcf JCPV |
64 | #ifdef CONFIG_SYS_EP8260_H2 |
65 | #define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) | |
9dd611b8 | 66 | #else |
6d0f6bcf | 67 | #define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110) |
9dd611b8 | 68 | #endif |
5b1d7137 WD |
69 | |
70 | /* Define this if you want to boot from 0x00000100. If you don't define | |
71 | * this, you will need to program the bootloader to 0xfff00000, and | |
72 | * get the hardware reset config words at 0xfe000000. The simplest | |
73 | * way to do that is to program the bootloader at both addresses. | |
74 | * It is suggested that you just let U-Boot live at 0x00000000. | |
75 | */ | |
6d0f6bcf JCPV |
76 | /* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */ |
77 | /* #undef CONFIG_SYS_SBC_BOOT_LOW */ | |
5b1d7137 WD |
78 | |
79 | /* The reset command will not work as expected if the reset address does | |
80 | * not point to the correct address. | |
81 | */ | |
82 | ||
6d0f6bcf | 83 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
5b1d7137 WD |
84 | |
85 | /* What should the base address of the main FLASH be and how big is | |
14d0a02a | 86 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk |
5b1d7137 WD |
87 | * The main FLASH is whichever is connected to *CS0. U-Boot expects |
88 | * this to be the SIMM. | |
89 | */ | |
6d0f6bcf JCPV |
90 | #ifdef CONFIG_SYS_EP8260_H2 |
91 | #define CONFIG_SYS_FLASH0_BASE 0xFE000000 | |
92 | #define CONFIG_SYS_FLASH0_SIZE 32 | |
9dd611b8 | 93 | #else |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_FLASH0_BASE 0xFF000000 |
95 | #define CONFIG_SYS_FLASH0_SIZE 16 | |
9dd611b8 | 96 | #endif |
5b1d7137 WD |
97 | |
98 | /* What should the base address of the secondary FLASH be and how big | |
99 | * is it (in Mbytes)? The secondary FLASH is whichever is connected | |
100 | * to *CS6. U-Boot expects this to be the on board FLASH. If you don't | |
101 | * want it enabled, don't define these constants. | |
102 | */ | |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_FLASH1_BASE 0 |
104 | #define CONFIG_SYS_FLASH1_SIZE 0 | |
105 | #undef CONFIG_SYS_FLASH1_BASE | |
106 | #undef CONFIG_SYS_FLASH1_SIZE | |
5b1d7137 WD |
107 | |
108 | /* What should be the base address of SDRAM DIMM (60x bus) and how big is | |
109 | * it (in Mbytes)? | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
112 | #define CONFIG_SYS_SDRAM0_SIZE 64 | |
5b1d7137 | 113 | |
6d0f6bcf | 114 | /* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the |
5b1d7137 WD |
115 | * local bus (8260 local bus is NOT cacheable!) |
116 | */ | |
6d0f6bcf JCPV |
117 | /* #define CONFIG_SYS_LSDRAM */ |
118 | #undef CONFIG_SYS_LSDRAM | |
5b1d7137 | 119 | |
6d0f6bcf | 120 | #ifdef CONFIG_SYS_LSDRAM |
5b1d7137 WD |
121 | /* What should be the base address of SDRAM DIMM (local bus) and how big is |
122 | * it (in Mbytes)? | |
123 | */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_SDRAM1_BASE 0x04000000 |
125 | #define CONFIG_SYS_SDRAM1_SIZE 32 | |
5b1d7137 | 126 | #else |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_SDRAM1_BASE 0 |
128 | #define CONFIG_SYS_SDRAM1_SIZE 0 | |
129 | #undef CONFIG_SYS_SDRAM1_BASE | |
130 | #undef CONFIG_SYS_SDRAM1_SIZE | |
131 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
132 | |
133 | /* What should be the base address of NVRAM and how big is | |
134 | * it (in Bytes) | |
135 | */ | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 |
137 | #define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 | |
5b1d7137 WD |
138 | |
139 | /* The RTC is a Dallas DS1556 | |
140 | */ | |
141 | #define CONFIG_RTC_DS1556 | |
142 | ||
143 | /* What should be the base address of the LEDs and switch S0? | |
144 | * If you don't want them enabled, don't define this. | |
145 | */ | |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_LED_BASE 0x00000000 |
147 | #undef CONFIG_SYS_LED_BASE | |
5b1d7137 WD |
148 | |
149 | /* | |
150 | * select serial console configuration | |
151 | * | |
152 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
153 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
154 | * for SCC). | |
155 | * | |
156 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
157 | * defined elsewhere. | |
158 | */ | |
159 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
160 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
161 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
162 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
163 | ||
164 | /* | |
165 | * select ethernet configuration | |
166 | * | |
167 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
168 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
169 | * for FCC) | |
170 | * | |
171 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 172 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
5b1d7137 WD |
173 | */ |
174 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
175 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
176 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
177 | #define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ | |
178 | ||
179 | #if ( CONFIG_ETHER_INDEX == 3 ) | |
180 | ||
181 | /* | |
182 | * - Rx-CLK is CLK15 | |
183 | * - Tx-CLK is CLK16 | |
184 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
185 | * - Enable Half Duplex in FSMR | |
186 | */ | |
d4590da4 MF |
187 | # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) |
188 | # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
5b1d7137 WD |
189 | |
190 | /* | |
191 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
192 | */ | |
6d0f6bcf JCPV |
193 | #ifdef CONFIG_SYS_LSDRAM |
194 | #define CONFIG_SYS_CPMFCR_RAMTYPE 3 | |
195 | #else /* CONFIG_SYS_LSDRAM */ | |
196 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
197 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
198 | |
199 | /* - Enable Half Duplex in FSMR */ | |
6d0f6bcf JCPV |
200 | /* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ |
201 | # define CONFIG_SYS_FCC_PSMR 0 | |
5b1d7137 WD |
202 | |
203 | #else /* CONFIG_ETHER_INDEX */ | |
204 | # error "on EP8260 ethernet must be FCC3" | |
205 | #endif /* CONFIG_ETHER_INDEX */ | |
206 | ||
207 | /* | |
208 | * select i2c support configuration | |
209 | * | |
210 | * Supported configurations are {none, software, hardware} drivers. | |
211 | * If the software driver is chosen, there are some additional | |
212 | * configuration items that the driver uses to drive the port pins. | |
213 | */ | |
ea818dbb HS |
214 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
215 | ||
6d0f6bcf | 216 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
ea818dbb | 217 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */ |
5b1d7137 WD |
218 | |
219 | /* | |
220 | * Software (bit-bang) I2C driver configuration | |
221 | */ | |
ea818dbb HS |
222 | #ifdef CONFIG_SYS_I2C_SOFT |
223 | #define CONFIG_SYS_I2C | |
224 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
225 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
5b1d7137 WD |
226 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
227 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
228 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
229 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
230 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
231 | else iop->pdat &= ~0x00010000 | |
232 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
233 | else iop->pdat &= ~0x00020000 | |
234 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
ea818dbb | 235 | #endif /* CONFIG_SYS_I2C_SOFT */ |
5b1d7137 WD |
236 | |
237 | /* #define CONFIG_RTC_DS174x */ | |
238 | ||
239 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
240 | * environment variables. Otherwise, the environment will be | |
241 | * put in the same sector as U-Boot, and changing variables | |
242 | * will erase U-Boot temporarily | |
243 | */ | |
0e8d1586 | 244 | #define CONFIG_ENV_IN_OWN_SECT |
5b1d7137 WD |
245 | |
246 | /* Define to allow the user to overwrite serial and ethaddr */ | |
247 | #define CONFIG_ENV_OVERWRITE | |
248 | ||
249 | /* What should the console's baud rate be? */ | |
6d0f6bcf | 250 | #ifdef CONFIG_SYS_EP8260_H2 |
9dd611b8 WD |
251 | #define CONFIG_BAUDRATE 9600 |
252 | #else | |
a562e1bd | 253 | #define CONFIG_BAUDRATE 115200 |
9dd611b8 | 254 | #endif |
5b1d7137 WD |
255 | |
256 | /* Ethernet MAC address */ | |
257 | #define CONFIG_ETHADDR 00:10:EC:00:30:8C | |
258 | ||
259 | #define CONFIG_IPADDR 192.168.254.130 | |
260 | #define CONFIG_SERVERIP 192.168.254.49 | |
261 | ||
262 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
263 | #define CONFIG_BOOTDELAY -1 | |
264 | ||
265 | /* undef this to save memory */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_LONGHELP |
5b1d7137 WD |
267 | |
268 | /* Monitor Command Prompt */ | |
5b1d7137 WD |
269 | |
270 | /* Define this variable to enable the "hush" shell (from | |
271 | Busybox) as command line interpreter, thus enabling | |
272 | powerful command line syntax like | |
273 | if...then...else...fi conditionals or `&&' and '||' | |
274 | constructs ("shell scripts"). | |
275 | If undefined, you get the old, much simpler behaviour | |
276 | with a somewhat smapper memory footprint. | |
277 | */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_HUSH_PARSER |
5b1d7137 | 279 | |
1bec3d30 | 280 | |
80ff4f99 JL |
281 | /* |
282 | * BOOTP options | |
283 | */ | |
284 | #define CONFIG_BOOTP_BOOTFILESIZE | |
285 | #define CONFIG_BOOTP_BOOTPATH | |
286 | #define CONFIG_BOOTP_GATEWAY | |
287 | #define CONFIG_BOOTP_HOSTNAME | |
288 | ||
289 | ||
5b1d7137 | 290 | /* |
1bec3d30 JL |
291 | * Command line configuration. |
292 | */ | |
4e620410 JCPV |
293 | #include <config_cmd_default.h> |
294 | ||
295 | #define CONFIG_CMD_ASKENV | |
296 | #define CONFIG_CMD_BEDBUG | |
297 | #define CONFIG_CMD_CACHE | |
298 | #define CONFIG_CMD_CDP | |
299 | #define CONFIG_CMD_DATE | |
300 | #define CONFIG_CMD_DIAG | |
301 | #define CONFIG_CMD_ELF | |
302 | #define CONFIG_CMD_FAT | |
303 | #define CONFIG_CMD_I2C | |
304 | #define CONFIG_CMD_IMMAP | |
305 | #define CONFIG_CMD_IRQ | |
306 | #define CONFIG_CMD_PING | |
307 | #define CONFIG_CMD_PORTIO | |
308 | #define CONFIG_CMD_REGINFO | |
309 | #define CONFIG_CMD_SAVES | |
310 | #define CONFIG_CMD_SDRAM | |
311 | #define CONFIG_CMD_SNTP | |
1bec3d30 | 312 | |
1bec3d30 | 313 | #undef CONFIG_CMD_XIMG |
5b1d7137 WD |
314 | |
315 | /* Where do the internal registers live? */ | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_IMMR 0xF0000000 |
317 | #define CONFIG_SYS_DEFAULT_IMMR 0x00010000 | |
5b1d7137 WD |
318 | |
319 | /* Where do the on board registers (CS4) live? */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_REGS_BASE 0xFA000000 |
5b1d7137 WD |
321 | |
322 | /***************************************************************************** | |
323 | * | |
324 | * You should not have to modify any of the following settings | |
325 | * | |
326 | *****************************************************************************/ | |
327 | ||
328 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
329 | #define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ | |
330 | ||
c837dcb1 | 331 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
5b1d7137 | 332 | |
5b1d7137 WD |
333 | /* |
334 | * Miscellaneous configurable options | |
335 | */ | |
1bec3d30 | 336 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 337 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5b1d7137 | 338 | #else |
6d0f6bcf | 339 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5b1d7137 WD |
340 | #endif |
341 | ||
342 | /* Print Buffer Size */ | |
6d0f6bcf | 343 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
5b1d7137 | 344 | |
6d0f6bcf | 345 | #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ |
5b1d7137 | 346 | |
6d0f6bcf | 347 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
5b1d7137 | 348 | |
6d0f6bcf JCPV |
349 | #ifdef CONFIG_SYS_LSDRAM |
350 | #define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */ | |
351 | #define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ | |
5b1d7137 | 352 | #else |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
354 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ | |
355 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
356 | |
357 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
358 | ||
6d0f6bcf | 359 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
5b1d7137 | 360 | |
5b1d7137 WD |
361 | /* |
362 | * Low Level Configuration Settings | |
363 | * (address mappings, register initial values, etc.) | |
364 | * You should know what you are doing if you make changes here. | |
365 | */ | |
366 | ||
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
368 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
5b1d7137 WD |
369 | |
370 | /*----------------------------------------------------------------------- | |
371 | * Hard Reset Configuration Words | |
372 | */ | |
373 | ||
6d0f6bcf JCPV |
374 | #if defined(CONFIG_SYS_SBC_BOOT_LOW) |
375 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
5b1d7137 | 376 | #else |
6d0f6bcf JCPV |
377 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000) |
378 | #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ | |
5b1d7137 | 379 | |
6d0f6bcf JCPV |
380 | #ifdef CONFIG_SYS_EP8260_H2 |
381 | /* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */ | |
382 | #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\ | |
383 | ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\ | |
384 | ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) ) | |
5b1d7137 | 385 | |
6d0f6bcf | 386 | #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\ |
8bde7f77 | 387 | HRCW_L2CPC01 |\ |
6d0f6bcf | 388 | CONFIG_SYS_SBC_HRCW_IMMR |\ |
5b1d7137 WD |
389 | HRCW_APPC10 |\ |
390 | HRCW_CS10PC01 |\ | |
6d0f6bcf JCPV |
391 | CONFIG_SYS_SBC_MODCK_H |\ |
392 | CONFIG_SYS_SBC_HRCW_BOOT_FLAGS) | |
9dd611b8 | 393 | #else |
6d0f6bcf | 394 | #define CONFIG_SYS_HRCW_MASTER 0x10400245 |
9dd611b8 | 395 | #endif |
5b1d7137 WD |
396 | |
397 | /* no slaves */ | |
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
399 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
400 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
401 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
402 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
403 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
404 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
5b1d7137 WD |
405 | |
406 | /*----------------------------------------------------------------------- | |
407 | * Definitions for initial stack pointer and data area (in DPRAM) | |
408 | */ | |
6d0f6bcf | 409 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 410 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 411 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 412 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5b1d7137 WD |
413 | |
414 | /*----------------------------------------------------------------------- | |
415 | * Start addresses for the final memory configuration | |
416 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
417 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
418 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
5b1d7137 | 419 | */ |
14d0a02a | 420 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
5b1d7137 WD |
421 | |
422 | ||
6d0f6bcf JCPV |
423 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
424 | # define CONFIG_SYS_RAMBOOT | |
5b1d7137 WD |
425 | #endif |
426 | ||
6d0f6bcf JCPV |
427 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
428 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
5b1d7137 WD |
429 | |
430 | /* | |
431 | * For booting Linux, the board info and command line data | |
432 | * have to be in the first 8 MB of memory, since this is | |
433 | * the maximum mapped by the Linux kernel during initialization. | |
434 | */ | |
6d0f6bcf | 435 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5b1d7137 WD |
436 | |
437 | /*----------------------------------------------------------------------- | |
438 | * FLASH and environment organization | |
439 | */ | |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
441 | #ifdef CONFIG_SYS_EP8260_H2 | |
442 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
9dd611b8 | 443 | #else |
6d0f6bcf | 444 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
9dd611b8 | 445 | #endif |
5b1d7137 | 446 | |
6d0f6bcf JCPV |
447 | #ifdef CONFIG_SYS_EP8260_H2 |
448 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ | |
449 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
bd51626c | 450 | #else |
6d0f6bcf JCPV |
451 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
452 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ | |
bd51626c | 453 | #endif |
5b1d7137 | 454 | |
6d0f6bcf | 455 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 456 | # define CONFIG_ENV_IS_IN_FLASH 1 |
5b1d7137 | 457 | |
0e8d1586 | 458 | # ifdef CONFIG_ENV_IN_OWN_SECT |
6d0f6bcf | 459 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 | 460 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
5b1d7137 | 461 | # else |
6d0f6bcf | 462 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
463 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
464 | # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
465 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
5b1d7137 | 466 | #else |
9314cee6 | 467 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 468 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 469 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 470 | #endif /* CONFIG_SYS_RAMBOOT */ |
5b1d7137 WD |
471 | |
472 | /*----------------------------------------------------------------------- | |
473 | * Cache Configuration | |
474 | */ | |
6d0f6bcf | 475 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
5b1d7137 | 476 | |
1bec3d30 | 477 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 478 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5b1d7137 WD |
479 | #endif |
480 | ||
481 | /*----------------------------------------------------------------------- | |
482 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
483 | *----------------------------------------------------------------------- | |
484 | * HID0 also contains cache control - initially enable both caches and | |
485 | * invalidate contents, then the final state leaves only the instruction | |
486 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
487 | * but Soft reset does not. | |
488 | * | |
489 | * HID1 has only read-only information - nothing to set. | |
490 | */ | |
6d0f6bcf | 491 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
5b1d7137 WD |
492 | HID0_DCE |\ |
493 | HID0_ICFI |\ | |
494 | HID0_DCI |\ | |
495 | HID0_IFEM |\ | |
496 | HID0_ABE) | |
6d0f6bcf | 497 | #ifdef CONFIG_SYS_LSDRAM |
5b1d7137 | 498 | /* 8260 local bus is NOT cacheable */ |
6d0f6bcf | 499 | #define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\ |
5b1d7137 WD |
500 | HID0_IFEM |\ |
501 | HID0_ABE |\ | |
502 | HID0_EMCP) | |
6d0f6bcf JCPV |
503 | #else /* !CONFIG_SYS_LSDRAM */ |
504 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ | |
5b1d7137 WD |
505 | HID0_IFEM |\ |
506 | HID0_ABE |\ | |
507 | HID0_EMCP) | |
6d0f6bcf | 508 | #endif /* CONFIG_SYS_LSDRAM */ |
5b1d7137 | 509 | |
6d0f6bcf | 510 | #define CONFIG_SYS_HID2 0 |
5b1d7137 WD |
511 | |
512 | /*----------------------------------------------------------------------- | |
513 | * RMR - Reset Mode Register | |
514 | *----------------------------------------------------------------------- | |
515 | */ | |
6d0f6bcf | 516 | #define CONFIG_SYS_RMR 0 |
5b1d7137 WD |
517 | |
518 | /*----------------------------------------------------------------------- | |
519 | * BCR - Bus Configuration 4-25 | |
520 | *----------------------------------------------------------------------- | |
521 | */ | |
6d0f6bcf | 522 | #define CONFIG_SYS_BCR (BCR_EBM |\ |
5b1d7137 WD |
523 | BCR_PLDP |\ |
524 | BCR_EAV |\ | |
9dd611b8 WD |
525 | BCR_NPQM0) |
526 | ||
5b1d7137 WD |
527 | /*----------------------------------------------------------------------- |
528 | * SIUMCR - SIU Module Configuration 4-31 | |
529 | *----------------------------------------------------------------------- | |
530 | */ | |
6d0f6bcf | 531 | #define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\ |
8bde7f77 WD |
532 | SIUMCR_APPC10 |\ |
533 | SIUMCR_CS10PC01) | |
5b1d7137 | 534 | |
5b1d7137 WD |
535 | /*----------------------------------------------------------------------- |
536 | * SYPCR - System Protection Control 11-9 | |
537 | * SYPCR can only be written once after reset! | |
538 | *----------------------------------------------------------------------- | |
539 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
540 | */ | |
6d0f6bcf | 541 | #ifdef CONFIG_SYS_EP8260_H2 |
a562e1bd WD |
542 | /* TBD: Find out why setting the BMT to 0xff causes the FCC to |
543 | * generate TX buffer underrun errors for large packets under | |
544 | * Linux | |
9dd611b8 | 545 | */ |
6d0f6bcf | 546 | #define CONFIG_SYS_SYPCR_BMT 0x00000600 |
9dd611b8 | 547 | #else |
6d0f6bcf | 548 | #define CONFIG_SYS_SYPCR_BMT SYPCR_BMT |
9dd611b8 WD |
549 | #endif |
550 | ||
6d0f6bcf JCPV |
551 | #ifdef CONFIG_SYS_LSDRAM |
552 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ | |
553 | CONFIG_SYS_SYPCR_BMT |\ | |
8bde7f77 WD |
554 | SYPCR_PBME |\ |
555 | SYPCR_LBME |\ | |
556 | SYPCR_SWP) | |
5b1d7137 | 557 | #else |
6d0f6bcf JCPV |
558 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
559 | CONFIG_SYS_SYPCR_BMT |\ | |
8bde7f77 WD |
560 | SYPCR_PBME |\ |
561 | SYPCR_SWP) | |
5b1d7137 | 562 | #endif |
9dd611b8 | 563 | |
5b1d7137 WD |
564 | /*----------------------------------------------------------------------- |
565 | * TMCNTSC - Time Counter Status and Control 4-40 | |
566 | *----------------------------------------------------------------------- | |
567 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
568 | * and enable Time Counter | |
569 | */ | |
6d0f6bcf | 570 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
8bde7f77 WD |
571 | TMCNTSC_ALR |\ |
572 | TMCNTSC_TCF |\ | |
573 | TMCNTSC_TCE) | |
5b1d7137 WD |
574 | |
575 | /*----------------------------------------------------------------------- | |
576 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
577 | *----------------------------------------------------------------------- | |
578 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
579 | * Periodic timer | |
580 | */ | |
6d0f6bcf JCPV |
581 | #ifdef CONFIG_SYS_EP8260_H2 |
582 | #define CONFIG_SYS_PISCR (PISCR_PS |\ | |
8bde7f77 | 583 | PISCR_PTF |\ |
9dd611b8 WD |
584 | PISCR_PTE) |
585 | #else | |
6d0f6bcf | 586 | #define CONFIG_SYS_PISCR 0 |
9dd611b8 WD |
587 | #endif |
588 | ||
5b1d7137 WD |
589 | /*----------------------------------------------------------------------- |
590 | * SCCR - System Clock Control 9-8 | |
591 | *----------------------------------------------------------------------- | |
592 | */ | |
6d0f6bcf JCPV |
593 | #ifdef CONFIG_SYS_EP8260_H2 |
594 | #define CONFIG_SYS_SCCR (SCCR_DFBRG00) | |
bd51626c | 595 | #else |
6d0f6bcf | 596 | #define CONFIG_SYS_SCCR (SCCR_DFBRG01) |
bd51626c | 597 | #endif |
5b1d7137 WD |
598 | |
599 | /*----------------------------------------------------------------------- | |
600 | * RCCR - RISC Controller Configuration 13-7 | |
601 | *----------------------------------------------------------------------- | |
602 | */ | |
6d0f6bcf | 603 | #define CONFIG_SYS_RCCR 0 |
5b1d7137 WD |
604 | |
605 | /*----------------------------------------------------------------------- | |
606 | * MPTPR - Memory Refresh Timer Prescale Register 10-32 | |
607 | *----------------------------------------------------------------------- | |
608 | */ | |
6d0f6bcf | 609 | #define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK) |
5b1d7137 WD |
610 | |
611 | /* | |
612 | * Init Memory Controller: | |
613 | * | |
614 | * Bank Bus Machine PortSz Device | |
615 | * ---- --- ------- ------ ------ | |
616 | * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) | |
617 | * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) | |
618 | * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) | |
619 | * 3 unused | |
620 | * 4 60x GPCM 8 bit Board Regs, NVRTC | |
621 | * 5 unused | |
622 | * 6 unused | |
623 | * 7 unused | |
624 | * 8 PCMCIA | |
625 | * 9 unused | |
626 | * 10 unused | |
627 | * 11 unused | |
628 | */ | |
629 | ||
630 | /*----------------------------------------------------------------------- | |
631 | * BRx - Base Register | |
632 | * Ref: Section 10.3.1 on page 10-14 | |
633 | * ORx - Option Register | |
634 | * Ref: Section 10.3.2 on page 10-18 | |
635 | *----------------------------------------------------------------------- | |
636 | */ | |
637 | ||
638 | /* Bank 0 - FLASH | |
639 | * | |
640 | */ | |
6d0f6bcf | 641 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
8bde7f77 | 642 | BRx_PS_64 |\ |
5b1d7137 | 643 | BRx_DECC_NONE |\ |
8bde7f77 WD |
644 | BRx_MS_GPCM_P |\ |
645 | BRx_V) | |
5b1d7137 | 646 | |
6d0f6bcf | 647 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
8bde7f77 WD |
648 | ORxG_CSNT |\ |
649 | ORxG_ACS_DIV1 |\ | |
9dd611b8 | 650 | ORxG_SCY_8_CLK |\ |
8bde7f77 | 651 | ORxG_EHTR) |
5b1d7137 WD |
652 | |
653 | /* Bank 1 - SDRAM | |
654 | * PSDRAM | |
655 | */ | |
6d0f6bcf | 656 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
657 | BRx_PS_64 |\ |
658 | BRx_MS_SDRAM_P |\ | |
659 | BRx_V) | |
5b1d7137 | 660 | |
6d0f6bcf | 661 | #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ |
8bde7f77 WD |
662 | ORxS_BPD_4 |\ |
663 | ORxS_ROWST_PBI1_A6 |\ | |
664 | ORxS_NUMR_12) | |
5b1d7137 | 665 | |
6d0f6bcf JCPV |
666 | #ifdef CONFIG_SYS_EP8260_H2 |
667 | #define CONFIG_SYS_PSDMR 0xC34E246E | |
9dd611b8 | 668 | #else |
6d0f6bcf | 669 | #define CONFIG_SYS_PSDMR 0xC34E2462 |
9dd611b8 | 670 | #endif |
5b1d7137 | 671 | |
6d0f6bcf | 672 | #define CONFIG_SYS_PSRT 0x64 |
5b1d7137 | 673 | |
6d0f6bcf | 674 | #ifdef CONFIG_SYS_LSDRAM |
5b1d7137 WD |
675 | /* Bank 2 - SDRAM |
676 | * LSDRAM | |
677 | */ | |
678 | ||
6d0f6bcf | 679 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
680 | BRx_PS_32 |\ |
681 | BRx_MS_SDRAM_L |\ | |
682 | BRx_V) | |
5b1d7137 | 683 | |
6d0f6bcf | 684 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ |
8bde7f77 WD |
685 | ORxS_BPD_4 |\ |
686 | ORxS_ROWST_PBI0_A9 |\ | |
687 | ORxS_NUMR_12) | |
5b1d7137 | 688 | |
6d0f6bcf JCPV |
689 | #define CONFIG_SYS_LSDMR 0x416A2562 |
690 | #define CONFIG_SYS_LSRT 0x64 | |
5b1d7137 | 691 | #else |
6d0f6bcf JCPV |
692 | #define CONFIG_SYS_LSRT 0x0 |
693 | #endif /* CONFIG_SYS_LSDRAM */ | |
5b1d7137 WD |
694 | |
695 | /* Bank 4 - On board registers | |
696 | * NVRTC and BCSR | |
697 | */ | |
6d0f6bcf | 698 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
699 | BRx_PS_8 |\ |
700 | BRx_MS_GPCM_P |\ | |
701 | BRx_V) | |
5b1d7137 | 702 | /* |
6d0f6bcf | 703 | #define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\ |
8bde7f77 WD |
704 | ORxG_CSNT |\ |
705 | ORxG_ACS_DIV1 |\ | |
706 | ORxG_SCY_10_CLK |\ | |
707 | ORxG_TRLX) | |
5b1d7137 | 708 | */ |
6d0f6bcf | 709 | #define CONFIG_SYS_OR4_PRELIM 0xfff00854 |
5b1d7137 | 710 | |
9dd611b8 | 711 | #ifdef _NOT_USED_SINCE_NOT_WORKING_ |
5b1d7137 WD |
712 | /* Bank 8 - On board registers |
713 | * PCMCIA (currently not working!) | |
714 | */ | |
6d0f6bcf | 715 | #define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
716 | BRx_PS_16 |\ |
717 | BRx_MS_GPCM_P |\ | |
718 | BRx_V) | |
5b1d7137 | 719 | |
6d0f6bcf | 720 | #define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\ |
8bde7f77 WD |
721 | ORxG_CSNT |\ |
722 | ORxG_ACS_DIV1 |\ | |
5b1d7137 | 723 | ORxG_SETA |\ |
8bde7f77 | 724 | ORxG_SCY_10_CLK) |
9dd611b8 | 725 | #endif |
5b1d7137 | 726 | |
700a0c64 WD |
727 | /* |
728 | * JFFS2 partitions | |
729 | * | |
730 | */ | |
731 | /* No command line, one static partition, whole device */ | |
68d7d651 | 732 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
733 | #define CONFIG_JFFS2_DEV "nor0" |
734 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
735 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
736 | ||
737 | /* mtdparts command line support */ | |
738 | /* Note: fake mtd_id used, no linux mtd map file */ | |
739 | /* | |
68d7d651 | 740 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
741 | #define MTDIDS_DEFAULT "" |
742 | #define MTDPARTS_DEFAULT "" | |
743 | */ | |
744 | ||
5b1d7137 | 745 | #endif /* __CONFIG_H */ |