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76dd9b6a RS |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * | |
4 | * Configuration settings for the SAMSUNG EXYNOS5 board. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
4c7bb1d2 SG |
9 | #ifndef __CONFIG_EXYNOS5_COMMON_H |
10 | #define __CONFIG_EXYNOS5_COMMON_H | |
76dd9b6a | 11 | |
5ea01ab1 SG |
12 | #define CONFIG_EXYNOS5 /* Exynos5 Family */ |
13 | ||
14 | #include "exynos-common.h" | |
15 | ||
76dd9b6a RS |
16 | #define CONFIG_EXYNOS_SPL |
17 | ||
f44ef7d6 | 18 | #ifdef FTRACE |
76dd9b6a RS |
19 | #define CONFIG_TRACE |
20 | #define CONFIG_CMD_TRACE | |
21 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) | |
22 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
23 | #define CONFIG_TRACE_EARLY | |
24 | #define CONFIG_TRACE_EARLY_ADDR 0x50000000 | |
f44ef7d6 | 25 | #endif |
76dd9b6a RS |
26 | |
27 | /* Enable ACE acceleration for SHA1 and SHA256 */ | |
28 | #define CONFIG_EXYNOS_ACE_SHA | |
29 | #define CONFIG_SHA_HW_ACCEL | |
30 | ||
76dd9b6a RS |
31 | /* Power Down Modes */ |
32 | #define S5P_CHECK_SLEEP 0x00000BAD | |
33 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
34 | #define S5P_CHECK_LPA 0xABAD0000 | |
35 | ||
36 | /* Offset for inform registers */ | |
37 | #define INFORM0_OFFSET 0x800 | |
38 | #define INFORM1_OFFSET 0x804 | |
39 | #define INFORM2_OFFSET 0x808 | |
40 | #define INFORM3_OFFSET 0x80c | |
41 | ||
76dd9b6a | 42 | /* select serial console configuration */ |
76dd9b6a | 43 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 |
76dd9b6a | 44 | |
76dd9b6a RS |
45 | #define CONFIG_CMD_HASH |
46 | ||
76dd9b6a RS |
47 | /* Thermal Management Unit */ |
48 | #define CONFIG_EXYNOS_TMU | |
49 | #define CONFIG_CMD_DTT | |
50 | #define CONFIG_TMU_CMD_DTT | |
51 | ||
76dd9b6a | 52 | /* MMC SPL */ |
76dd9b6a | 53 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
5ea01ab1 | 54 | #define CONFIG_SUPPORT_EMMC_BOOT |
76dd9b6a | 55 | |
76dd9b6a RS |
56 | /* specific .lds file */ |
57 | #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" | |
76dd9b6a | 58 | |
76dd9b6a | 59 | /* Boot Argument Buffer Size */ |
76dd9b6a RS |
60 | /* memtest works on */ |
61 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
62 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
63 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
64 | ||
65 | #define CONFIG_RD_LVL | |
66 | ||
76dd9b6a RS |
67 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
68 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
69 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
70 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
71 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
72 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
73 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
74 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
75 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) | |
76 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE | |
77 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) | |
78 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE | |
79 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) | |
80 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE | |
81 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) | |
82 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE | |
83 | ||
84 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
85 | ||
76dd9b6a RS |
86 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
87 | ||
88 | #define CONFIG_SECURE_BL1_ONLY | |
89 | ||
90 | /* Secure FW size configuration */ | |
91 | #ifdef CONFIG_SECURE_BL1_ONLY | |
92 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ | |
93 | #else | |
94 | #define CONFIG_SEC_FW_SIZE 0 | |
95 | #endif | |
96 | ||
97 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ | |
98 | #define CONFIG_RES_BLOCK_SIZE (512) | |
99 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
100 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ | |
101 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
102 | ||
103 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) | |
104 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) | |
fa253157 | 105 | |
a187559e | 106 | /* U-Boot copy size from boot Media to DRAM.*/ |
76dd9b6a RS |
107 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) |
108 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) | |
109 | ||
76dd9b6a RS |
110 | #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 |
111 | #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) | |
112 | ||
76dd9b6a | 113 | /* I2C */ |
76dd9b6a | 114 | #define CONFIG_SYS_I2C_S3C24X0 |
189d8016 | 115 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ |
76dd9b6a | 116 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 |
76dd9b6a RS |
117 | |
118 | /* SPI */ | |
76dd9b6a | 119 | #ifdef CONFIG_SPI_FLASH |
76dd9b6a RS |
120 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
121 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
76dd9b6a RS |
122 | #endif |
123 | ||
124 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH | |
125 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
126 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
127 | #define CONFIG_ENV_SPI_BUS 1 | |
128 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
129 | #endif | |
130 | ||
76dd9b6a RS |
131 | /* Ethernet Controllor Driver */ |
132 | #ifdef CONFIG_CMD_NET | |
133 | #define CONFIG_SMC911X | |
134 | #define CONFIG_SMC911X_BASE 0x5000000 | |
135 | #define CONFIG_SMC911X_16_BIT | |
136 | #define CONFIG_ENV_SROM_BANK 1 | |
137 | #endif /*CONFIG_CMD_NET*/ | |
138 | ||
76dd9b6a RS |
139 | /* SHA hashing */ |
140 | #define CONFIG_CMD_HASH | |
141 | #define CONFIG_HASH_VERIFY | |
142 | #define CONFIG_SHA1 | |
143 | #define CONFIG_SHA256 | |
144 | ||
145 | /* Enable Time Command */ | |
76dd9b6a | 146 | |
66223787 | 147 | /* USB */ |
66223787 SS |
148 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
149 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
150 | ||
151 | #define CONFIG_USB_HOST_ETHER | |
152 | #define CONFIG_USB_ETHER_ASIX | |
153 | #define CONFIG_USB_ETHER_SMSC95XX | |
76aab9eb | 154 | #define CONFIG_USB_ETHER_RTL8152 |
66223787 | 155 | |
582693b2 AS |
156 | /* USB boot mode */ |
157 | #define CONFIG_USB_BOOTING | |
158 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 | |
159 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 | |
160 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 | |
161 | ||
e6825e03 IC |
162 | #define BOOT_TARGET_DEVICES(func) \ |
163 | func(MMC, mmc, 1) \ | |
164 | func(MMC, mmc, 0) \ | |
165 | func(PXE, pxe, na) \ | |
166 | func(DHCP, dhcp, na) | |
167 | ||
168 | #include <config_distro_bootcmd.h> | |
169 | ||
170 | #ifndef MEM_LAYOUT_ENV_SETTINGS | |
171 | /* 2GB RAM, bootm size of 256M, load scripts after that */ | |
172 | #define MEM_LAYOUT_ENV_SETTINGS \ | |
173 | "bootm_size=0x10000000\0" \ | |
174 | "kernel_addr_r=0x42000000\0" \ | |
175 | "fdt_addr_r=0x43000000\0" \ | |
176 | "ramdisk_addr_r=0x43300000\0" \ | |
177 | "scriptaddr=0x50000000\0" \ | |
178 | "pxefile_addr_r=0x51000000\0" | |
179 | #endif | |
180 | ||
181 | #ifndef EXYNOS_DEVICE_SETTINGS | |
182 | #define EXYNOS_DEVICE_SETTINGS \ | |
183 | "stdin=serial\0" \ | |
184 | "stdout=serial\0" \ | |
185 | "stderr=serial\0" | |
186 | #endif | |
187 | ||
188 | #ifndef EXYNOS_FDTFILE_SETTING | |
189 | #define EXYNOS_FDTFILE_SETTING | |
190 | #endif | |
191 | ||
192 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
193 | EXYNOS_DEVICE_SETTINGS \ | |
194 | EXYNOS_FDTFILE_SETTING \ | |
195 | MEM_LAYOUT_ENV_SETTINGS \ | |
196 | BOOTENV | |
197 | ||
4c7bb1d2 | 198 | #endif /* __CONFIG_EXYNOS5_COMMON_H */ |