[people/ms/u-boot.git] / include / configs / exynos5250-dt.h

/*
 * Copyright (C) 2012 Samsung Electronics
 *
 * Configuration settings for the SAMSUNG EXYNOS5250 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
#define CONFIG_S5P			/* S5P Family */
#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
#define CONFIG_SMDK5250			/* which is in a SMDK5250 */

#include <asm/arch/cpu.h>		/* get chip and board defs */

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Enable fdt support for Exynos5250 */
#define CONFIG_ARCH_DEVICE_TREE		exynos5250
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE

/* Keep L2 Cache Disabled */
#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_TEXT_BASE		0x43E00000

/* input clock of PLL: SMDK5250 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ		24000000

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING

/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
#define MACH_TYPE_SMDK5250		3774
#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250

/* Power Down Modes */
#define S5P_CHECK_SLEEP			0x00000BAD
#define S5P_CHECK_DIDLE			0xBAD00000
#define S5P_CHECK_LPA			0xABAD0000

/* Offset for inform registers */
#define INFORM0_OFFSET			0x800
#define INFORM1_OFFSET			0x804

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))

/* select serial console configuration */
#define CONFIG_SERIAL3			/* use SERIAL 3 */
#define CONFIG_BAUDRATE			115200
#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000

/* Console configuration */
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define EXYNOS_DEVICE_SETTINGS \
		"stdin=serial\0" \
		"stdout=serial,lcd\0" \
		"stderr=serial,lcd\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	EXYNOS_DEVICE_SETTINGS

#define TZPC_BASE_OFFSET		0x10000

/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_S5P_SDHCI

#define CONFIG_BOARD_EARLY_INIT_F

/* PWM */
#define CONFIG_PWM

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Command definition*/
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NET

#define CONFIG_BOOTDELAY		3
#define CONFIG_ZERO_BOOTDELAY_CHECK

/* USB */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
#define CONFIG_USB_STORAGE

/* MMC SPL */
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR	0x02020030

/* specific .lds file */
#define CONFIG_SPL_LDSCRIPT	"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
#define CONFIG_SPL_TEXT_BASE	0x02023400
#define CONFIG_SPL_MAX_SIZE	(14 * 1024)

#define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
#define CONFIG_SYS_PROMPT		"SMDK5250 # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)

#define CONFIG_SYS_HZ			1000

#define CONFIG_RD_LVL

#define CONFIG_NR_DRAM_BANKS	8
#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE

#define CONFIG_SYS_MONITOR_BASE	0x00000000

/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING		" for SMDK5250"

#define CONFIG_SYS_MMC_ENV_DEV		0

#define CONFIG_SECURE_BL1_ONLY

/* Secure FW size configuration */
#ifdef	CONFIG_SECURE_BL1_ONLY
#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
#else
#define	CONFIG_SEC_FW_SIZE		0
#endif

/* Configuration of BL1, BL2, ENV Blocks on mmc */
#define CONFIG_RES_BLOCK_SIZE	(512)
#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */

#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)

/* U-boot copy size from boot Media to DRAM.*/
#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)

#define OM_STAT				(0x1f << 1)
#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
#define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)

#define CONFIG_DOS_PARTITION

#define CONFIG_IRAM_STACK	0x02050000

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)

/* I2C */
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_HARD_I2C
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
#define CONFIG_DRIVER_S3C24X0_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_MAX_I2C_NUM	8
#define CONFIG_SYS_I2C_SLAVE    0x0
#define CONFIG_I2C_EDID

/* PMIC */
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX77686

/* SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH

#ifdef CONFIG_SPI_FLASH
#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED		50000000
#define EXYNOS5_SPI_NUM_CONTROLLERS	5
#endif

#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
#define CONFIG_ENV_SPI_BUS	1
#define CONFIG_ENV_SPI_MAX_HZ	50000000
#endif

/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686

/* SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH

#ifdef CONFIG_SPI_FLASH
#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED		50000000
#define EXYNOS5_SPI_NUM_CONTROLLERS	5
#endif

#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
#define CONFIG_ENV_SPI_BUS	1
#define CONFIG_ENV_SPI_MAX_HZ	50000000
#endif

/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE		0x5000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_ENV_SROM_BANK		1
#endif /*CONFIG_CMD_NET*/

/* Enable PXE Support */
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PXE
#define CONFIG_MENU
#endif

/* Sound */
#define CONFIG_CMD_SOUND
#ifdef CONFIG_CMD_SOUND
#define CONFIG_SOUND
#define CONFIG_I2S
#define CONFIG_SOUND_MAX98095
#define CONFIG_SOUND_WM8994
#endif

/* Enable devicetree support */
#define CONFIG_OF_LIBFDT

/* SHA hashing */
#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
#define CONFIG_SHA1
#define CONFIG_SHA256

/* Display */
#define CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
#define LCD_XRES			2560
#define LCD_YRES			1600
#define LCD_BPP			LCD_COLOR16
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
0aee53ba	1	/*
540b5af2	2	* Copyright (C) 2012 Samsung Electronics
0aee53ba	3	*
540b5af2	4	* Configuration settings for the SAMSUNG EXYNOS5250 board.
0aee53ba CK	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/* High Level Configuration Options */
	29	#define CONFIG_SAMSUNG /* in a SAMSUNG core */
	30	#define CONFIG_S5P /* S5P Family */
	31	#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
	32	#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
	33
	34	#include <asm/arch/cpu.h> /* get chip and board defs */
	35
	36	#define CONFIG_ARCH_CPU_INIT
	37	#define CONFIG_DISPLAY_CPUINFO
	38	#define CONFIG_DISPLAY_BOARDINFO
	39
540b5af2 HR	40	/* Enable fdt support for Exynos5250 */
	41	#define CONFIG_ARCH_DEVICE_TREE exynos5250
	42	#define CONFIG_OF_CONTROL
	43	#define CONFIG_OF_SEPARATE
	44
0aee53ba CK	45	/* Keep L2 Cache Disabled */
	46	#define CONFIG_SYS_DCACHE_OFF
	47
	48	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	49	#define CONFIG_SYS_TEXT_BASE 0x43E00000
	50
	51	/* input clock of PLL: SMDK5250 has 24MHz input clock */
	52	#define CONFIG_SYS_CLK_FREQ 24000000
	53
	54	#define CONFIG_SETUP_MEMORY_TAGS
	55	#define CONFIG_CMDLINE_TAG
	56	#define CONFIG_INITRD_TAG
	57	#define CONFIG_CMDLINE_EDITING
	58
	59	/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
	60	#define MACH_TYPE_SMDK5250 3774
	61	#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
	62
	63	/* Power Down Modes */
	64	#define S5P_CHECK_SLEEP 0x00000BAD
	65	#define S5P_CHECK_DIDLE 0xBAD00000
	66	#define S5P_CHECK_LPA 0xABAD0000
	67
	68	/* Offset for inform registers */
	69	#define INFORM0_OFFSET 0x800
	70	#define INFORM1_OFFSET 0x804
	71
	72	/* Size of malloc() pool */
211e8438	73	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
0aee53ba CK	74
0aee53ba CK	75	/* select serial console configuration */
41222c2a	76	#define CONFIG_SERIAL3 /* use SERIAL 3 */
0aee53ba CK	77	#define CONFIG_BAUDRATE 115200
	78	#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
	79
a2468ded AK	80	/* Console configuration */
	81	#define CONFIG_CONSOLE_MUX
	82	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	83	#define EXYNOS_DEVICE_SETTINGS \
	84	"stdin=serial\0" \
	85	"stdout=serial,lcd\0" \
	86	"stderr=serial,lcd\0"
	87
	88	#define CONFIG_EXTRA_ENV_SETTINGS \
	89	EXYNOS_DEVICE_SETTINGS
	90
0aee53ba CK	91	#define TZPC_BASE_OFFSET 0x10000
	92
	93	/* SD/MMC configuration */
	94	#define CONFIG_GENERIC_MMC
	95	#define CONFIG_MMC
7d2d58b4 JC	96	#define CONFIG_SDHCI
7d2d58b4 JC	97	#define CONFIG_S5P_SDHCI
0aee53ba CK	98
	99	#define CONFIG_BOARD_EARLY_INIT_F
	100
	101	/* PWM */
	102	#define CONFIG_PWM
	103
	104	/* allow to overwrite serial and ethaddr */
	105	#define CONFIG_ENV_OVERWRITE
	106
	107	/* Command definition*/
	108	#include <config_cmd_default.h>
	109
	110	#define CONFIG_CMD_PING
	111	#define CONFIG_CMD_ELF
	112	#define CONFIG_CMD_MMC
	113	#define CONFIG_CMD_EXT2
	114	#define CONFIG_CMD_FAT
bf936210	115	#define CONFIG_CMD_NET
0aee53ba CK	116
	117	#define CONFIG_BOOTDELAY 3
	118	#define CONFIG_ZERO_BOOTDELAY_CHECK
	119
a4dae631 RS	120	/* USB */
	121	#define CONFIG_CMD_USB
	122	#define CONFIG_USB_EHCI
	123	#define CONFIG_USB_EHCI_EXYNOS
	124	#define CONFIG_USB_STORAGE
	125
81e35203 CK	126	/* MMC SPL */
	127	#define CONFIG_SPL
	128	#define COPY_BL2_FNPTR_ADDR 0x02020030
	129
78fbcc95 RS	130	/* specific .lds file */
	131	#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
	132	#define CONFIG_SPL_TEXT_BASE 0x02023400
	133	#define CONFIG_SPL_MAX_SIZE (14 * 1024)
	134
0aee53ba CK	135	#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
	136
	137	/* Miscellaneous configurable options */
	138	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	139	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
0aee53ba CK	140	#define CONFIG_SYS_PROMPT "SMDK5250 # "
	141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	142	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	143	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	144	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
	145	/* Boot Argument Buffer Size */
	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	147	/* memtest works on */
	148	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	149	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
	150	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
	151
	152	#define CONFIG_SYS_HZ 1000
	153
0aee53ba CK	154	#define CONFIG_RD_LVL
0aee53ba CK	155
0aee53ba CK	156	#define CONFIG_NR_DRAM_BANKS 8
	157	#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
	158	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	159	#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
	160	#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
	161	#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
	162	#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
	163	#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
	164	#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
	165	#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
	166	#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
	167	#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
	168	#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
	169	#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
	170	#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
	171	#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
	172	#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
	173	#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
	174
	175	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	176
	177	/* FLASH and environment organization */
	178	#define CONFIG_SYS_NO_FLASH
	179	#undef CONFIG_CMD_IMLS
	180	#define CONFIG_IDENT_STRING " for SMDK5250"
	181
0aee53ba CK	182	#define CONFIG_SYS_MMC_ENV_DEV 0
	183
	184	#define CONFIG_SECURE_BL1_ONLY
	185
	186	/* Secure FW size configuration */
	187	#ifdef CONFIG_SECURE_BL1_ONLY
	188	#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
	189	#else
	190	#define CONFIG_SEC_FW_SIZE 0
	191	#endif
	192
	193	/* Configuration of BL1, BL2, ENV Blocks on mmc */
	194	#define CONFIG_RES_BLOCK_SIZE (512)
	195	#define CONFIG_BL1_SIZE (16 << 10) /16 K reserved for BL1/
	196	#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
	197	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
	198
	199	#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
	200	#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
	201	#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
	202
81e35203 CK	203	/* U-boot copy size from boot Media to DRAM.*/
	204	#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
	205	#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
7a533773 RS	206
	207	#define OM_STAT (0x1f << 1)
	208	#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
	209	#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
	210
0aee53ba CK	211	#define CONFIG_DOS_PARTITION
	212
	213	#define CONFIG_IRAM_STACK 0x02050000
	214
	215	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
	216
c82b050e RS	217	/* I2C */
	218	#define CONFIG_SYS_I2C_INIT_BOARD
	219	#define CONFIG_HARD_I2C
	220	#define CONFIG_CMD_I2C
	221	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
	222	#define CONFIG_DRIVER_S3C24X0_I2C
	223	#define CONFIG_I2C_MULTI_BUS
	224	#define CONFIG_MAX_I2C_NUM 8
	225	#define CONFIG_SYS_I2C_SLAVE 0x0
23b479b2	226	#define CONFIG_I2C_EDID
c82b050e	227
0d146a56 RS	228	/* PMIC */
	229	#define CONFIG_PMIC
	230	#define CONFIG_PMIC_I2C
	231	#define CONFIG_PMIC_MAX77686
	232
3a8a7001 HR	233	/* SPI */
	234	#define CONFIG_ENV_IS_IN_SPI_FLASH
	235	#define CONFIG_SPI_FLASH
	236
	237	#ifdef CONFIG_SPI_FLASH
	238	#define CONFIG_EXYNOS_SPI
	239	#define CONFIG_CMD_SF
	240	#define CONFIG_CMD_SPI
	241	#define CONFIG_SPI_FLASH_WINBOND
	242	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	243	#define CONFIG_SF_DEFAULT_SPEED 50000000
	244	#define EXYNOS5_SPI_NUM_CONTROLLERS 5
	245	#endif
	246
	247	#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
	248	#define CONFIG_ENV_SPI_MODE SPI_MODE_0
	249	#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
	250	#define CONFIG_ENV_SPI_BUS 1
	251	#define CONFIG_ENV_SPI_MAX_HZ 50000000
	252	#endif
	253
0d146a56	254	/* PMIC */
211e8438 RS	255	#define CONFIG_POWER
	256	#define CONFIG_POWER_I2C
	257	#define CONFIG_POWER_MAX77686
0d146a56	258
3a8a7001 HR	259	/* SPI */
	260	#define CONFIG_ENV_IS_IN_SPI_FLASH
	261	#define CONFIG_SPI_FLASH
	262
	263	#ifdef CONFIG_SPI_FLASH
	264	#define CONFIG_EXYNOS_SPI
	265	#define CONFIG_CMD_SF
	266	#define CONFIG_CMD_SPI
	267	#define CONFIG_SPI_FLASH_WINBOND
	268	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	269	#define CONFIG_SF_DEFAULT_SPEED 50000000
	270	#define EXYNOS5_SPI_NUM_CONTROLLERS 5
	271	#endif
	272
	273	#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
	274	#define CONFIG_ENV_SPI_MODE SPI_MODE_0
	275	#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
	276	#define CONFIG_ENV_SPI_BUS 1
	277	#define CONFIG_ENV_SPI_MAX_HZ 50000000
	278	#endif
	279
bf936210 CK	280	/* Ethernet Controllor Driver */
	281	#ifdef CONFIG_CMD_NET
	282	#define CONFIG_SMC911X
	283	#define CONFIG_SMC911X_BASE 0x5000000
	284	#define CONFIG_SMC911X_16_BIT
	285	#define CONFIG_ENV_SROM_BANK 1
	286	#endif /CONFIG_CMD_NET/
	287
061562c4 CK	288	/* Enable PXE Support */
	289	#ifdef CONFIG_CMD_NET
	290	#define CONFIG_CMD_PXE
	291	#define CONFIG_MENU
	292	#endif
	293
36364714 RS	294	/* Sound */
	295	#define CONFIG_CMD_SOUND
	296	#ifdef CONFIG_CMD_SOUND
	297	#define CONFIG_SOUND
	298	#define CONFIG_I2S
cfa6df19	299	#define CONFIG_SOUND_MAX98095
36364714 RS	300	#define CONFIG_SOUND_WM8994
	301	#endif
	302
0aee53ba CK	303	/* Enable devicetree support */
	304	#define CONFIG_OF_LIBFDT
	305
23b479b2 SG	306	/* SHA hashing */
	307	#define CONFIG_CMD_HASH
	308	#define CONFIG_HASH_VERIFY
	309	#define CONFIG_SHA1
	310	#define CONFIG_SHA256
	311
9b572852 AK	312	/* Display */
9b572852 AK	313	#define CONFIG_LCD
99e51629	314	#ifdef CONFIG_LCD
9b572852 AK	315	#define CONFIG_EXYNOS_FB
	316	#define CONFIG_EXYNOS_DP
	317	#define LCD_XRES 2560
	318	#define LCD_YRES 1600
	319	#define LCD_BPP LCD_COLOR16
99e51629	320	#endif
9b572852	321
0aee53ba	322	#endif /* __CONFIG_H */