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ad7a1785 AB |
1 | /* |
2 | * Copyright (C) 2011 | |
3 | * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de> | |
4 | * | |
5 | * Configuration settings for the grasshopper (ICnova AP7000) board | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
ad7a1785 AB |
8 | */ |
9 | #ifndef __GRASSHOPPER_CONFIG_H | |
10 | #define __GRASSHOPPER_CONFIG_H | |
11 | ||
12 | #include <asm/arch/hardware.h> | |
13 | ||
ad7a1785 AB |
14 | #define CONFIG_AT32AP |
15 | #define CONFIG_AT32AP7000 | |
16 | ||
ad7a1785 AB |
17 | /* |
18 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL | |
19 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
20 | * PLL frequency. | |
21 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz | |
22 | */ | |
23 | #define CONFIG_PLL | |
24 | #define CONFIG_SYS_POWER_MANAGER | |
25 | #define CONFIG_SYS_OSC0_HZ 20000000 | |
26 | #define CONFIG_SYS_PLL0_DIV 1 | |
27 | #define CONFIG_SYS_PLL0_MUL 7 | |
28 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
29 | /* | |
30 | * Set the CPU running at: | |
31 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz | |
32 | */ | |
33 | #define CONFIG_SYS_CLKDIV_CPU 0 | |
34 | /* | |
35 | * Set the HSB running at: | |
36 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz | |
37 | */ | |
38 | #define CONFIG_SYS_CLKDIV_HSB 1 | |
39 | /* | |
40 | * Set the PBA running at: | |
41 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz | |
42 | */ | |
43 | #define CONFIG_SYS_CLKDIV_PBA 2 | |
44 | /* | |
45 | * Set the PBB running at: | |
46 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz | |
47 | */ | |
48 | #define CONFIG_SYS_CLKDIV_PBB 1 | |
49 | ||
50 | /* Reserve VM regions for SDRAM and NOR flash */ | |
51 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
52 | ||
53 | /* | |
54 | * The PLLOPT register controls the PLL like this: | |
55 | * icp = PLLOPT<2> | |
56 | * ivco = PLLOPT<1:0> | |
57 | * | |
58 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
59 | */ | |
60 | #define CONFIG_SYS_PLL0_OPT 0x04 | |
61 | ||
62 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 | |
63 | #define CONFIG_USART_ID 1 | |
64 | ||
573feec8 AB |
65 | #define CONFIG_BOARD_EARLY_INIT_R |
66 | ||
ad7a1785 AB |
67 | /* User serviceable stuff */ |
68 | #define CONFIG_CMDLINE_TAG | |
69 | #define CONFIG_SETUP_MEMORY_TAGS | |
70 | #define CONFIG_INITRD_TAG | |
71 | ||
72 | #define CONFIG_STACKSIZE (2048) | |
73 | ||
74 | #define CONFIG_BAUDRATE 115200 | |
75 | ||
ad7a1785 AB |
76 | |
77 | /* | |
78 | * After booting the board for the first time, new ethernet addresses | |
79 | * should be generated and assigned to the environment variables | |
80 | * "ethaddr". This is normally done during production. | |
81 | */ | |
82 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
ad7a1785 AB |
83 | |
84 | /* | |
85 | * BOOTP options | |
86 | */ | |
87 | #define CONFIG_BOOTP_SUBNETMASK | |
88 | #define CONFIG_BOOTP_GATEWAY | |
89 | ||
90 | /* | |
91 | * Command line configuration. | |
92 | */ | |
ad7a1785 | 93 | /* add useful commands */ |
ad7a1785 | 94 | #define CONFIG_CMD_JFFS2 |
ad7a1785 AB |
95 | #define CONFIG_CMD_REGINFO |
96 | ||
ad7a1785 | 97 | #define CONFIG_AUTO_COMPLETE |
ad7a1785 AB |
98 | #define CONFIG_CMDLINE_EDITING |
99 | ||
100 | #define CONFIG_ATMEL_USART | |
101 | #define CONFIG_MACB | |
102 | #define CONFIG_PORTMUX_PIO | |
103 | #define CONFIG_SYS_NR_PIOS 5 | |
104 | #define CONFIG_SYS_HSDRAMC | |
105 | ||
106 | #define CONFIG_SYS_DCACHE_LINESZ 32 | |
107 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
108 | ||
109 | #define CONFIG_NR_DRAM_BANKS 1 | |
110 | ||
111 | #define CONFIG_SYS_FLASH_CFI | |
112 | #define CONFIG_FLASH_CFI_DRIVER | |
113 | ||
114 | #define CONFIG_SYS_FLASH_BASE 0x00000000 | |
115 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
116 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
117 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
118 | ||
119 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
120 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
121 | ||
122 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE | |
123 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
124 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
125 | ||
126 | #define CONFIG_ENV_IS_IN_FLASH | |
127 | /* place u-boot env in flash sector after u-boot */ | |
128 | #define CONFIG_ENV_SIZE 0x10000 | |
129 | #define CONFIG_ENV_ADDR 0x20000 | |
130 | ||
131 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \ | |
132 | CONFIG_SYS_INTRAM_SIZE) | |
133 | ||
134 | #define CONFIG_SYS_MALLOC_LEN (256*1024) | |
ad7a1785 AB |
135 | |
136 | /* Allow 4MB for the kernel run-time image */ | |
137 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) | |
138 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
139 | ||
140 | /* Other configuration settings that shouldn't have to change all that often */ | |
ad7a1785 AB |
141 | #define CONFIG_SYS_CBSIZE 256 |
142 | #define CONFIG_SYS_MAXARGS 16 | |
143 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
144 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
145 | #define CONFIG_SYS_LONGHELP | |
146 | ||
147 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE | |
148 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) | |
ad7a1785 AB |
149 | |
150 | #endif /* __GRASSHOPPER_CONFIG_H */ | |
151 | /* vim: set ts=8 noet: */ |