[people/ms/u-boot.git] / include / configs / imx31_litekit.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the LogicPD i.MX31 Litekit board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
#define CONFIG_MX31		1    /* in a mx31 */
#define CONFIG_MX31_CLK32	32000

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_TEXT_BASE	0xa0000000

#define CONFIG_MACH_TYPE	MACH_TYPE_MX31LITE

/* Temporarily disabled */
#if 0
#define CONFIG_OF_LIBFDT		1
#define CONFIG_FIT			1
#define CONFIG_FIT_VERBOSE		1
#endif

#define CONFIG_CMDLINE_TAG		1    /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE
#define CONFIG_MXC_GPIO

#define CONFIG_HARD_SPI		1
#define CONFIG_MXC_SPI		1
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	1000000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN	32
#define CONFIG_RTC_MC13XXX

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND

#define CONFIG_BOOTDELAY	3

#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.23.168
#define CONFIG_SERVERIP		192.168.23.2

#define	CONFIG_EXTRA_ENV_SETTINGS											\
	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"							\
	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
	"bootcmd=run bootcmd_net\0"											\
	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0"		\
	"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"


#define CONFIG_SMC911X		1
#define CONFIG_SMC911X_BASE	(CS4_BASE + 0x00020000)
#define CONFIG_SMC911X_32_BIT	1

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"uboot> "
#define CONFIG_SYS_CBSIZE		256  /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		16          /* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */

#define CONFIG_CMDLINE_EDITING	1

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1           /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	     /* max number of sectors on one chip */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */

#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x001f0000)
#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		(64 * 1024)

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/*
 * JFFS2 partitions
 */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV	"nor0"

/*
 * NAND flash
 */
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC

#endif /* __CONFIG_H */
Commit	Line	Data
caebc95b SH	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Kshitij Gupta <kshitij@ti.com>
	6	*
7064122c	7	* Configuration settings for the LogicPD i.MX31 Litekit board.
caebc95b	8	*
3765b3e7	9	* SPDX-License-Identifier: GPL-2.0+
caebc95b SH	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
86271115	15	#include <asm/arch/imx-regs.h>
e7ae84d6	16
caebc95b SH	17	/* High Level Configuration Options */
	18	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	19	#define CONFIG_MX31 1 /* in a mx31 */
caebc95b SH	20	#define CONFIG_MX31_CLK32 32000
	21
	22	#define CONFIG_DISPLAY_CPUINFO
	23	#define CONFIG_DISPLAY_BOARDINFO
	24
ac88e66e FE	25	#define CONFIG_SYS_TEXT_BASE 0xa0000000
ac88e66e FE	26
4c414387 FE	27	#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
4c414387 FE	28
caebc95b SH	29	/* Temporarily disabled */
	30	#if 0
	31	#define CONFIG_OF_LIBFDT 1
	32	#define CONFIG_FIT 1
	33	#define CONFIG_FIT_VERBOSE 1
	34	#endif
	35
	36	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	37	#define CONFIG_SETUP_MEMORY_TAGS 1
	38	#define CONFIG_INITRD_TAG 1
	39
	40	/*
	41	* Size of malloc() pool
	42	*/
6d0f6bcf	43	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
caebc95b SH	44
	45	/*
	46	* Hardware drivers
	47	*/
	48
40f6fffe SB	49	#define CONFIG_MXC_UART
40f6fffe SB	50	#define CONFIG_MXC_UART_BASE UART1_BASE
87e14f0f	51	#define CONFIG_MXC_GPIO
caebc95b	52
f9204e15 ML	53	#define CONFIG_HARD_SPI 1
f9204e15 ML	54	#define CONFIG_MXC_SPI 1
d255bb0e	55	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	56	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
f9204e15	57
2672d5db	58	/* PMIC Controller */
be3b51aa ŁM	59	#define CONFIG_POWER
	60	#define CONFIG_POWER_SPI
	61	#define CONFIG_POWER_FSL
dfe5e14f SB	62	#define CONFIG_FSL_PMIC_BUS 1
	63	#define CONFIG_FSL_PMIC_CS 0
	64	#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95	65	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
2672d5db	66	#define CONFIG_FSL_PMIC_BITLEN 32
4e8b7544	67	#define CONFIG_RTC_MC13XXX
f9204e15	68
caebc95b SH	69	/* allow to overwrite serial and ethaddr */
	70	#define CONFIG_ENV_OVERWRITE
	71	#define CONFIG_CONS_INDEX 1
	72	#define CONFIG_BAUDRATE 115200
caebc95b SH	73
	74	/***********************************************************
	75	* Command definition
	76	***********************************************************/
	77
	78	#include <config_cmd_default.h>
	79
	80	#define CONFIG_CMD_MII
	81	#define CONFIG_CMD_PING
f9204e15 ML	82	#define CONFIG_CMD_SPI
f9204e15 ML	83	#define CONFIG_CMD_DATE
ba6adeb4	84	#define CONFIG_CMD_NAND
caebc95b SH	85
	86	#define CONFIG_BOOTDELAY 3
	87
	88	#define CONFIG_NETMASK 255.255.255.0
	89	#define CONFIG_IPADDR 192.168.23.168
	90	#define CONFIG_SERVERIP 192.168.23.2
	91
	92	#define CONFIG_EXTRA_ENV_SETTINGS \
	93	"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
	94	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	95	"bootcmd=run bootcmd_net\0" \
	96	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
	97	"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
	98
	99
736fead8 BW	100	#define CONFIG_SMC911X 1
	101	#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
	102	#define CONFIG_SMC911X_32_BIT 1
caebc95b SH	103
	104	/*
	105	* Miscellaneous configurable options
	106	*/
6d0f6bcf JCPV	107	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	108	#define CONFIG_SYS_PROMPT "uboot> "
	109	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
caebc95b	110	/* Print Buffer Size */
6d0f6bcf JCPV	111	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	112	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	113	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
caebc95b	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
6d0f6bcf JCPV	116	#define CONFIG_SYS_MEMTEST_END 0x10000
caebc95b	117
6d0f6bcf	118	#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
caebc95b	119
caebc95b SH	120	#define CONFIG_CMDLINE_EDITING 1
caebc95b SH	121
caebc95b SH	122	/*-----------------------------------------------------------------------
	123	* Physical Memory Map
	124	*/
	125	#define CONFIG_NR_DRAM_BANKS 1
e7ae84d6	126	#define PHYS_SDRAM_1 CSD0_BASE
caebc95b	127	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
4e37731a	128	#define CONFIG_BOARD_EARLY_INIT_F
caebc95b	129
7a5faf08	130	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
68a75d0b	131	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
553f0982	132	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
25ddd1fb	133	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
68a75d0b ML	134	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
68a75d0b ML	135
caebc95b SH	136	/*-----------------------------------------------------------------------
	137	* FLASH and environment organization
	138	*/
6d0f6bcf JCPV	139	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	140	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	141	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	142	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
caebc95b	143
6d0f6bcf	144	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
5a1aceb0	145	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	146	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
0e8d1586 JCPV	147	#define CONFIG_ENV_SIZE (64 * 1024)
caebc95b SH	148
	149	/*-----------------------------------------------------------------------
	150	* CFI FLASH driver setup
	151	*/
6d0f6bcf	152	#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a	153	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
6d0f6bcf JCPV	154	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
6d0f6bcf JCPV	155	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
caebc95b SH	156
caebc95b SH	157	/* timeout values are in ticks */
6d0f6bcf JCPV	158	#define CONFIG_SYS_FLASH_ERASE_TOUT (100CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	159	#define CONFIG_SYS_FLASH_WRITE_TOUT (100CONFIG_SYS_HZ) / Timeout for Flash Write */
caebc95b SH	160
	161	/*
	162	* JFFS2 partitions
	163	*/
68d7d651	164	#undef CONFIG_CMD_MTDPARTS
caebc95b SH	165	#define CONFIG_JFFS2_DEV "nor0"
caebc95b SH	166
ba6adeb4 ML	167	/*
	168	* NAND flash
	169	*/
	170	#define CONFIG_NAND_MXC
	171	#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
	172	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	173	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	174	#define CONFIG_MXC_NAND_HWECC
	175
caebc95b	176	#endif /* __CONFIG_H */