[people/ms/u-boot.git] / include / configs / imx31_phycore.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the phyCORE-i.MX31 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

/* High Level Configuration Options */
#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
#define CONFIG_MX31			/* in a mx31 */
#define CONFIG_MX31_CLK32	32000

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM		1 /* I2C2 */
#define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE		UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C

#define CONFIG_BOOTDELAY	3

#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
					"1536k(kernel),-(root)"

#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.23.168
#define CONFIG_SERVERIP		192.168.23.2

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
	"bootargs_flash=setenv bootargs $(bootargs) "			\
		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"bootcmd=run bootcmd_net\0"					\
	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
		"tftpboot 0x80000000 $(uimage);bootm\0"			\
	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
		"bootm 0x80000000\0"					\
	"unlock=yes\0"							\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
		"protect off 0xa0000000 +0x20000;"			\
		"erase 0xa0000000 +0x20000;"				\
		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
		"erase 0xa0040000 +0x180000;"				\
		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
		"erase 0xa01c0000 0xa1ffffff;"				\
		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
		"sync:1241513985,vmode:0\0"


#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	0xa8000000
#define CONFIG_SMC911X_32_BIT

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"uboot> "
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE		256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS		16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */

#define CONFIG_CMDLINE_EDITING

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x80000000
#define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_TEXT_BASE		0xA0000000

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		0xa0000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
#define CONFIG_ENV_SIZE				4096
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */

/*
 * Timeout for Flash Erase and Flash Write
 * timeout values are in ticks
 */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)

/*
 * JFFS2 partitions
 */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV	"nor0"

/* EET platform additions */
#ifdef CONFIG_IMX31_PHYCORE_EET
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_MXC_GPIO

#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
#define CONFIG_CMD_SPI

#define CONFIG_S6E63D6

#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
5ad86216 SH	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Kshitij Gupta <kshitij@ti.com>
	6	*
7064122c	7	* Configuration settings for the phyCORE-i.MX31 board.
5ad86216	8	*
3765b3e7	9	* SPDX-License-Identifier: GPL-2.0+
5ad86216 SH	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
953ee4d0 FE	15	#include <asm/arch/imx-regs.h>
953ee4d0 FE	16
6ac1c903 AG	17	/* High Level Configuration Options */
	18	#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
	19	#define CONFIG_MX31 /* in a mx31 */
5ad86216 SH	20	#define CONFIG_MX31_CLK32 32000
	21
	22	#define CONFIG_DISPLAY_CPUINFO
	23	#define CONFIG_DISPLAY_BOARDINFO
	24
6ac1c903 AG	25	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	26	#define CONFIG_SETUP_MEMORY_TAGS
	27	#define CONFIG_INITRD_TAG
5ad86216 SH	28
	29	/*
	30	* Size of malloc() pool
	31	*/
62a22dca	32	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
5ad86216 SH	33
	34	/*
	35	* Hardware drivers
	36	*/
	37
b089d039	38	#define CONFIG_SYS_I2C
	39	#define CONFIG_SYS_I2C_MXC
	40	#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
de6f604d	41	#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
5ad86216	42
6ac1c903	43	#define CONFIG_MXC_UART
40f6fffe	44	#define CONFIG_MXC_UART_BASE UART1_BASE
5ad86216 SH	45
	46	/* allow to overwrite serial and ethaddr */
	47	#define CONFIG_ENV_OVERWRITE
	48	#define CONFIG_CONS_INDEX 1
	49	#define CONFIG_BAUDRATE 115200
5ad86216 SH	50
	51	/***********************************************************
	52	* Command definition
	53	***********************************************************/
	54
	55	#include <config_cmd_default.h>
	56
	57	#define CONFIG_CMD_PING
	58	#define CONFIG_CMD_EEPROM
	59	#define CONFIG_CMD_I2C
	60
	61	#define CONFIG_BOOTDELAY 3
	62
6ac1c903 AG	63	#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
6ac1c903 AG	64	"1536k(kernel),-(root)"
5ad86216 SH	65
	66	#define CONFIG_NETMASK 255.255.255.0
	67	#define CONFIG_IPADDR 192.168.23.168
	68	#define CONFIG_SERVERIP 192.168.23.2
	69
6ac1c903 AG	70	#define CONFIG_EXTRA_ENV_SETTINGS \
	71	"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
	72	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
	73	"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	74	"bootargs_flash=setenv bootargs $(bootargs) " \
	75	"root=/dev/mtdblock2 rootfstype=jffs2\0" \
	76	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
	77	"bootcmd=run bootcmd_net\0" \
	78	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
	79	"tftpboot 0x80000000 $(uimage);bootm\0" \
	80	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
	81	"bootm 0x80000000\0" \
	82	"unlock=yes\0" \
	83	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	84	"prg_uboot=tftpboot 0x80000000 $(uboot);" \
	85	"protect off 0xa0000000 +0x20000;" \
	86	"erase 0xa0000000 +0x20000;" \
	87	"cp.b 0x80000000 0xa0000000 $(filesize)\0" \
	88	"prg_kernel=tftpboot 0x80000000 $(uimage);" \
	89	"erase 0xa0040000 +0x180000;" \
	90	"cp.b 0x80000000 0xa0040000 $(filesize)\0" \
	91	"prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
	92	"erase 0xa01c0000 0xa1ffffff;" \
	93	"cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
	94	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
	95	"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
	96	"sync:1241513985,vmode:0\0"
	97
	98
	99	#define CONFIG_SMC911X
736fead8	100	#define CONFIG_SMC911X_BASE 0xa8000000
6ac1c903	101	#define CONFIG_SMC911X_32_BIT
5ad86216 SH	102
	103	/*
	104	* Miscellaneous configurable options
	105	*/
6d0f6bcf JCPV	106	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	107	#define CONFIG_SYS_PROMPT "uboot> "
6ac1c903 AG	108	/* Console I/O Buffer Size */
6ac1c903 AG	109	#define CONFIG_SYS_CBSIZE 256
5ad86216	110	/* Print Buffer Size */
6ac1c903 AG	111	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	112	sizeof(CONFIG_SYS_PROMPT) + 16)
	113	/* max number of command args */
	114	#define CONFIG_SYS_MAXARGS 16
	115	/* Boot Argument Buffer Size */
	116	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5ad86216	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
6d0f6bcf JCPV	119	#define CONFIG_SYS_MEMTEST_END 0x10000
5ad86216	120
6d0f6bcf	121	#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
5ad86216	122
6ac1c903	123	#define CONFIG_CMDLINE_EDITING
5ad86216	124
6ac1c903	125	/*
5ad86216 SH	126	* Physical Memory Map
5ad86216 SH	127	*/
6ac1c903 AG	128	#define CONFIG_NR_DRAM_BANKS 1
	129	#define PHYS_SDRAM_1 0x80000000
	130	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
953ee4d0 FE	131	#define CONFIG_BOARD_EARLY_INIT_F
	132	#define CONFIG_SYS_TEXT_BASE 0xA0000000
	133
	134	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	135	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	136	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	137	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	138	GENERATED_GBL_DATA_SIZE)
	139	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	140	CONFIG_SYS_GBL_DATA_OFFSET)
5ad86216	141
6ac1c903	142	/*
5ad86216 SH	143	* FLASH and environment organization
5ad86216 SH	144	*/
6d0f6bcf	145	#define CONFIG_SYS_FLASH_BASE 0xa0000000
6ac1c903 AG	146	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
	147	#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
	148	/* Monitor at beginning of flash */
	149	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	150
	151	#define CONFIG_ENV_IS_IN_EEPROM
	152	#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
	153	#define CONFIG_ENV_SIZE 4096
6d0f6bcf	154	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
6ac1c903 AG	155	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
	156	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
	157	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
5ad86216	158
6ac1c903	159	/*
5ad86216 SH	160	* CFI FLASH driver setup
5ad86216 SH	161	*/
6ac1c903 AG	162	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
	163	#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
	164	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
	165	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
5ad86216	166
6ac1c903 AG	167	/*
	168	* Timeout for Flash Erase and Flash Write
	169	* timeout values are in ticks
	170	*/
	171	#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
	172	#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
5ad86216 SH	173
	174	/*
	175	* JFFS2 partitions
	176	*/
68d7d651	177	#undef CONFIG_CMD_MTDPARTS
5ad86216 SH	178	#define CONFIG_JFFS2_DEV "nor0"
5ad86216 SH	179
a2bb7105 GL	180	/* EET platform additions */
a2bb7105 GL	181	#ifdef CONFIG_IMX31_PHYCORE_EET
9660e442	182	#define CONFIG_BOARD_LATE_INIT
a2bb7105	183
c4ea1424	184	#define CONFIG_MXC_GPIO
a2bb7105	185
6ac1c903 AG	186	#define CONFIG_HARD_SPI
6ac1c903 AG	187	#define CONFIG_MXC_SPI
a2bb7105 GL	188	#define CONFIG_CMD_SPI
a2bb7105 GL	189
6ac1c903	190	#define CONFIG_S6E63D6
a2bb7105	191
62a22dca HR	192	#define CONFIG_VIDEO
	193	#define CONFIG_CFB_CONSOLE
	194	#define CONFIG_VIDEO_MX3
	195	#define CONFIG_VIDEO_LOGO
	196	#define CONFIG_VIDEO_SW_CURSOR
	197	#define CONFIG_VGA_AS_SINGLE_DEVICE
	198	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	199	#define CONFIG_SPLASH_SCREEN
	200	#define CONFIG_CMD_BMP
	201	#define CONFIG_BMP_16BPP
a2bb7105 GL	202	#endif
a2bb7105 GL	203
5ad86216	204	#endif /* __CONFIG_H */