[people/ms/u-boot.git] / include / configs / inka4x0.h

/*
 * (C) Copyright 2009
 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
#define CONFIG_INKA4X0		1	/* INKA4x0 board		*/

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFE00000	boot low
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFE00000	/* Standard: boot low */
#endif
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/

#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_IPADDR		192.168.100.2
#define	CONFIG_SERVERIP		192.168.100.1
#define	CONFIG_NETMASK		255.255.255.0
#define HOSTNAME		inka4x0
#define CONFIG_BOOTFILE		"/tftpboot/inka4x0/uImage"
#define	CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"enable_disp=mw.l 100000 04000000 1;"				\
		"cp.l 100000 f0000b20 1;"				\
		"cp.l 100000 f0000b28 1\0"				\
	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
		"run ideargs addip addcons enable_disp;bootm\0"		\
	"brightness=255\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run ide_boot"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_BASE		0xffe00000
#define CONFIG_SYS_FLASH_SIZE		0x00200000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/*
 * SDRAM controller configuration
 */
#undef CONFIG_SDR_MT48LC16M16A2
#undef CONFIG_DDR_MT46V16M16
#undef CONFIG_DDR_MT46V32M16
#undef CONFIG_DDR_HYB25D512160BF
#define CONFIG_DDR_K4H511638C

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM

/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)

#ifdef CONFIG_POST
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII

/*
 * GPIO configuration
 *
 * use CS1 as gpio_wkup_6 output
 *	Bit 0 (mask: 0x80000000): 0
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 *	      EEPROM
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01501444

/*
 * RTC configuration
 */
#define CONFIG_RTC_RTC4543 	1	/* use external RTC */

/*
 * Software (bit-bang) three wire serial configuration
 *
 * Note that we need the ifdefs because otherwise compilation of
 * mkimage.c fails.
 */
#define CONFIG_SOFT_TWS		1

#ifdef TWS_IMPLEMENTATION
#include <mpc5xxx.h>
#include <asm/io.h>

#define TWS_CE		MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
#define TWS_WR		MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
#define TWS_DATA	MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
#define TWS_CLK		MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */

static inline void tws_ce(unsigned bit)
{
	struct mpc5xxx_wu_gpio *wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	if (bit)
		setbits_8(&wu_gpio->dvo, TWS_CE);
	else
		clrbits_8(&wu_gpio->dvo, TWS_CE);
}

static inline void tws_wr(unsigned bit)
{
	struct mpc5xxx_wu_gpio *wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	if (bit)
		setbits_8(&wu_gpio->dvo, TWS_WR);
	else
		clrbits_8(&wu_gpio->dvo, TWS_WR);
}

static inline void tws_clk(unsigned bit)
{
	struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	if (bit)
		setbits_8(&gpio->sint_dvo, TWS_CLK);
	else
		clrbits_8(&gpio->sint_dvo, TWS_CLK);
}

static inline void tws_data(unsigned bit)
{
	struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	if (bit)
		setbits_8(&gpio->sint_dvo, TWS_DATA);
	else
		clrbits_8(&gpio->sint_dvo, TWS_DATA);
}

static inline unsigned tws_data_read(void)
{
	struct mpc5xxx_gpio *gpio =
			(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	return !!(in_8(&gpio->sint_ival) & TWS_DATA);
}

static inline void tws_data_config_output(unsigned output)
{
	struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	if (output)
		setbits_8(&gpio->sint_ddr, TWS_DATA);
	else
		clrbits_8(&gpio->sint_ddr, TWS_DATA);
}
#endif /* TWS_IMPLEMENTATION */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* 32Mbit SRAM @0x30000000 */
#define CONFIG_SYS_CS1_START		0x30000000
#define CONFIG_SYS_CS1_SIZE		0x00400000
#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */

/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CONFIG_SYS_CS2_START		0x80000000
#define CONFIG_SYS_CS2_SIZE		0x0001000
#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */

/* GPIO in @0x30400000 */
#define CONFIG_SYS_CS3_START		0x30400000
#define CONFIG_SYS_CS3_SIZE		0x00100000
#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_OHCI
#define CONFIG_USB_CLOCK	0x00015555
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/

#define CONFIG_ATAPI            1

#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */

#endif /* __CONFIG_H */
Commit	Line	Data
138ff60c	1	/*
e979e85f DZ	2	* (C) Copyright 2009
	3	* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
	4	*
414eec35	5	* (C) Copyright 2003-2005
138ff60c WD	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
138ff60c WD	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
138ff60c WD	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	* (easy to change)
	17	*/
	18
b2a6dfe4 MY	19	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
b2a6dfe4 MY	20	#define CONFIG_INKA4X0 1 /* INKA4x0 board */
138ff60c	21
2ae18241 WD	22	/*
	23	* Valid values for CONFIG_SYS_TEXT_BASE are:
	24	* 0xFFE00000 boot low
	25	* 0x00100000 boot from RAM (for testing only)
	26	*/
	27	#ifndef CONFIG_SYS_TEXT_BASE
	28	#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
	29	#endif
2ced53e1	30	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
2ae18241	31
6d0f6bcf	32	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
138ff60c	33
151ab83a WD	34	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
151ab83a WD	35
31d82672 BB	36	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	37
138ff60c WD	38	/*
	39	* Serial console configuration
	40	*/
151ab83a WD	41	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
151ab83a WD	42	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	43	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
138ff60c	44
436be29c WD	45	/*
	46	* PCI Mapping:
	47	* 0x40000000 - 0x4fffffff - PCI Memory
	48	* 0x50000000 - 0x50ffffff - PCI IO Space
	49	*/
436be29c	50	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	51	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
436be29c WD	52
	53	#define CONFIG_PCI_MEM_BUS 0x40000000
	54	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	55	#define CONFIG_PCI_MEM_SIZE 0x10000000
	56
	57	#define CONFIG_PCI_IO_BUS 0x50000000
	58	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	59	#define CONFIG_PCI_IO_SIZE 0x01000000
	60
6d0f6bcf	61	#define CONFIG_SYS_XLB_PIPELINING 1
436be29c WD	62
	63	/* Partitions */
	64	#define CONFIG_MAC_PARTITION
	65	#define CONFIG_DOS_PARTITION
	66	#define CONFIG_ISO_PARTITION
	67
7f5c0157 JL	68	/*
	69	* BOOTP options
	70	*/
	71	#define CONFIG_BOOTP_BOOTFILESIZE
	72	#define CONFIG_BOOTP_BOOTPATH
	73	#define CONFIG_BOOTP_GATEWAY
	74	#define CONFIG_BOOTP_HOSTNAME
	75
138ff60c	76	/*
1d2c6bc4	77	* Command line configuration.
138ff60c	78	*/
e979e85f	79	#define CONFIG_CMD_DATE
1d2c6bc4	80	#define CONFIG_CMD_IDE
1d2c6bc4	81	#define CONFIG_CMD_PCI
1d2c6bc4	82
b05dcb58 WD	83	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
b05dcb58 WD	84
14d0a02a	85	#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
6d0f6bcf	86	# define CONFIG_SYS_LOWBOOT 1
138ff60c WD	87	#endif
	88
	89	/*
	90	* Autobooting
	91	*/
138ff60c WD	92
138ff60c WD	93	#define CONFIG_PREBOOT "echo;" \
32bf3d14	94	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
138ff60c WD	95	"echo"
	96
	97	#undef CONFIG_BOOTARGS
	98
84e106c0 WD	99	#define CONFIG_IPADDR 192.168.100.2
	100	#define CONFIG_SERVERIP 192.168.100.1
	101	#define CONFIG_NETMASK 255.255.255.0
	102	#define HOSTNAME inka4x0
b3f44c21	103	#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
8b3637c6	104	#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
84e106c0	105
138ff60c WD	106	#define CONFIG_EXTRA_ENV_SETTINGS \
	107	"netdev=eth0\0" \
	108	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	109	"nfsroot=${serverip}:${rootpath}\0" \
138ff60c	110	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	111	"addip=setenv bootargs ${bootargs} " \
	112	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	113	":${hostname}:${netdev}:off panic=1\0" \
84e106c0 WD	114	"addcons=setenv bootargs ${bootargs} " \
	115	"console=ttyS0,${baudrate}\0" \
	116	"flash_nfs=run nfsargs addip addcons;" \
fe126d8b	117	"bootm ${kernel_addr}\0" \
84e106c0 WD	118	"net_nfs=tftp 200000 ${bootfile};" \
	119	"run nfsargs addip addcons;bootm\0" \
	120	"enable_disp=mw.l 100000 04000000 1;" \
	121	"cp.l 100000 f0000b20 1;" \
	122	"cp.l 100000 f0000b28 1\0" \
	123	"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
	124	"ide_boot=ext2load ide 0:1 200000 uImage;" \
f23cb34c	125	"run ideargs addip addcons enable_disp;bootm\0" \
84e106c0	126	"brightness=255\0" \
138ff60c WD	127	""
138ff60c WD	128
84e106c0	129	#define CONFIG_BOOTCOMMAND "run ide_boot"
138ff60c WD	130
	131	/*
	132	* IPB Bus clocking configuration.
	133	*/
6d0f6bcf	134	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
138ff60c WD	135
	136	/*
	137	* Flash configuration
	138	*/
6d0f6bcf	139	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	140	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	141	#define CONFIG_SYS_FLASH_BASE 0xffe00000
	142	#define CONFIG_SYS_FLASH_SIZE 0x00200000
	143	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	144	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	145	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	146	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
138ff60c WD	147
	148	/*
	149	* Environment settings
	150	*/
5a1aceb0	151	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	152	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586 JCPV	153	#define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	154	#define CONFIG_ENV_SECT_SIZE 0x2000
138ff60c	155	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf	156	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
138ff60c WD	157
	158	/*
	159	* Memory map
	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_MBAR 0xF0000000
	162	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	163	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
138ff60c	164
5fb6d719 MB	165	/*
	166	* SDRAM controller configuration
	167	*/
	168	#undef CONFIG_SDR_MT48LC16M16A2
	169	#undef CONFIG_DDR_MT46V16M16
	170	#undef CONFIG_DDR_MT46V32M16
	171	#undef CONFIG_DDR_HYB25D512160BF
	172	#define CONFIG_DDR_K4H511638C
138ff60c WD	173
138ff60c WD	174	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	175	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
800eb096	176
138ff60c	177	/* preserve space for the post_word at end of on-chip SRAM */
800eb096 MZ	178	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
	179
	180	#ifdef CONFIG_POST
553f0982	181	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
138ff60c	182	#else
553f0982	183	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
138ff60c WD	184	#endif
138ff60c WD	185
25ddd1fb	186	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	187	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
138ff60c	188
14d0a02a	189	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	190	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	191	# define CONFIG_SYS_RAMBOOT 1
138ff60c WD	192	#endif
138ff60c WD	193
6d0f6bcf JCPV	194	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	195	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	196	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
138ff60c WD	197
	198	/*
	199	* Ethernet configuration
	200	*/
	201	#define CONFIG_MPC5xxx_FEC 1
86321fc1	202	#define CONFIG_MPC5xxx_FEC_MII100
138ff60c	203	/*
86321fc1	204	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
138ff60c	205	*/
86321fc1	206	/* #define CONFIG_MPC5xxx_FEC_MII10 */
138ff60c	207	#define CONFIG_PHY_ADDR 0x00
84e106c0	208	#define CONFIG_MII
138ff60c WD	209
	210	/*
	211	* GPIO configuration
	212	*
9f709b6c WD	213	* use CS1 as gpio_wkup_6 output
9f709b6c WD	214	* Bit 0 (mask: 0x80000000): 0
138ff60c WD	215	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	216	* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
	217	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
	218	* EEPROM
	219	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
e979e85f DZ	220	* use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
	221	* use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
	222	* use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
138ff60c	223	*/
e979e85f	224	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
138ff60c WD	225
	226	/*
	227	* RTC configuration
	228	*/
e979e85f DZ	229	#define CONFIG_RTC_RTC4543 1 /* use external RTC */
	230
	231	/*
	232	* Software (bit-bang) three wire serial configuration
	233	*
	234	* Note that we need the ifdefs because otherwise compilation of
	235	* mkimage.c fails.
	236	*/
	237	#define CONFIG_SOFT_TWS 1
	238
	239	#ifdef TWS_IMPLEMENTATION
	240	#include <mpc5xxx.h>
	241	#include <asm/io.h>
	242
	243	#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
	244	#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
	245	#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
	246	#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
	247
	248	static inline void tws_ce(unsigned bit)
	249	{
	250	struct mpc5xxx_wu_gpio *wu_gpio =
	251	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	252	if (bit)
	253	setbits_8(&wu_gpio->dvo, TWS_CE);
	254	else
	255	clrbits_8(&wu_gpio->dvo, TWS_CE);
	256	}
	257
	258	static inline void tws_wr(unsigned bit)
	259	{
	260	struct mpc5xxx_wu_gpio *wu_gpio =
	261	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	262	if (bit)
	263	setbits_8(&wu_gpio->dvo, TWS_WR);
	264	else
	265	clrbits_8(&wu_gpio->dvo, TWS_WR);
	266	}
	267
	268	static inline void tws_clk(unsigned bit)
	269	{
	270	struct mpc5xxx_gpio *gpio =
	271	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	272	if (bit)
	273	setbits_8(&gpio->sint_dvo, TWS_CLK);
	274	else
	275	clrbits_8(&gpio->sint_dvo, TWS_CLK);
	276	}
	277
	278	static inline void tws_data(unsigned bit)
	279	{
	280	struct mpc5xxx_gpio *gpio =
	281	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	282	if (bit)
	283	setbits_8(&gpio->sint_dvo, TWS_DATA);
	284	else
	285	clrbits_8(&gpio->sint_dvo, TWS_DATA);
	286	}
	287
	288	static inline unsigned tws_data_read(void)
	289	{
	290	struct mpc5xxx_gpio *gpio =
	291	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	292	return !!(in_8(&gpio->sint_ival) & TWS_DATA);
293	}
294
295	static inline void tws_data_config_output(unsigned output)
296	{
297	struct mpc5xxx_gpio *gpio =
298	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
299	if (output)
300	setbits_8(&gpio->sint_ddr, TWS_DATA);
301	else
302	clrbits_8(&gpio->sint_ddr, TWS_DATA);
303	}
304	#endif /* TWS_IMPLEMENTATION */
138ff60c WD	305
	306	/*
	307	* Miscellaneous configurable options
	308	*/
6d0f6bcf	309	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1d2c6bc4	310	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	311	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
138ff60c	312	#else
6d0f6bcf	313	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
138ff60c	314	#endif
6d0f6bcf JCPV	315	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	316	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	317	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
138ff60c	318
6d0f6bcf	319	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
1d2c6bc4	320	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	321	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
1d2c6bc4 JL	322	#endif
1d2c6bc4 JL	323
138ff60c	324	/* Enable an alternate, more extensive memory test */
6d0f6bcf	325	#define CONFIG_SYS_ALT_MEMTEST
138ff60c	326
6d0f6bcf JCPV	327	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	328	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
138ff60c	329
6d0f6bcf	330	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
138ff60c	331
138ff60c WD	332	/*
	333	* Various low-level settings
	334	*/
6d0f6bcf JCPV	335	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	336	#define CONFIG_SYS_HID0_FINAL HID0_ICE
138ff60c	337
6d0f6bcf JCPV	338	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	339	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	340	#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
	341	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	342	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
138ff60c	343
e58cf2a0	344	/* 32Mbit SRAM @0x30000000 */
6d0f6bcf JCPV	345	#define CONFIG_SYS_CS1_START 0x30000000
	346	#define CONFIG_SYS_CS1_SIZE 0x00400000
	347	#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
e58cf2a0 WD	348
e58cf2a0 WD	349	/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
6d0f6bcf JCPV	350	#define CONFIG_SYS_CS2_START 0x80000000
	351	#define CONFIG_SYS_CS2_SIZE 0x0001000
	352	#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
e58cf2a0	353
f4733a07	354	/* GPIO in @0x30400000 */
6d0f6bcf JCPV	355	#define CONFIG_SYS_CS3_START 0x30400000
	356	#define CONFIG_SYS_CS3_SIZE 0x00100000
	357	#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
f4733a07	358
6d0f6bcf JCPV	359	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	360	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
138ff60c	361
436be29c WD	362	/*-----------------------------------------------------------------------
	363	* USB stuff
	364	*-----------------------------------------------------------------------
	365	*/
	366	#define CONFIG_USB_OHCI
151ab83a WD	367	#define CONFIG_USB_CLOCK 0x00015555
151ab83a WD	368	#define CONFIG_USB_CONFIG 0x00001000
436be29c	369
b05dcb58 WD	370	/*-----------------------------------------------------------------------
	371	* IDE/ATA stuff Supports IDE harddisk
	372	*-----------------------------------------------------------------------
	373	*/
	374
	375	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	376
	377	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	378	#undef CONFIG_IDE_LED /* LED for ide not supported */
	379
b05dcb58 WD	380	#define CONFIG_IDE_PREINIT
b05dcb58 WD	381
6d0f6bcf JCPV	382	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	383	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
b05dcb58	384
6d0f6bcf JCPV	385	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	386	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	387	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
	388	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
	389	#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
	390	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
b05dcb58 WD	391
b05dcb58 WD	392	#define CONFIG_ATAPI 1
1806c759	393
6d0f6bcf	394	#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
b05dcb58	395
138ff60c	396	#endif /* __CONFIG_H */