include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2009
   3  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4  *
   5  * (C) Copyright 2003-2005
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  20 #define CONFIG_INKA4X0          1       /* INKA4x0 board                */
  21
  22 /*
  23  * Valid values for CONFIG_SYS_TEXT_BASE are:
  24  * 0xFFE00000   boot low
  25  * 0x00100000   boot from RAM (for testing only)
  26  */
  27 #ifndef CONFIG_SYS_TEXT_BASE
  28 #define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  29 #endif
  30 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  31
  32 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  33
  34 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  35
  36 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  37
  38 /*
  39  * Serial console configuration
  40  */
  41 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  42 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  43 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  44
  45 /*
  46  * PCI Mapping:
  47  * 0x40000000 - 0x4fffffff - PCI Memory
  48  * 0x50000000 - 0x50ffffff - PCI IO Space
  49  */
  50 #define CONFIG_PCI_SCAN_SHOW    1
  51 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  52
  53 #define CONFIG_PCI_MEM_BUS      0x40000000
  54 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  55 #define CONFIG_PCI_MEM_SIZE     0x10000000
  56
  57 #define CONFIG_PCI_IO_BUS       0x50000000
  58 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  59 #define CONFIG_PCI_IO_SIZE      0x01000000
  60
  61 #define CONFIG_SYS_XLB_PIPELINING       1
  62
  63 /* Partitions */
  64 #define CONFIG_MAC_PARTITION
  65 #define CONFIG_DOS_PARTITION
  66 #define CONFIG_ISO_PARTITION
  67
  68 /*
  69  * BOOTP options
  70  */
  71 #define CONFIG_BOOTP_BOOTFILESIZE
  72 #define CONFIG_BOOTP_BOOTPATH
  73 #define CONFIG_BOOTP_GATEWAY
  74 #define CONFIG_BOOTP_HOSTNAME
  75
  76 /*
  77  * Command line configuration.
  78  */
  79 #define CONFIG_CMD_DATE
  80 #define CONFIG_CMD_IDE
  81 #define CONFIG_CMD_PCI
  82
  83 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  84
  85 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
  86 #   define CONFIG_SYS_LOWBOOT           1
  87 #endif
  88
  89 /*
  90  * Autobooting
  91  */
  92
  93 #define CONFIG_PREBOOT  "echo;" \
  94         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  95         "echo"
  96
  97 #undef  CONFIG_BOOTARGS
  98
  99 #define CONFIG_IPADDR           192.168.100.2
 100 #define CONFIG_SERVERIP         192.168.100.1
 101 #define CONFIG_NETMASK          255.255.255.0
 102 #define HOSTNAME                inka4x0
 103 #define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
 104 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 105
 106 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 107         "netdev=eth0\0"                                                 \
 108         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 109                 "nfsroot=${serverip}:${rootpath}\0"                     \
 110         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 111         "addip=setenv bootargs ${bootargs} "                            \
 112                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 113                 ":${hostname}:${netdev}:off panic=1\0"                  \
 114         "addcons=setenv bootargs ${bootargs} "                          \
 115                 "console=ttyS0,${baudrate}\0"                           \
 116         "flash_nfs=run nfsargs addip addcons;"                          \
 117                 "bootm ${kernel_addr}\0"                                \
 118         "net_nfs=tftp 200000 ${bootfile};"                              \
 119                 "run nfsargs addip addcons;bootm\0"                     \
 120         "enable_disp=mw.l 100000 04000000 1;"                           \
 121                 "cp.l 100000 f0000b20 1;"                               \
 122                 "cp.l 100000 f0000b28 1\0"                              \
 123         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 124         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 125                 "run ideargs addip addcons enable_disp;bootm\0"         \
 126         "brightness=255\0"                                              \
 127         ""
 128
 129 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 130
 131 /*
 132  * IPB Bus clocking configuration.
 133  */
 134 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 135
 136 /*
 137  * Flash configuration
 138  */
 139 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 140 #define CONFIG_FLASH_CFI_DRIVER 1
 141 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 142 #define CONFIG_SYS_FLASH_SIZE           0x00200000
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 144 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 145 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 147
 148 /*
 149  * Environment settings
 150  */
 151 #define CONFIG_ENV_IS_IN_FLASH  1
 152 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 153 #define CONFIG_ENV_SIZE         0x2000
 154 #define CONFIG_ENV_SECT_SIZE    0x2000
 155 #define CONFIG_ENV_OVERWRITE    1
 156 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 157
 158 /*
 159  * Memory map
 160  */
 161 #define CONFIG_SYS_MBAR         0xF0000000
 162 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 163 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 164
 165 /*
 166  * SDRAM controller configuration
 167  */
 168 #undef CONFIG_SDR_MT48LC16M16A2
 169 #undef CONFIG_DDR_MT46V16M16
 170 #undef CONFIG_DDR_MT46V32M16
 171 #undef CONFIG_DDR_HYB25D512160BF
 172 #define CONFIG_DDR_K4H511638C
 173
 174 /* Use ON-Chip SRAM until RAM will be available */
 175 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 176
 177 /* preserve space for the post_word at end of on-chip SRAM */
 178 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 179
 180 #ifdef CONFIG_POST
 181 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 182 #else
 183 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 184 #endif
 185
 186 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 187 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 188
 189 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 190 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 191 #   define CONFIG_SYS_RAMBOOT           1
 192 #endif
 193
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 195 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 196 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 197
 198 /*
 199  * Ethernet configuration
 200  */
 201 #define CONFIG_MPC5xxx_FEC      1
 202 #define CONFIG_MPC5xxx_FEC_MII100
 203 /*
 204  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 205  */
 206 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 207 #define CONFIG_PHY_ADDR         0x00
 208 #define CONFIG_MII
 209
 210 /*
 211  * GPIO configuration
 212  *
 213  * use CS1 as gpio_wkup_6 output
 214  *      Bit 0 (mask: 0x80000000): 0
 215  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 216  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 217  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 218  *            EEPROM
 219  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 220  * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 221  * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 222  * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 223  */
 224 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 225
 226 /*
 227  * RTC configuration
 228  */
 229 #define CONFIG_RTC_RTC4543      1       /* use external RTC */
 230
 231 /*
 232  * Software (bit-bang) three wire serial configuration
 233  *
 234  * Note that we need the ifdefs because otherwise compilation of
 235  * mkimage.c fails.
 236  */
 237 #define CONFIG_SOFT_TWS         1
 238
 239 #ifdef TWS_IMPLEMENTATION
 240 #include <mpc5xxx.h>
 241 #include <asm/io.h>
 242
 243 #define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 244 #define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 245 #define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 246 #define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 247
 248 static inline void tws_ce(unsigned bit)
 249 {
 250         struct mpc5xxx_wu_gpio *wu_gpio =
 251                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 252         if (bit)
 253                 setbits_8(&wu_gpio->dvo, TWS_CE);
 254         else
 255                 clrbits_8(&wu_gpio->dvo, TWS_CE);
 256 }
 257
 258 static inline void tws_wr(unsigned bit)
 259 {
 260         struct mpc5xxx_wu_gpio *wu_gpio =
 261                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 262         if (bit)
 263                 setbits_8(&wu_gpio->dvo, TWS_WR);
 264         else
 265                 clrbits_8(&wu_gpio->dvo, TWS_WR);
 266 }
 267
 268 static inline void tws_clk(unsigned bit)
 269 {
 270         struct mpc5xxx_gpio *gpio =
 271                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 272         if (bit)
 273                 setbits_8(&gpio->sint_dvo, TWS_CLK);
 274         else
 275                 clrbits_8(&gpio->sint_dvo, TWS_CLK);
 276 }
 277
 278 static inline void tws_data(unsigned bit)
 279 {
 280         struct mpc5xxx_gpio *gpio =
 281                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 282         if (bit)
 283                 setbits_8(&gpio->sint_dvo, TWS_DATA);
 284         else
 285                 clrbits_8(&gpio->sint_dvo, TWS_DATA);
 286 }
 287
 288 static inline unsigned tws_data_read(void)
 289 {
 290         struct mpc5xxx_gpio *gpio =
 291                         (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 292         return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 293 }
 294
 295 static inline void tws_data_config_output(unsigned output)
 296 {
 297         struct mpc5xxx_gpio *gpio =
 298                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 299         if (output)
 300                 setbits_8(&gpio->sint_ddr, TWS_DATA);
 301         else
 302                 clrbits_8(&gpio->sint_ddr, TWS_DATA);
 303 }
 304 #endif /* TWS_IMPLEMENTATION */
 305
 306 /*
 307  * Miscellaneous configurable options
 308  */
 309 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 310 #if defined(CONFIG_CMD_KGDB)
 311 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 312 #else
 313 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 314 #endif
 315 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 316 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 317 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 318
 319 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 320 #if defined(CONFIG_CMD_KGDB)
 321 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 322 #endif
 323
 324 /* Enable an alternate, more extensive memory test */
 325 #define CONFIG_SYS_ALT_MEMTEST
 326
 327 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 328 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 329
 330 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 331
 332 /*
 333  * Various low-level settings
 334  */
 335 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 336 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 337
 338 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 339 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 340 #define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 341 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 342 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 343
 344 /* 32Mbit SRAM @0x30000000 */
 345 #define CONFIG_SYS_CS1_START            0x30000000
 346 #define CONFIG_SYS_CS1_SIZE             0x00400000
 347 #define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 348
 349 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 350 #define CONFIG_SYS_CS2_START            0x80000000
 351 #define CONFIG_SYS_CS2_SIZE             0x0001000
 352 #define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 353
 354 /* GPIO in @0x30400000 */
 355 #define CONFIG_SYS_CS3_START            0x30400000
 356 #define CONFIG_SYS_CS3_SIZE             0x00100000
 357 #define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 358
 359 #define CONFIG_SYS_CS_BURST             0x00000000
 360 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 361
 362 /*-----------------------------------------------------------------------
 363  * USB stuff
 364  *-----------------------------------------------------------------------
 365  */
 366 #define CONFIG_USB_OHCI
 367 #define CONFIG_USB_CLOCK        0x00015555
 368 #define CONFIG_USB_CONFIG       0x00001000
 369
 370 /*-----------------------------------------------------------------------
 371  * IDE/ATA stuff Supports IDE harddisk
 372  *-----------------------------------------------------------------------
 373  */
 374
 375 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 376
 377 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 378 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 379
 380 #define CONFIG_IDE_PREINIT
 381
 382 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 383 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 384
 385 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 386 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 387 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 388 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 389 #define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 390 #define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 391
 392 #define CONFIG_ATAPI            1
 393
 394 #define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 395
 396 #endif /* __CONFIG_H */