[people/ms/u-boot.git] / include / configs / inka4x0.h

/*
 * (C) Copyright 2009
 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_INKA4X0		1	/* INKA4x0 board			*/

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFE00000	boot low
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFE00000	/* Standard: boot low */
#endif
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/

#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_ETHADDR		00:a0:a4:03:00:00
#define	CONFIG_OVERWRITE_ETHADDR_ONCE

#define	CONFIG_IPADDR		192.168.100.2
#define	CONFIG_SERVERIP		192.168.100.1
#define	CONFIG_NETMASK		255.255.255.0
#define HOSTNAME		inka4x0
#define CONFIG_BOOTFILE		"/tftpboot/inka4x0/uImage"
#define	CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"enable_disp=mw.l 100000 04000000 1;"				\
		"cp.l 100000 f0000b20 1;"				\
		"cp.l 100000 f0000b28 1\0"				\
	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
		"run ideargs addip addcons enable_disp;bootm\0"		\
	"brightness=255\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run ide_boot"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_BASE		0xffe00000
#define CONFIG_SYS_FLASH_SIZE		0x00200000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/*
 * SDRAM controller configuration
 */
#undef CONFIG_SDR_MT48LC16M16A2
#undef CONFIG_DDR_MT46V16M16
#undef CONFIG_DDR_MT46V32M16
#undef CONFIG_DDR_HYB25D512160BF
#define CONFIG_DDR_K4H511638C

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM

/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)

#ifdef CONFIG_POST
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII

/*
 * GPIO configuration
 *
 * use CS1 as gpio_wkup_6 output
 *	Bit 0 (mask: 0x80000000): 0
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 *	      EEPROM
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01501444

/*
 * RTC configuration
 */
#define CONFIG_RTC_RTC4543 	1	/* use external RTC */

/*
 * Software (bit-bang) three wire serial configuration
 *
 * Note that we need the ifdefs because otherwise compilation of
 * mkimage.c fails.
 */
#define CONFIG_SOFT_TWS		1

#ifdef TWS_IMPLEMENTATION
#include <mpc5xxx.h>
#include <asm/io.h>

#define TWS_CE		MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
#define TWS_WR		MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
#define TWS_DATA	MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
#define TWS_CLK		MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */

static inline void tws_ce(unsigned bit)
{
	struct mpc5xxx_wu_gpio *wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	if (bit)
		setbits_8(&wu_gpio->dvo, TWS_CE);
	else
		clrbits_8(&wu_gpio->dvo, TWS_CE);
}

static inline void tws_wr(unsigned bit)
{
	struct mpc5xxx_wu_gpio *wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	if (bit)
		setbits_8(&wu_gpio->dvo, TWS_WR);
	else
		clrbits_8(&wu_gpio->dvo, TWS_WR);
}

static inline void tws_clk(unsigned bit)
{
	struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	if (bit)
		setbits_8(&gpio->sint_dvo, TWS_CLK);
	else
		clrbits_8(&gpio->sint_dvo, TWS_CLK);
}

static inline void tws_data(unsigned bit)
{
	struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	if (bit)
		setbits_8(&gpio->sint_dvo, TWS_DATA);
	else
		clrbits_8(&gpio->sint_dvo, TWS_DATA);
}

static inline unsigned tws_data_read(void)
{
	struct mpc5xxx_gpio *gpio =
			(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	return !!(in_8(&gpio->sint_ival) & TWS_DATA);
}

static inline void tws_data_config_output(unsigned output)
{
	struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	if (output)
		setbits_8(&gpio->sint_ddr, TWS_DATA);
	else
		clrbits_8(&gpio->sint_ddr, TWS_DATA);
}
#endif /* TWS_IMPLEMENTATION */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* 32Mbit SRAM @0x30000000 */
#define CONFIG_SYS_CS1_START		0x30000000
#define CONFIG_SYS_CS1_SIZE		0x00400000
#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */

/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CONFIG_SYS_CS2_START		0x80000000
#define CONFIG_SYS_CS2_SIZE		0x0001000
#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */

/* GPIO in @0x30400000 */
#define CONFIG_SYS_CS3_START		0x30400000
#define CONFIG_SYS_CS3_SIZE		0x00100000
#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_OHCI
#define CONFIG_USB_CLOCK	0x00015555
#define CONFIG_USB_CONFIG	0x00001000
#define CONFIG_USB_STORAGE

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/

#define CONFIG_ATAPI            1

#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */

#endif /* __CONFIG_H */
Commit	Line	Data
138ff60c	1	/*
e979e85f DZ	2	* (C) Copyright 2009
	3	* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
	4	*
414eec35	5	* (C) Copyright 2003-2005
138ff60c WD	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
138ff60c WD	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
138ff60c WD	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	* (easy to change)
	17	*/
	18
151ab83a WD	19	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	20	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	21	#define CONFIG_INKA4X0 1 /* INKA4x0 board */
138ff60c	22
2ae18241 WD	23	/*
	24	* Valid values for CONFIG_SYS_TEXT_BASE are:
	25	* 0xFFE00000 boot low
	26	* 0x00100000 boot from RAM (for testing only)
	27	*/
	28	#ifndef CONFIG_SYS_TEXT_BASE
	29	#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
	30	#endif
2ced53e1	31	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
2ae18241	32
6d0f6bcf	33	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
138ff60c	34
151ab83a WD	35	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
151ab83a WD	36
31d82672 BB	37	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	38
138ff60c WD	39	/*
	40	* Serial console configuration
	41	*/
151ab83a WD	42	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
151ab83a WD	43	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
138ff60c	45
436be29c WD	46	/*
	47	* PCI Mapping:
	48	* 0x40000000 - 0x4fffffff - PCI Memory
	49	* 0x50000000 - 0x50ffffff - PCI IO Space
	50	*/
	51	#define CONFIG_PCI 1
	52	#define CONFIG_PCI_PNP 1
	53	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	54	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
436be29c WD	55
	56	#define CONFIG_PCI_MEM_BUS 0x40000000
	57	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	58	#define CONFIG_PCI_MEM_SIZE 0x10000000
	59
	60	#define CONFIG_PCI_IO_BUS 0x50000000
	61	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	62	#define CONFIG_PCI_IO_SIZE 0x01000000
	63
6d0f6bcf	64	#define CONFIG_SYS_XLB_PIPELINING 1
436be29c WD	65
	66	/* Partitions */
	67	#define CONFIG_MAC_PARTITION
	68	#define CONFIG_DOS_PARTITION
	69	#define CONFIG_ISO_PARTITION
	70
1d2c6bc4	71
7f5c0157 JL	72	/*
	73	* BOOTP options
	74	*/
	75	#define CONFIG_BOOTP_BOOTFILESIZE
	76	#define CONFIG_BOOTP_BOOTPATH
	77	#define CONFIG_BOOTP_GATEWAY
	78	#define CONFIG_BOOTP_HOSTNAME
	79
	80
138ff60c	81	/*
1d2c6bc4	82	* Command line configuration.
138ff60c	83	*/
1d2c6bc4 JL	84	#include <config_cmd_default.h>
1d2c6bc4 JL	85
e979e85f	86	#define CONFIG_CMD_DATE
1d2c6bc4 JL	87	#define CONFIG_CMD_DHCP
	88	#define CONFIG_CMD_EXT2
	89	#define CONFIG_CMD_FAT
	90	#define CONFIG_CMD_IDE
	91	#define CONFIG_CMD_NFS
	92	#define CONFIG_CMD_PCI
e979e85f	93	#define CONFIG_CMD_PING
1d2c6bc4 JL	94	#define CONFIG_CMD_SNTP
	95	#define CONFIG_CMD_USB
	96
b05dcb58 WD	97	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
b05dcb58 WD	98
14d0a02a	99	#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
6d0f6bcf	100	# define CONFIG_SYS_LOWBOOT 1
138ff60c WD	101	#endif
	102
	103	/*
	104	* Autobooting
	105	*/
84e106c0	106	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
138ff60c WD	107
138ff60c WD	108	#define CONFIG_PREBOOT "echo;" \
32bf3d14	109	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
138ff60c WD	110	"echo"
	111
	112	#undef CONFIG_BOOTARGS
	113
84e106c0 WD	114	#define CONFIG_ETHADDR 00:a0:a4:03:00:00
	115	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	116
	117	#define CONFIG_IPADDR 192.168.100.2
	118	#define CONFIG_SERVERIP 192.168.100.1
	119	#define CONFIG_NETMASK 255.255.255.0
	120	#define HOSTNAME inka4x0
b3f44c21	121	#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
8b3637c6	122	#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
84e106c0	123
138ff60c WD	124	#define CONFIG_EXTRA_ENV_SETTINGS \
	125	"netdev=eth0\0" \
	126	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	127	"nfsroot=${serverip}:${rootpath}\0" \
138ff60c	128	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	129	"addip=setenv bootargs ${bootargs} " \
	130	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	131	":${hostname}:${netdev}:off panic=1\0" \
84e106c0 WD	132	"addcons=setenv bootargs ${bootargs} " \
	133	"console=ttyS0,${baudrate}\0" \
	134	"flash_nfs=run nfsargs addip addcons;" \
fe126d8b	135	"bootm ${kernel_addr}\0" \
84e106c0 WD	136	"net_nfs=tftp 200000 ${bootfile};" \
	137	"run nfsargs addip addcons;bootm\0" \
	138	"enable_disp=mw.l 100000 04000000 1;" \
	139	"cp.l 100000 f0000b20 1;" \
	140	"cp.l 100000 f0000b28 1\0" \
	141	"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
	142	"ide_boot=ext2load ide 0:1 200000 uImage;" \
f23cb34c	143	"run ideargs addip addcons enable_disp;bootm\0" \
84e106c0	144	"brightness=255\0" \
138ff60c WD	145	""
138ff60c WD	146
84e106c0	147	#define CONFIG_BOOTCOMMAND "run ide_boot"
138ff60c WD	148
	149	/*
	150	* IPB Bus clocking configuration.
	151	*/
6d0f6bcf	152	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
138ff60c WD	153
	154	/*
	155	* Flash configuration
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	158	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	159	#define CONFIG_SYS_FLASH_BASE 0xffe00000
	160	#define CONFIG_SYS_FLASH_SIZE 0x00200000
	161	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	162	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	163	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	164	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
138ff60c WD	165
	166	/*
	167	* Environment settings
	168	*/
5a1aceb0	169	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	170	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586 JCPV	171	#define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	172	#define CONFIG_ENV_SECT_SIZE 0x2000
138ff60c	173	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf	174	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
138ff60c WD	175
	176	/*
	177	* Memory map
	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_MBAR 0xF0000000
	180	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	181	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
138ff60c	182
5fb6d719 MB	183	/*
	184	* SDRAM controller configuration
	185	*/
	186	#undef CONFIG_SDR_MT48LC16M16A2
	187	#undef CONFIG_DDR_MT46V16M16
	188	#undef CONFIG_DDR_MT46V32M16
	189	#undef CONFIG_DDR_HYB25D512160BF
	190	#define CONFIG_DDR_K4H511638C
138ff60c WD	191
138ff60c WD	192	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	193	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
800eb096	194
138ff60c	195	/* preserve space for the post_word at end of on-chip SRAM */
800eb096 MZ	196	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
	197
	198	#ifdef CONFIG_POST
553f0982	199	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
138ff60c	200	#else
553f0982	201	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
138ff60c WD	202	#endif
138ff60c WD	203
25ddd1fb	204	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	205	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
138ff60c	206
14d0a02a	207	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	208	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	209	# define CONFIG_SYS_RAMBOOT 1
138ff60c WD	210	#endif
138ff60c WD	211
6d0f6bcf JCPV	212	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	213	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	214	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
138ff60c WD	215
	216	/*
	217	* Ethernet configuration
	218	*/
	219	#define CONFIG_MPC5xxx_FEC 1
86321fc1	220	#define CONFIG_MPC5xxx_FEC_MII100
138ff60c	221	/*
86321fc1	222	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
138ff60c	223	*/
86321fc1	224	/* #define CONFIG_MPC5xxx_FEC_MII10 */
138ff60c	225	#define CONFIG_PHY_ADDR 0x00
84e106c0	226	#define CONFIG_MII
138ff60c WD	227
	228	/*
	229	* GPIO configuration
	230	*
9f709b6c WD	231	* use CS1 as gpio_wkup_6 output
9f709b6c WD	232	* Bit 0 (mask: 0x80000000): 0
138ff60c WD	233	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	234	* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
	235	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
	236	* EEPROM
	237	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
e979e85f DZ	238	* use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
	239	* use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
	240	* use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
138ff60c	241	*/
e979e85f	242	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
138ff60c WD	243
	244	/*
	245	* RTC configuration
	246	*/
e979e85f DZ	247	#define CONFIG_RTC_RTC4543 1 /* use external RTC */
	248
	249	/*
	250	* Software (bit-bang) three wire serial configuration
	251	*
	252	* Note that we need the ifdefs because otherwise compilation of
	253	* mkimage.c fails.
	254	*/
	255	#define CONFIG_SOFT_TWS 1
	256
	257	#ifdef TWS_IMPLEMENTATION
	258	#include <mpc5xxx.h>
	259	#include <asm/io.h>
	260
	261	#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
	262	#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
	263	#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
	264	#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
	265
	266	static inline void tws_ce(unsigned bit)
	267	{
	268	struct mpc5xxx_wu_gpio *wu_gpio =
	269	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	270	if (bit)
	271	setbits_8(&wu_gpio->dvo, TWS_CE);
	272	else
	273	clrbits_8(&wu_gpio->dvo, TWS_CE);
	274	}
	275
	276	static inline void tws_wr(unsigned bit)
	277	{
	278	struct mpc5xxx_wu_gpio *wu_gpio =
	279	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	280	if (bit)
	281	setbits_8(&wu_gpio->dvo, TWS_WR);
	282	else
	283	clrbits_8(&wu_gpio->dvo, TWS_WR);
	284	}
	285
	286	static inline void tws_clk(unsigned bit)
	287	{
	288	struct mpc5xxx_gpio *gpio =
	289	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	290	if (bit)
	291	setbits_8(&gpio->sint_dvo, TWS_CLK);
	292	else
	293	clrbits_8(&gpio->sint_dvo, TWS_CLK);
	294	}
	295
	296	static inline void tws_data(unsigned bit)
	297	{
	298	struct mpc5xxx_gpio *gpio =
	299	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	300	if (bit)
	301	setbits_8(&gpio->sint_dvo, TWS_DATA);
	302	else
	303	clrbits_8(&gpio->sint_dvo, TWS_DATA);
	304	}
	305
	306	static inline unsigned tws_data_read(void)
	307	{
	308	struct mpc5xxx_gpio *gpio =
	309	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	310	return !!(in_8(&gpio->sint_ival) & TWS_DATA);
311	}
312
313	static inline void tws_data_config_output(unsigned output)
314	{
315	struct mpc5xxx_gpio *gpio =
316	(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
317	if (output)
318	setbits_8(&gpio->sint_ddr, TWS_DATA);
319	else
320	clrbits_8(&gpio->sint_ddr, TWS_DATA);
321	}
322	#endif /* TWS_IMPLEMENTATION */
138ff60c WD	323
	324	/*
	325	* Miscellaneous configurable options
	326	*/
6d0f6bcf	327	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1d2c6bc4	328	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	329	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
138ff60c	330	#else
6d0f6bcf	331	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
138ff60c	332	#endif
6d0f6bcf JCPV	333	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	334	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	335	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
138ff60c	336
6d0f6bcf	337	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
1d2c6bc4	338	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	339	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
1d2c6bc4 JL	340	#endif
1d2c6bc4 JL	341
138ff60c	342	/* Enable an alternate, more extensive memory test */
6d0f6bcf	343	#define CONFIG_SYS_ALT_MEMTEST
138ff60c	344
6d0f6bcf JCPV	345	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	346	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
138ff60c	347
6d0f6bcf	348	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
138ff60c	349
138ff60c	350	/*
7f5c0157	351	* Enable loopw command.
138ff60c WD	352	*/
	353	#define CONFIG_LOOPW
	354
	355	/*
	356	* Various low-level settings
	357	*/
6d0f6bcf JCPV	358	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	359	#define CONFIG_SYS_HID0_FINAL HID0_ICE
138ff60c	360
6d0f6bcf JCPV	361	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	362	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	363	#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
	364	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	365	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
138ff60c	366
e58cf2a0	367	/* 32Mbit SRAM @0x30000000 */
6d0f6bcf JCPV	368	#define CONFIG_SYS_CS1_START 0x30000000
	369	#define CONFIG_SYS_CS1_SIZE 0x00400000
	370	#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
e58cf2a0 WD	371
e58cf2a0 WD	372	/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
6d0f6bcf JCPV	373	#define CONFIG_SYS_CS2_START 0x80000000
	374	#define CONFIG_SYS_CS2_SIZE 0x0001000
	375	#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
e58cf2a0	376
f4733a07	377	/* GPIO in @0x30400000 */
6d0f6bcf JCPV	378	#define CONFIG_SYS_CS3_START 0x30400000
	379	#define CONFIG_SYS_CS3_SIZE 0x00100000
	380	#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
f4733a07	381
6d0f6bcf JCPV	382	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	383	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
138ff60c	384
436be29c WD	385	/*-----------------------------------------------------------------------
	386	* USB stuff
	387	*-----------------------------------------------------------------------
	388	*/
	389	#define CONFIG_USB_OHCI
151ab83a WD	390	#define CONFIG_USB_CLOCK 0x00015555
151ab83a WD	391	#define CONFIG_USB_CONFIG 0x00001000
1968e615	392	#define CONFIG_USB_STORAGE
436be29c	393
b05dcb58 WD	394	/*-----------------------------------------------------------------------
	395	* IDE/ATA stuff Supports IDE harddisk
	396	*-----------------------------------------------------------------------
	397	*/
	398
	399	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	400
	401	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	402	#undef CONFIG_IDE_LED /* LED for ide not supported */
	403
b05dcb58 WD	404	#define CONFIG_IDE_PREINIT
b05dcb58 WD	405
6d0f6bcf JCPV	406	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	407	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
b05dcb58	408
6d0f6bcf JCPV	409	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	410	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	411	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
	412	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
	413	#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
	414	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
b05dcb58 WD	415
b05dcb58 WD	416	#define CONFIG_ATAPI 1
1806c759	417
6d0f6bcf	418	#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
b05dcb58	419
138ff60c	420	#endif /* __CONFIG_H */